1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 33 /* VA hole for 48bit addresses on Vega10 */ 34 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL 35 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL 36 37 /* 38 * Hardware is programmed as if the hole doesn't exists with start and end 39 * address values. 40 * 41 * This mask is used to remove the upper 16bits of the VA and so come up with 42 * the linear addr value. 43 */ 44 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL 45 46 /* 47 * Ring size as power of two for the log of recent faults. 48 */ 49 #define AMDGPU_GMC_FAULT_RING_ORDER 8 50 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 51 52 /* 53 * Hash size as power of two for the log of recent faults 54 */ 55 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 56 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 57 58 /* 59 * Number of IH timestamp ticks until a fault is considered handled 60 */ 61 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 62 63 struct firmware; 64 65 /* 66 * GMC page fault information 67 */ 68 struct amdgpu_gmc_fault { 69 uint64_t timestamp; 70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 71 uint64_t key:52; 72 }; 73 74 /* 75 * VMHUB structures, functions & helpers 76 */ 77 struct amdgpu_vmhub { 78 uint32_t ctx0_ptb_addr_lo32; 79 uint32_t ctx0_ptb_addr_hi32; 80 uint32_t vm_inv_eng0_req; 81 uint32_t vm_inv_eng0_ack; 82 uint32_t vm_context0_cntl; 83 uint32_t vm_l2_pro_fault_status; 84 uint32_t vm_l2_pro_fault_cntl; 85 }; 86 87 /* 88 * GPU MC structures, functions & helpers 89 */ 90 struct amdgpu_gmc_funcs { 91 /* flush the vm tlb via mmio */ 92 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 93 uint32_t vmhub, uint32_t flush_type); 94 /* flush the vm tlb via ring */ 95 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 96 uint64_t pd_addr); 97 /* Change the VMID -> PASID mapping */ 98 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 99 unsigned pasid); 100 /* enable/disable PRT support */ 101 void (*set_prt)(struct amdgpu_device *adev, bool enable); 102 /* map mtype to hardware flags */ 103 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags); 104 /* get the pde for a given mc addr */ 105 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 106 u64 *dst, u64 *flags); 107 /* get the pte flags to use for a BO VA mapping */ 108 void (*get_vm_pte)(struct amdgpu_device *adev, 109 struct amdgpu_bo_va_mapping *mapping, 110 uint64_t *flags); 111 }; 112 113 struct amdgpu_xgmi { 114 /* from psp */ 115 u64 node_id; 116 u64 hive_id; 117 /* fixed per family */ 118 u64 node_segment_size; 119 /* physical node (0-3) */ 120 unsigned physical_node_id; 121 /* number of nodes (0-4) */ 122 unsigned num_physical_nodes; 123 /* gpu list in the same hive */ 124 struct list_head head; 125 bool supported; 126 struct ras_common_if *ras_if; 127 }; 128 129 struct amdgpu_gmc { 130 resource_size_t aper_size; 131 resource_size_t aper_base; 132 /* for some chips with <= 32MB we need to lie 133 * about vram size near mc fb location */ 134 u64 mc_vram_size; 135 u64 visible_vram_size; 136 u64 agp_size; 137 u64 agp_start; 138 u64 agp_end; 139 u64 gart_size; 140 u64 gart_start; 141 u64 gart_end; 142 u64 vram_start; 143 u64 vram_end; 144 /* FB region , it's same as local vram region in single GPU, in XGMI 145 * configuration, this region covers all GPUs in the same hive , 146 * each GPU in the hive has the same view of this FB region . 147 * GPU0's vram starts at offset (0 * segment size) , 148 * GPU1 starts at offset (1 * segment size), etc. 149 */ 150 u64 fb_start; 151 u64 fb_end; 152 unsigned vram_width; 153 u64 real_vram_size; 154 int vram_mtrr; 155 u64 mc_mask; 156 const struct firmware *fw; /* MC firmware */ 157 uint32_t fw_version; 158 struct amdgpu_irq_src vm_fault; 159 uint32_t vram_type; 160 uint8_t vram_vendor; 161 uint32_t srbm_soft_reset; 162 bool prt_warning; 163 uint64_t stolen_size; 164 /* apertures */ 165 u64 shared_aperture_start; 166 u64 shared_aperture_end; 167 u64 private_aperture_start; 168 u64 private_aperture_end; 169 /* protects concurrent invalidation */ 170 spinlock_t invalidate_lock; 171 bool translate_further; 172 struct kfd_vm_fault_info *vm_fault_info; 173 atomic_t vm_fault_info_updated; 174 175 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 176 struct { 177 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 178 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 179 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 180 181 const struct amdgpu_gmc_funcs *gmc_funcs; 182 183 struct amdgpu_xgmi xgmi; 184 struct amdgpu_irq_src ecc_irq; 185 }; 186 187 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type))) 188 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 189 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 190 #define amdgpu_gmc_map_mtype(adev, flags) (adev)->gmc.gmc_funcs->map_mtype((adev),(flags)) 191 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 192 #define amdgpu_gmc_get_vm_pte(adev, mapping, flags) (adev)->gmc.gmc_funcs->get_vm_pte((adev), (mapping), (flags)) 193 194 /** 195 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 196 * 197 * @adev: amdgpu_device pointer 198 * 199 * Returns: 200 * True if full VRAM is visible through the BAR 201 */ 202 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 203 { 204 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 205 206 return (gmc->real_vram_size == gmc->visible_vram_size); 207 } 208 209 /** 210 * amdgpu_gmc_sign_extend - sign extend the given gmc address 211 * 212 * @addr: address to extend 213 */ 214 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) 215 { 216 if (addr >= AMDGPU_GMC_HOLE_START) 217 addr |= AMDGPU_GMC_HOLE_END; 218 219 return addr; 220 } 221 222 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 223 uint64_t *addr, uint64_t *flags); 224 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 225 uint32_t gpu_page_idx, uint64_t addr, 226 uint64_t flags); 227 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 228 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 229 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 230 u64 base); 231 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 232 struct amdgpu_gmc *mc); 233 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 234 struct amdgpu_gmc *mc); 235 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 236 uint16_t pasid, uint64_t timestamp); 237 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 238 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 239 240 #endif 241