1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 33 struct firmware; 34 35 /* 36 * VMHUB structures, functions & helpers 37 */ 38 struct amdgpu_vmhub { 39 uint32_t ctx0_ptb_addr_lo32; 40 uint32_t ctx0_ptb_addr_hi32; 41 uint32_t vm_inv_eng0_req; 42 uint32_t vm_inv_eng0_ack; 43 uint32_t vm_context0_cntl; 44 uint32_t vm_l2_pro_fault_status; 45 uint32_t vm_l2_pro_fault_cntl; 46 }; 47 48 /* 49 * GPU MC structures, functions & helpers 50 */ 51 struct amdgpu_gmc_funcs { 52 /* flush the vm tlb via mmio */ 53 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 54 uint32_t vmid); 55 /* flush the vm tlb via ring */ 56 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 57 unsigned pasid, uint64_t pd_addr); 58 /* write pte/pde updates using the cpu */ 59 int (*set_pte_pde)(struct amdgpu_device *adev, 60 void *cpu_pt_addr, /* cpu addr of page table */ 61 uint32_t gpu_page_idx, /* pte/pde to update */ 62 uint64_t addr, /* addr to write into pte/pde */ 63 uint64_t flags); /* access flags */ 64 /* enable/disable PRT support */ 65 void (*set_prt)(struct amdgpu_device *adev, bool enable); 66 /* set pte flags based per asic */ 67 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 68 uint32_t flags); 69 /* get the pde for a given mc addr */ 70 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 71 u64 *dst, u64 *flags); 72 }; 73 74 struct amdgpu_gmc { 75 resource_size_t aper_size; 76 resource_size_t aper_base; 77 /* for some chips with <= 32MB we need to lie 78 * about vram size near mc fb location */ 79 u64 mc_vram_size; 80 u64 visible_vram_size; 81 u64 gart_size; 82 u64 gart_start; 83 u64 gart_end; 84 u64 vram_start; 85 u64 vram_end; 86 unsigned vram_width; 87 u64 real_vram_size; 88 int vram_mtrr; 89 u64 mc_mask; 90 const struct firmware *fw; /* MC firmware */ 91 uint32_t fw_version; 92 struct amdgpu_irq_src vm_fault; 93 uint32_t vram_type; 94 uint32_t srbm_soft_reset; 95 bool prt_warning; 96 uint64_t stolen_size; 97 /* apertures */ 98 u64 shared_aperture_start; 99 u64 shared_aperture_end; 100 u64 private_aperture_start; 101 u64 private_aperture_end; 102 /* protects concurrent invalidation */ 103 spinlock_t invalidate_lock; 104 bool translate_further; 105 106 const struct amdgpu_gmc_funcs *gmc_funcs; 107 }; 108 109 #endif 110