1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_gmc.h" 31 #include "amdgpu_ras.h" 32 #include "amdgpu_xgmi.h" 33 34 /** 35 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 36 * 37 * @adev: amdgpu_device pointer 38 * 39 * Allocate video memory for pdb0 and map it for CPU access 40 * Returns 0 for success, error for failure. 41 */ 42 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 43 { 44 int r; 45 struct amdgpu_bo_param bp; 46 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 47 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 48 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 49 50 memset(&bp, 0, sizeof(bp)); 51 bp.size = PAGE_ALIGN((npdes + 1) * 8); 52 bp.byte_align = PAGE_SIZE; 53 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 54 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 55 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 56 bp.type = ttm_bo_type_kernel; 57 bp.resv = NULL; 58 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 59 60 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 61 if (r) 62 return r; 63 64 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 65 if (unlikely(r != 0)) 66 goto bo_reserve_failure; 67 68 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 69 if (r) 70 goto bo_pin_failure; 71 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 72 if (r) 73 goto bo_kmap_failure; 74 75 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 76 return 0; 77 78 bo_kmap_failure: 79 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 80 bo_pin_failure: 81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 82 bo_reserve_failure: 83 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 84 return r; 85 } 86 87 /** 88 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 89 * 90 * @bo: the BO to get the PDE for 91 * @level: the level in the PD hirarchy 92 * @addr: resulting addr 93 * @flags: resulting flags 94 * 95 * Get the address and flags to be used for a PDE (Page Directory Entry). 96 */ 97 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 98 uint64_t *addr, uint64_t *flags) 99 { 100 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 101 102 switch (bo->tbo.mem.mem_type) { 103 case TTM_PL_TT: 104 *addr = bo->tbo.ttm->dma_address[0]; 105 break; 106 case TTM_PL_VRAM: 107 *addr = amdgpu_bo_gpu_offset(bo); 108 break; 109 default: 110 *addr = 0; 111 break; 112 } 113 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem); 114 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 115 } 116 117 /* 118 * amdgpu_gmc_pd_addr - return the address of the root directory 119 */ 120 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 121 { 122 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 123 uint64_t pd_addr; 124 125 /* TODO: move that into ASIC specific code */ 126 if (adev->asic_type >= CHIP_VEGA10) { 127 uint64_t flags = AMDGPU_PTE_VALID; 128 129 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 130 pd_addr |= flags; 131 } else { 132 pd_addr = amdgpu_bo_gpu_offset(bo); 133 } 134 return pd_addr; 135 } 136 137 /** 138 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 139 * 140 * @adev: amdgpu_device pointer 141 * @cpu_pt_addr: cpu address of the page table 142 * @gpu_page_idx: entry in the page table to update 143 * @addr: dst addr to write into pte/pde 144 * @flags: access flags 145 * 146 * Update the page tables using CPU. 147 */ 148 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 149 uint32_t gpu_page_idx, uint64_t addr, 150 uint64_t flags) 151 { 152 void __iomem *ptr = (void *)cpu_pt_addr; 153 uint64_t value; 154 155 /* 156 * The following is for PTE only. GART does not have PDEs. 157 */ 158 value = addr & 0x0000FFFFFFFFF000ULL; 159 value |= flags; 160 writeq(value, ptr + (gpu_page_idx * 8)); 161 return 0; 162 } 163 164 /** 165 * amdgpu_gmc_agp_addr - return the address in the AGP address space 166 * 167 * @bo: TTM BO which needs the address, must be in GTT domain 168 * 169 * Tries to figure out how to access the BO through the AGP aperture. Returns 170 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 171 */ 172 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 173 { 174 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 175 176 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 177 return AMDGPU_BO_INVALID_OFFSET; 178 179 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 180 return AMDGPU_BO_INVALID_OFFSET; 181 182 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 183 } 184 185 /** 186 * amdgpu_gmc_vram_location - try to find VRAM location 187 * 188 * @adev: amdgpu device structure holding all necessary information 189 * @mc: memory controller structure holding memory information 190 * @base: base address at which to put VRAM 191 * 192 * Function will try to place VRAM at base address provided 193 * as parameter. 194 */ 195 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 196 u64 base) 197 { 198 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 199 200 mc->vram_start = base; 201 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 202 if (limit && limit < mc->real_vram_size) 203 mc->real_vram_size = limit; 204 205 if (mc->xgmi.num_physical_nodes == 0) { 206 mc->fb_start = mc->vram_start; 207 mc->fb_end = mc->vram_end; 208 } 209 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 210 mc->mc_vram_size >> 20, mc->vram_start, 211 mc->vram_end, mc->real_vram_size >> 20); 212 } 213 214 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 215 * 216 * @adev: amdgpu device structure holding all necessary information 217 * @mc: memory controller structure holding memory information 218 * 219 * This function is only used if use GART for FB translation. In such 220 * case, we use sysvm aperture (vmid0 page tables) for both vram 221 * and gart (aka system memory) access. 222 * 223 * GPUVM (and our organization of vmid0 page tables) require sysvm 224 * aperture to be placed at a location aligned with 8 times of native 225 * page size. For example, if vm_context0_cntl.page_table_block_size 226 * is 12, then native page size is 8G (2M*2^12), sysvm should start 227 * with a 64G aligned address. For simplicity, we just put sysvm at 228 * address 0. So vram start at address 0 and gart is right after vram. 229 */ 230 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 231 { 232 u64 hive_vram_start = 0; 233 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 234 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 235 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 236 mc->gart_start = hive_vram_end + 1; 237 mc->gart_end = mc->gart_start + mc->gart_size - 1; 238 mc->fb_start = hive_vram_start; 239 mc->fb_end = hive_vram_end; 240 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 241 mc->mc_vram_size >> 20, mc->vram_start, 242 mc->vram_end, mc->real_vram_size >> 20); 243 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 244 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 245 } 246 247 /** 248 * amdgpu_gmc_gart_location - try to find GART location 249 * 250 * @adev: amdgpu device structure holding all necessary information 251 * @mc: memory controller structure holding memory information 252 * 253 * Function will place try to place GART before or after VRAM. 254 * If GART size is bigger than space left then we ajust GART size. 255 * Thus function will never fails. 256 */ 257 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 258 { 259 const uint64_t four_gb = 0x100000000ULL; 260 u64 size_af, size_bf; 261 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 262 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 263 264 /* VCE doesn't like it when BOs cross a 4GB segment, so align 265 * the GART base on a 4GB boundary as well. 266 */ 267 size_bf = mc->fb_start; 268 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 269 270 if (mc->gart_size > max(size_bf, size_af)) { 271 dev_warn(adev->dev, "limiting GART\n"); 272 mc->gart_size = max(size_bf, size_af); 273 } 274 275 if ((size_bf >= mc->gart_size && size_bf < size_af) || 276 (size_af < mc->gart_size)) 277 mc->gart_start = 0; 278 else 279 mc->gart_start = max_mc_address - mc->gart_size + 1; 280 281 mc->gart_start &= ~(four_gb - 1); 282 mc->gart_end = mc->gart_start + mc->gart_size - 1; 283 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 284 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 285 } 286 287 /** 288 * amdgpu_gmc_agp_location - try to find AGP location 289 * @adev: amdgpu device structure holding all necessary information 290 * @mc: memory controller structure holding memory information 291 * 292 * Function will place try to find a place for the AGP BAR in the MC address 293 * space. 294 * 295 * AGP BAR will be assigned the largest available hole in the address space. 296 * Should be called after VRAM and GART locations are setup. 297 */ 298 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 299 { 300 const uint64_t sixteen_gb = 1ULL << 34; 301 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 302 u64 size_af, size_bf; 303 304 if (amdgpu_sriov_vf(adev)) { 305 mc->agp_start = 0xffffffffffff; 306 mc->agp_end = 0x0; 307 mc->agp_size = 0; 308 309 return; 310 } 311 312 if (mc->fb_start > mc->gart_start) { 313 size_bf = (mc->fb_start & sixteen_gb_mask) - 314 ALIGN(mc->gart_end + 1, sixteen_gb); 315 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 316 } else { 317 size_bf = mc->fb_start & sixteen_gb_mask; 318 size_af = (mc->gart_start & sixteen_gb_mask) - 319 ALIGN(mc->fb_end + 1, sixteen_gb); 320 } 321 322 if (size_bf > size_af) { 323 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 324 mc->agp_size = size_bf; 325 } else { 326 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 327 mc->agp_size = size_af; 328 } 329 330 mc->agp_end = mc->agp_start + mc->agp_size - 1; 331 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 332 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 333 } 334 335 /** 336 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 337 * 338 * @addr: 48 bit physical address, page aligned (36 significant bits) 339 * @pasid: 16 bit process address space identifier 340 */ 341 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 342 { 343 return addr << 4 | pasid; 344 } 345 346 /** 347 * amdgpu_gmc_filter_faults - filter VM faults 348 * 349 * @adev: amdgpu device structure 350 * @addr: address of the VM fault 351 * @pasid: PASID of the process causing the fault 352 * @timestamp: timestamp of the fault 353 * 354 * Returns: 355 * True if the fault was filtered and should not be processed further. 356 * False if the fault is a new one and needs to be handled. 357 */ 358 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 359 uint16_t pasid, uint64_t timestamp) 360 { 361 struct amdgpu_gmc *gmc = &adev->gmc; 362 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 363 struct amdgpu_gmc_fault *fault; 364 uint32_t hash; 365 366 /* If we don't have space left in the ring buffer return immediately */ 367 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 368 AMDGPU_GMC_FAULT_TIMEOUT; 369 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 370 return true; 371 372 /* Try to find the fault in the hash */ 373 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 374 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 375 while (fault->timestamp >= stamp) { 376 uint64_t tmp; 377 378 if (atomic64_read(&fault->key) == key) 379 return true; 380 381 tmp = fault->timestamp; 382 fault = &gmc->fault_ring[fault->next]; 383 384 /* Check if the entry was reused */ 385 if (fault->timestamp >= tmp) 386 break; 387 } 388 389 /* Add the fault to the ring */ 390 fault = &gmc->fault_ring[gmc->last_fault]; 391 atomic64_set(&fault->key, key); 392 fault->timestamp = timestamp; 393 394 /* And update the hash */ 395 fault->next = gmc->fault_hash[hash].idx; 396 gmc->fault_hash[hash].idx = gmc->last_fault++; 397 return false; 398 } 399 400 /** 401 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 402 * 403 * @adev: amdgpu device structure 404 * @addr: address of the VM fault 405 * @pasid: PASID of the process causing the fault 406 * 407 * Remove the address from fault filter, then future vm fault on this address 408 * will pass to retry fault handler to recover. 409 */ 410 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 411 uint16_t pasid) 412 { 413 struct amdgpu_gmc *gmc = &adev->gmc; 414 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 415 struct amdgpu_gmc_fault *fault; 416 uint32_t hash; 417 uint64_t tmp; 418 419 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 420 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 421 do { 422 if (atomic64_cmpxchg(&fault->key, key, 0) == key) 423 break; 424 425 tmp = fault->timestamp; 426 fault = &gmc->fault_ring[fault->next]; 427 } while (fault->timestamp < tmp); 428 } 429 430 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 431 { 432 int r; 433 434 if (adev->umc.ras_funcs && 435 adev->umc.ras_funcs->ras_late_init) { 436 r = adev->umc.ras_funcs->ras_late_init(adev); 437 if (r) 438 return r; 439 } 440 441 if (adev->mmhub.ras_funcs && 442 adev->mmhub.ras_funcs->ras_late_init) { 443 r = adev->mmhub.ras_funcs->ras_late_init(adev); 444 if (r) 445 return r; 446 } 447 448 if (!adev->gmc.xgmi.connected_to_cpu) 449 adev->gmc.xgmi.ras_funcs = &xgmi_ras_funcs; 450 451 if (adev->gmc.xgmi.ras_funcs && 452 adev->gmc.xgmi.ras_funcs->ras_late_init) { 453 r = adev->gmc.xgmi.ras_funcs->ras_late_init(adev); 454 if (r) 455 return r; 456 } 457 458 if (adev->hdp.ras_funcs && 459 adev->hdp.ras_funcs->ras_late_init) { 460 r = adev->hdp.ras_funcs->ras_late_init(adev); 461 if (r) 462 return r; 463 } 464 465 return 0; 466 } 467 468 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 469 { 470 if (adev->umc.ras_funcs && 471 adev->umc.ras_funcs->ras_fini) 472 adev->umc.ras_funcs->ras_fini(adev); 473 474 if (adev->mmhub.ras_funcs && 475 adev->mmhub.ras_funcs->ras_fini) 476 adev->mmhub.ras_funcs->ras_fini(adev); 477 478 if (adev->gmc.xgmi.ras_funcs && 479 adev->gmc.xgmi.ras_funcs->ras_fini) 480 adev->gmc.xgmi.ras_funcs->ras_fini(adev); 481 482 if (adev->hdp.ras_funcs && 483 adev->hdp.ras_funcs->ras_fini) 484 adev->hdp.ras_funcs->ras_fini(adev); 485 } 486 487 /* 488 * The latest engine allocation on gfx9/10 is: 489 * Engine 2, 3: firmware 490 * Engine 0, 1, 4~16: amdgpu ring, 491 * subject to change when ring number changes 492 * Engine 17: Gart flushes 493 */ 494 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 495 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 496 497 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 498 { 499 struct amdgpu_ring *ring; 500 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 501 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 502 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 503 unsigned i; 504 unsigned vmhub, inv_eng; 505 506 for (i = 0; i < adev->num_rings; ++i) { 507 ring = adev->rings[i]; 508 vmhub = ring->funcs->vmhub; 509 510 if (ring == &adev->mes.ring) 511 continue; 512 513 inv_eng = ffs(vm_inv_engs[vmhub]); 514 if (!inv_eng) { 515 dev_err(adev->dev, "no VM inv eng for ring %s\n", 516 ring->name); 517 return -EINVAL; 518 } 519 520 ring->vm_inv_eng = inv_eng - 1; 521 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 522 523 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 524 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 525 } 526 527 return 0; 528 } 529 530 /** 531 * amdgpu_tmz_set -- check and set if a device supports TMZ 532 * @adev: amdgpu_device pointer 533 * 534 * Check and set if an the device @adev supports Trusted Memory 535 * Zones (TMZ). 536 */ 537 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 538 { 539 switch (adev->asic_type) { 540 case CHIP_RAVEN: 541 case CHIP_RENOIR: 542 if (amdgpu_tmz == 0) { 543 adev->gmc.tmz_enabled = false; 544 dev_info(adev->dev, 545 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 546 } else { 547 adev->gmc.tmz_enabled = true; 548 dev_info(adev->dev, 549 "Trusted Memory Zone (TMZ) feature enabled\n"); 550 } 551 break; 552 case CHIP_NAVI10: 553 case CHIP_NAVI14: 554 case CHIP_NAVI12: 555 case CHIP_VANGOGH: 556 /* Don't enable it by default yet. 557 */ 558 if (amdgpu_tmz < 1) { 559 adev->gmc.tmz_enabled = false; 560 dev_info(adev->dev, 561 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 562 } else { 563 adev->gmc.tmz_enabled = true; 564 dev_info(adev->dev, 565 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 566 } 567 break; 568 default: 569 adev->gmc.tmz_enabled = false; 570 dev_warn(adev->dev, 571 "Trusted Memory Zone (TMZ) feature not supported\n"); 572 break; 573 } 574 } 575 576 /** 577 * amdgpu_noretry_set -- set per asic noretry defaults 578 * @adev: amdgpu_device pointer 579 * 580 * Set a per asic default for the no-retry parameter. 581 * 582 */ 583 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 584 { 585 struct amdgpu_gmc *gmc = &adev->gmc; 586 587 switch (adev->asic_type) { 588 case CHIP_VEGA10: 589 case CHIP_VEGA20: 590 case CHIP_ARCTURUS: 591 case CHIP_ALDEBARAN: 592 /* 593 * noretry = 0 will cause kfd page fault tests fail 594 * for some ASICs, so set default to 1 for these ASICs. 595 */ 596 if (amdgpu_noretry == -1) 597 gmc->noretry = 1; 598 else 599 gmc->noretry = amdgpu_noretry; 600 break; 601 case CHIP_RAVEN: 602 default: 603 /* Raven currently has issues with noretry 604 * regardless of what we decide for other 605 * asics, we should leave raven with 606 * noretry = 0 until we root cause the 607 * issues. 608 * 609 * default this to 0 for now, but we may want 610 * to change this in the future for certain 611 * GPUs as it can increase performance in 612 * certain cases. 613 */ 614 if (amdgpu_noretry == -1) 615 gmc->noretry = 0; 616 else 617 gmc->noretry = amdgpu_noretry; 618 break; 619 } 620 } 621 622 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 623 bool enable) 624 { 625 struct amdgpu_vmhub *hub; 626 u32 tmp, reg, i; 627 628 hub = &adev->vmhub[hub_type]; 629 for (i = 0; i < 16; i++) { 630 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 631 632 tmp = RREG32(reg); 633 if (enable) 634 tmp |= hub->vm_cntx_cntl_vm_fault; 635 else 636 tmp &= ~hub->vm_cntx_cntl_vm_fault; 637 638 WREG32(reg, tmp); 639 } 640 } 641 642 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 643 { 644 unsigned size; 645 646 /* 647 * TODO: 648 * Currently there is a bug where some memory client outside 649 * of the driver writes to first 8M of VRAM on S3 resume, 650 * this overrides GART which by default gets placed in first 8M and 651 * causes VM_FAULTS once GTT is accessed. 652 * Keep the stolen memory reservation until the while this is not solved. 653 */ 654 switch (adev->asic_type) { 655 case CHIP_VEGA10: 656 case CHIP_RAVEN: 657 case CHIP_RENOIR: 658 adev->mman.keep_stolen_vga_memory = true; 659 break; 660 default: 661 adev->mman.keep_stolen_vga_memory = false; 662 break; 663 } 664 665 if (amdgpu_sriov_vf(adev) || 666 !amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) { 667 size = 0; 668 } else { 669 size = amdgpu_gmc_get_vbios_fb_size(adev); 670 671 if (adev->mman.keep_stolen_vga_memory) 672 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 673 } 674 675 /* set to 0 if the pre-OS buffer uses up most of vram */ 676 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 677 size = 0; 678 679 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 680 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 681 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 682 } else { 683 adev->mman.stolen_vga_size = size; 684 adev->mman.stolen_extended_size = 0; 685 } 686 } 687 688 /** 689 * amdgpu_gmc_init_pdb0 - initialize PDB0 690 * 691 * @adev: amdgpu_device pointer 692 * 693 * This function is only used when GART page table is used 694 * for FB address translatioin. In such a case, we construct 695 * a 2-level system VM page table: PDB0->PTB, to cover both 696 * VRAM of the hive and system memory. 697 * 698 * PDB0 is static, initialized once on driver initialization. 699 * The first n entries of PDB0 are used as PTE by setting 700 * P bit to 1, pointing to VRAM. The n+1'th entry points 701 * to a big PTB covering system memory. 702 * 703 */ 704 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 705 { 706 int i; 707 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 708 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 709 */ 710 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 711 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 712 u64 vram_addr = adev->vm_manager.vram_base_offset - 713 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 714 u64 vram_end = vram_addr + vram_size; 715 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 716 717 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 718 flags |= AMDGPU_PTE_WRITEABLE; 719 flags |= AMDGPU_PTE_SNOOPED; 720 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 721 flags |= AMDGPU_PDE_PTE; 722 723 /* The first n PDE0 entries are used as PTE, 724 * pointing to vram 725 */ 726 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 727 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 728 729 /* The n+1'th PDE0 entry points to a huge 730 * PTB who has more than 512 entries each 731 * pointing to a 4K system page 732 */ 733 flags = AMDGPU_PTE_VALID; 734 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 735 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 736 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 737 } 738 739 /** 740 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 741 * address 742 * 743 * @adev: amdgpu_device pointer 744 * @mc_addr: MC address of buffer 745 */ 746 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 747 { 748 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 749 } 750 751 /** 752 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 753 * GPU's view 754 * 755 * @adev: amdgpu_device pointer 756 * @bo: amdgpu buffer object 757 */ 758 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 759 { 760 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 761 } 762 763 /** 764 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address 765 * from CPU's view 766 * 767 * @adev: amdgpu_device pointer 768 * @bo: amdgpu buffer object 769 */ 770 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 771 { 772 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; 773 } 774