1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include "amdgpu.h" 28 29 /** 30 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 31 * 32 * @bo: the BO to get the PDE for 33 * @level: the level in the PD hirarchy 34 * @addr: resulting addr 35 * @flags: resulting flags 36 * 37 * Get the address and flags to be used for a PDE (Page Directory Entry). 38 */ 39 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 40 uint64_t *addr, uint64_t *flags) 41 { 42 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 43 struct ttm_dma_tt *ttm; 44 45 switch (bo->tbo.mem.mem_type) { 46 case TTM_PL_TT: 47 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm); 48 *addr = ttm->dma_address[0]; 49 break; 50 case TTM_PL_VRAM: 51 *addr = amdgpu_bo_gpu_offset(bo); 52 break; 53 default: 54 *addr = 0; 55 break; 56 } 57 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem); 58 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 59 } 60 61 /** 62 * amdgpu_gmc_pd_addr - return the address of the root directory 63 * 64 */ 65 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 66 { 67 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 68 uint64_t pd_addr; 69 70 /* TODO: move that into ASIC specific code */ 71 if (adev->asic_type >= CHIP_VEGA10) { 72 uint64_t flags = AMDGPU_PTE_VALID; 73 74 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 75 pd_addr |= flags; 76 } else { 77 pd_addr = amdgpu_bo_gpu_offset(bo); 78 } 79 return pd_addr; 80 } 81 82 /** 83 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 84 * 85 * @adev: amdgpu_device pointer 86 * @cpu_pt_addr: cpu address of the page table 87 * @gpu_page_idx: entry in the page table to update 88 * @addr: dst addr to write into pte/pde 89 * @flags: access flags 90 * 91 * Update the page tables using CPU. 92 */ 93 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 94 uint32_t gpu_page_idx, uint64_t addr, 95 uint64_t flags) 96 { 97 void __iomem *ptr = (void *)cpu_pt_addr; 98 uint64_t value; 99 100 /* 101 * The following is for PTE only. GART does not have PDEs. 102 */ 103 value = addr & 0x0000FFFFFFFFF000ULL; 104 value |= flags; 105 writeq(value, ptr + (gpu_page_idx * 8)); 106 return 0; 107 } 108 109 /** 110 * amdgpu_gmc_agp_addr - return the address in the AGP address space 111 * 112 * @tbo: TTM BO which needs the address, must be in GTT domain 113 * 114 * Tries to figure out how to access the BO through the AGP aperture. Returns 115 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 116 */ 117 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 118 { 119 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 120 struct ttm_dma_tt *ttm; 121 122 if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached) 123 return AMDGPU_BO_INVALID_OFFSET; 124 125 ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm); 126 if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 127 return AMDGPU_BO_INVALID_OFFSET; 128 129 return adev->gmc.agp_start + ttm->dma_address[0]; 130 } 131 132 /** 133 * amdgpu_gmc_vram_location - try to find VRAM location 134 * 135 * @adev: amdgpu device structure holding all necessary informations 136 * @mc: memory controller structure holding memory informations 137 * @base: base address at which to put VRAM 138 * 139 * Function will try to place VRAM at base address provided 140 * as parameter. 141 */ 142 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 143 u64 base) 144 { 145 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 146 147 mc->vram_start = base; 148 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 149 if (limit && limit < mc->real_vram_size) 150 mc->real_vram_size = limit; 151 152 if (mc->xgmi.num_physical_nodes == 0) { 153 mc->fb_start = mc->vram_start; 154 mc->fb_end = mc->vram_end; 155 } 156 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 157 mc->mc_vram_size >> 20, mc->vram_start, 158 mc->vram_end, mc->real_vram_size >> 20); 159 } 160 161 /** 162 * amdgpu_gmc_gart_location - try to find GART location 163 * 164 * @adev: amdgpu device structure holding all necessary informations 165 * @mc: memory controller structure holding memory informations 166 * 167 * Function will place try to place GART before or after VRAM. 168 * 169 * If GART size is bigger than space left then we ajust GART size. 170 * Thus function will never fails. 171 */ 172 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 173 { 174 const uint64_t four_gb = 0x100000000ULL; 175 u64 size_af, size_bf; 176 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 177 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 178 179 mc->gart_size += adev->pm.smu_prv_buffer_size; 180 181 /* VCE doesn't like it when BOs cross a 4GB segment, so align 182 * the GART base on a 4GB boundary as well. 183 */ 184 size_bf = mc->fb_start; 185 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 186 187 if (mc->gart_size > max(size_bf, size_af)) { 188 dev_warn(adev->dev, "limiting GART\n"); 189 mc->gart_size = max(size_bf, size_af); 190 } 191 192 if ((size_bf >= mc->gart_size && size_bf < size_af) || 193 (size_af < mc->gart_size)) 194 mc->gart_start = 0; 195 else 196 mc->gart_start = max_mc_address - mc->gart_size + 1; 197 198 mc->gart_start &= ~(four_gb - 1); 199 mc->gart_end = mc->gart_start + mc->gart_size - 1; 200 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 201 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 202 } 203 204 /** 205 * amdgpu_gmc_agp_location - try to find AGP location 206 * @adev: amdgpu device structure holding all necessary informations 207 * @mc: memory controller structure holding memory informations 208 * 209 * Function will place try to find a place for the AGP BAR in the MC address 210 * space. 211 * 212 * AGP BAR will be assigned the largest available hole in the address space. 213 * Should be called after VRAM and GART locations are setup. 214 */ 215 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 216 { 217 const uint64_t sixteen_gb = 1ULL << 34; 218 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 219 u64 size_af, size_bf; 220 221 if (mc->fb_start > mc->gart_start) { 222 size_bf = (mc->fb_start & sixteen_gb_mask) - 223 ALIGN(mc->gart_end + 1, sixteen_gb); 224 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 225 } else { 226 size_bf = mc->fb_start & sixteen_gb_mask; 227 size_af = (mc->gart_start & sixteen_gb_mask) - 228 ALIGN(mc->fb_end + 1, sixteen_gb); 229 } 230 231 if (size_bf > size_af) { 232 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 233 mc->agp_size = size_bf; 234 } else { 235 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 236 mc->agp_size = size_af; 237 } 238 239 mc->agp_end = mc->agp_start + mc->agp_size - 1; 240 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 241 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 242 } 243 244 /** 245 * amdgpu_gmc_filter_faults - filter VM faults 246 * 247 * @adev: amdgpu device structure 248 * @addr: address of the VM fault 249 * @pasid: PASID of the process causing the fault 250 * @timestamp: timestamp of the fault 251 * 252 * Returns: 253 * True if the fault was filtered and should not be processed further. 254 * False if the fault is a new one and needs to be handled. 255 */ 256 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr, 257 uint16_t pasid, uint64_t timestamp) 258 { 259 struct amdgpu_gmc *gmc = &adev->gmc; 260 261 uint64_t stamp, key = addr << 4 | pasid; 262 struct amdgpu_gmc_fault *fault; 263 uint32_t hash; 264 265 /* If we don't have space left in the ring buffer return immediately */ 266 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 267 AMDGPU_GMC_FAULT_TIMEOUT; 268 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 269 return true; 270 271 /* Try to find the fault in the hash */ 272 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 273 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 274 while (fault->timestamp >= stamp) { 275 uint64_t tmp; 276 277 if (fault->key == key) 278 return true; 279 280 tmp = fault->timestamp; 281 fault = &gmc->fault_ring[fault->next]; 282 283 /* Check if the entry was reused */ 284 if (fault->timestamp >= tmp) 285 break; 286 } 287 288 /* Add the fault to the ring */ 289 fault = &gmc->fault_ring[gmc->last_fault]; 290 fault->key = key; 291 fault->timestamp = timestamp; 292 293 /* And update the hash */ 294 fault->next = gmc->fault_hash[hash].idx; 295 gmc->fault_hash[hash].idx = gmc->last_fault++; 296 return false; 297 } 298