1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #ifdef CONFIG_X86 29 #include <asm/hypervisor.h> 30 #endif 31 32 #include "amdgpu.h" 33 #include "amdgpu_gmc.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_xgmi.h" 36 37 #include <drm/drm_drv.h> 38 #include <drm/ttm/ttm_tt.h> 39 40 /** 41 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 42 * 43 * @adev: amdgpu_device pointer 44 * 45 * Allocate video memory for pdb0 and map it for CPU access 46 * Returns 0 for success, error for failure. 47 */ 48 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 49 { 50 int r; 51 struct amdgpu_bo_param bp; 52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 54 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 55 56 memset(&bp, 0, sizeof(bp)); 57 bp.size = PAGE_ALIGN((npdes + 1) * 8); 58 bp.byte_align = PAGE_SIZE; 59 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 60 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 61 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 62 bp.type = ttm_bo_type_kernel; 63 bp.resv = NULL; 64 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 65 66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 67 if (r) 68 return r; 69 70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 71 if (unlikely(r != 0)) 72 goto bo_reserve_failure; 73 74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 75 if (r) 76 goto bo_pin_failure; 77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 78 if (r) 79 goto bo_kmap_failure; 80 81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 82 return 0; 83 84 bo_kmap_failure: 85 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 86 bo_pin_failure: 87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 88 bo_reserve_failure: 89 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 90 return r; 91 } 92 93 /** 94 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 95 * 96 * @bo: the BO to get the PDE for 97 * @level: the level in the PD hirarchy 98 * @addr: resulting addr 99 * @flags: resulting flags 100 * 101 * Get the address and flags to be used for a PDE (Page Directory Entry). 102 */ 103 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 104 uint64_t *addr, uint64_t *flags) 105 { 106 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 107 108 switch (bo->tbo.resource->mem_type) { 109 case TTM_PL_TT: 110 *addr = bo->tbo.ttm->dma_address[0]; 111 break; 112 case TTM_PL_VRAM: 113 *addr = amdgpu_bo_gpu_offset(bo); 114 break; 115 default: 116 *addr = 0; 117 break; 118 } 119 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); 120 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 121 } 122 123 /* 124 * amdgpu_gmc_pd_addr - return the address of the root directory 125 */ 126 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 129 uint64_t pd_addr; 130 131 /* TODO: move that into ASIC specific code */ 132 if (adev->asic_type >= CHIP_VEGA10) { 133 uint64_t flags = AMDGPU_PTE_VALID; 134 135 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 136 pd_addr |= flags; 137 } else { 138 pd_addr = amdgpu_bo_gpu_offset(bo); 139 } 140 return pd_addr; 141 } 142 143 /** 144 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 145 * 146 * @adev: amdgpu_device pointer 147 * @cpu_pt_addr: cpu address of the page table 148 * @gpu_page_idx: entry in the page table to update 149 * @addr: dst addr to write into pte/pde 150 * @flags: access flags 151 * 152 * Update the page tables using CPU. 153 */ 154 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 155 uint32_t gpu_page_idx, uint64_t addr, 156 uint64_t flags) 157 { 158 void __iomem *ptr = (void *)cpu_pt_addr; 159 uint64_t value; 160 161 /* 162 * The following is for PTE only. GART does not have PDEs. 163 */ 164 value = addr & 0x0000FFFFFFFFF000ULL; 165 value |= flags; 166 writeq(value, ptr + (gpu_page_idx * 8)); 167 168 return 0; 169 } 170 171 /** 172 * amdgpu_gmc_agp_addr - return the address in the AGP address space 173 * 174 * @bo: TTM BO which needs the address, must be in GTT domain 175 * 176 * Tries to figure out how to access the BO through the AGP aperture. Returns 177 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 178 */ 179 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 180 { 181 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 182 183 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 184 return AMDGPU_BO_INVALID_OFFSET; 185 186 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 187 return AMDGPU_BO_INVALID_OFFSET; 188 189 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 190 } 191 192 /** 193 * amdgpu_gmc_vram_location - try to find VRAM location 194 * 195 * @adev: amdgpu device structure holding all necessary information 196 * @mc: memory controller structure holding memory information 197 * @base: base address at which to put VRAM 198 * 199 * Function will try to place VRAM at base address provided 200 * as parameter. 201 */ 202 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 203 u64 base) 204 { 205 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20; 206 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 207 208 mc->vram_start = base; 209 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 210 if (limit < mc->real_vram_size) 211 mc->real_vram_size = limit; 212 213 if (vis_limit && vis_limit < mc->visible_vram_size) 214 mc->visible_vram_size = vis_limit; 215 216 if (mc->real_vram_size < mc->visible_vram_size) 217 mc->visible_vram_size = mc->real_vram_size; 218 219 if (mc->xgmi.num_physical_nodes == 0) { 220 mc->fb_start = mc->vram_start; 221 mc->fb_end = mc->vram_end; 222 } 223 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 224 mc->mc_vram_size >> 20, mc->vram_start, 225 mc->vram_end, mc->real_vram_size >> 20); 226 } 227 228 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 229 * 230 * @adev: amdgpu device structure holding all necessary information 231 * @mc: memory controller structure holding memory information 232 * 233 * This function is only used if use GART for FB translation. In such 234 * case, we use sysvm aperture (vmid0 page tables) for both vram 235 * and gart (aka system memory) access. 236 * 237 * GPUVM (and our organization of vmid0 page tables) require sysvm 238 * aperture to be placed at a location aligned with 8 times of native 239 * page size. For example, if vm_context0_cntl.page_table_block_size 240 * is 12, then native page size is 8G (2M*2^12), sysvm should start 241 * with a 64G aligned address. For simplicity, we just put sysvm at 242 * address 0. So vram start at address 0 and gart is right after vram. 243 */ 244 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 245 { 246 u64 hive_vram_start = 0; 247 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 248 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 249 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 250 mc->gart_start = hive_vram_end + 1; 251 mc->gart_end = mc->gart_start + mc->gart_size - 1; 252 mc->fb_start = hive_vram_start; 253 mc->fb_end = hive_vram_end; 254 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 255 mc->mc_vram_size >> 20, mc->vram_start, 256 mc->vram_end, mc->real_vram_size >> 20); 257 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 258 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 259 } 260 261 /** 262 * amdgpu_gmc_gart_location - try to find GART location 263 * 264 * @adev: amdgpu device structure holding all necessary information 265 * @mc: memory controller structure holding memory information 266 * 267 * Function will place try to place GART before or after VRAM. 268 * If GART size is bigger than space left then we ajust GART size. 269 * Thus function will never fails. 270 */ 271 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 272 { 273 const uint64_t four_gb = 0x100000000ULL; 274 u64 size_af, size_bf; 275 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 276 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 277 278 /* VCE doesn't like it when BOs cross a 4GB segment, so align 279 * the GART base on a 4GB boundary as well. 280 */ 281 size_bf = mc->fb_start; 282 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 283 284 if (mc->gart_size > max(size_bf, size_af)) { 285 dev_warn(adev->dev, "limiting GART\n"); 286 mc->gart_size = max(size_bf, size_af); 287 } 288 289 if ((size_bf >= mc->gart_size && size_bf < size_af) || 290 (size_af < mc->gart_size)) 291 mc->gart_start = 0; 292 else 293 mc->gart_start = max_mc_address - mc->gart_size + 1; 294 295 mc->gart_start &= ~(four_gb - 1); 296 mc->gart_end = mc->gart_start + mc->gart_size - 1; 297 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 298 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 299 } 300 301 /** 302 * amdgpu_gmc_agp_location - try to find AGP location 303 * @adev: amdgpu device structure holding all necessary information 304 * @mc: memory controller structure holding memory information 305 * 306 * Function will place try to find a place for the AGP BAR in the MC address 307 * space. 308 * 309 * AGP BAR will be assigned the largest available hole in the address space. 310 * Should be called after VRAM and GART locations are setup. 311 */ 312 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 313 { 314 const uint64_t sixteen_gb = 1ULL << 34; 315 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 316 u64 size_af, size_bf; 317 318 if (amdgpu_sriov_vf(adev)) { 319 mc->agp_start = 0xffffffffffff; 320 mc->agp_end = 0x0; 321 mc->agp_size = 0; 322 323 return; 324 } 325 326 if (mc->fb_start > mc->gart_start) { 327 size_bf = (mc->fb_start & sixteen_gb_mask) - 328 ALIGN(mc->gart_end + 1, sixteen_gb); 329 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 330 } else { 331 size_bf = mc->fb_start & sixteen_gb_mask; 332 size_af = (mc->gart_start & sixteen_gb_mask) - 333 ALIGN(mc->fb_end + 1, sixteen_gb); 334 } 335 336 if (size_bf > size_af) { 337 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 338 mc->agp_size = size_bf; 339 } else { 340 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 341 mc->agp_size = size_af; 342 } 343 344 mc->agp_end = mc->agp_start + mc->agp_size - 1; 345 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 346 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 347 } 348 349 /** 350 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 351 * 352 * @addr: 48 bit physical address, page aligned (36 significant bits) 353 * @pasid: 16 bit process address space identifier 354 */ 355 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 356 { 357 return addr << 4 | pasid; 358 } 359 360 /** 361 * amdgpu_gmc_filter_faults - filter VM faults 362 * 363 * @adev: amdgpu device structure 364 * @ih: interrupt ring that the fault received from 365 * @addr: address of the VM fault 366 * @pasid: PASID of the process causing the fault 367 * @timestamp: timestamp of the fault 368 * 369 * Returns: 370 * True if the fault was filtered and should not be processed further. 371 * False if the fault is a new one and needs to be handled. 372 */ 373 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 374 struct amdgpu_ih_ring *ih, uint64_t addr, 375 uint16_t pasid, uint64_t timestamp) 376 { 377 struct amdgpu_gmc *gmc = &adev->gmc; 378 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 379 struct amdgpu_gmc_fault *fault; 380 uint32_t hash; 381 382 /* Stale retry fault if timestamp goes backward */ 383 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp)) 384 return true; 385 386 /* If we don't have space left in the ring buffer return immediately */ 387 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 388 AMDGPU_GMC_FAULT_TIMEOUT; 389 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 390 return true; 391 392 /* Try to find the fault in the hash */ 393 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 394 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 395 while (fault->timestamp >= stamp) { 396 uint64_t tmp; 397 398 if (atomic64_read(&fault->key) == key) 399 return true; 400 401 tmp = fault->timestamp; 402 fault = &gmc->fault_ring[fault->next]; 403 404 /* Check if the entry was reused */ 405 if (fault->timestamp >= tmp) 406 break; 407 } 408 409 /* Add the fault to the ring */ 410 fault = &gmc->fault_ring[gmc->last_fault]; 411 atomic64_set(&fault->key, key); 412 fault->timestamp = timestamp; 413 414 /* And update the hash */ 415 fault->next = gmc->fault_hash[hash].idx; 416 gmc->fault_hash[hash].idx = gmc->last_fault++; 417 return false; 418 } 419 420 /** 421 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 422 * 423 * @adev: amdgpu device structure 424 * @addr: address of the VM fault 425 * @pasid: PASID of the process causing the fault 426 * 427 * Remove the address from fault filter, then future vm fault on this address 428 * will pass to retry fault handler to recover. 429 */ 430 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 431 uint16_t pasid) 432 { 433 struct amdgpu_gmc *gmc = &adev->gmc; 434 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 435 struct amdgpu_gmc_fault *fault; 436 uint32_t hash; 437 uint64_t tmp; 438 439 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 440 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 441 do { 442 if (atomic64_cmpxchg(&fault->key, key, 0) == key) 443 break; 444 445 tmp = fault->timestamp; 446 fault = &gmc->fault_ring[fault->next]; 447 } while (fault->timestamp < tmp); 448 } 449 450 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev) 451 { 452 int r; 453 454 /* umc ras block */ 455 r = amdgpu_umc_ras_sw_init(adev); 456 if (r) 457 return r; 458 459 /* mmhub ras block */ 460 r = amdgpu_mmhub_ras_sw_init(adev); 461 if (r) 462 return r; 463 464 /* hdp ras block */ 465 r = amdgpu_hdp_ras_sw_init(adev); 466 if (r) 467 return r; 468 469 /* mca.x ras block */ 470 r = amdgpu_mca_mp0_ras_sw_init(adev); 471 if (r) 472 return r; 473 474 r = amdgpu_mca_mp1_ras_sw_init(adev); 475 if (r) 476 return r; 477 478 r = amdgpu_mca_mpio_ras_sw_init(adev); 479 if (r) 480 return r; 481 482 /* xgmi ras block */ 483 r = amdgpu_xgmi_ras_sw_init(adev); 484 if (r) 485 return r; 486 487 return 0; 488 } 489 490 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 491 { 492 return 0; 493 } 494 495 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 496 { 497 498 } 499 500 /* 501 * The latest engine allocation on gfx9/10 is: 502 * Engine 2, 3: firmware 503 * Engine 0, 1, 4~16: amdgpu ring, 504 * subject to change when ring number changes 505 * Engine 17: Gart flushes 506 */ 507 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 508 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 509 510 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 511 { 512 struct amdgpu_ring *ring; 513 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 514 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 515 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 516 unsigned i; 517 unsigned vmhub, inv_eng; 518 519 if (adev->enable_mes) { 520 /* reserve engine 5 for firmware */ 521 for (vmhub = 0; vmhub < AMDGPU_MAX_VMHUBS; vmhub++) 522 vm_inv_engs[vmhub] &= ~(1 << 5); 523 } 524 525 for (i = 0; i < adev->num_rings; ++i) { 526 ring = adev->rings[i]; 527 vmhub = ring->funcs->vmhub; 528 529 if (ring == &adev->mes.ring) 530 continue; 531 532 inv_eng = ffs(vm_inv_engs[vmhub]); 533 if (!inv_eng) { 534 dev_err(adev->dev, "no VM inv eng for ring %s\n", 535 ring->name); 536 return -EINVAL; 537 } 538 539 ring->vm_inv_eng = inv_eng - 1; 540 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 541 542 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 543 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 544 } 545 546 return 0; 547 } 548 549 /** 550 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ 551 * @adev: amdgpu_device pointer 552 * 553 * Check and set if an the device @adev supports Trusted Memory 554 * Zones (TMZ). 555 */ 556 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 557 { 558 switch (adev->ip_versions[GC_HWIP][0]) { 559 /* RAVEN */ 560 case IP_VERSION(9, 2, 2): 561 case IP_VERSION(9, 1, 0): 562 /* RENOIR looks like RAVEN */ 563 case IP_VERSION(9, 3, 0): 564 /* GC 10.3.7 */ 565 case IP_VERSION(10, 3, 7): 566 if (amdgpu_tmz == 0) { 567 adev->gmc.tmz_enabled = false; 568 dev_info(adev->dev, 569 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 570 } else { 571 adev->gmc.tmz_enabled = true; 572 dev_info(adev->dev, 573 "Trusted Memory Zone (TMZ) feature enabled\n"); 574 } 575 break; 576 case IP_VERSION(10, 1, 10): 577 case IP_VERSION(10, 1, 1): 578 case IP_VERSION(10, 1, 2): 579 case IP_VERSION(10, 1, 3): 580 case IP_VERSION(10, 3, 0): 581 case IP_VERSION(10, 3, 2): 582 case IP_VERSION(10, 3, 4): 583 case IP_VERSION(10, 3, 5): 584 case IP_VERSION(10, 3, 6): 585 /* VANGOGH */ 586 case IP_VERSION(10, 3, 1): 587 /* YELLOW_CARP*/ 588 case IP_VERSION(10, 3, 3): 589 case IP_VERSION(11, 0, 1): 590 case IP_VERSION(11, 0, 4): 591 /* Don't enable it by default yet. 592 */ 593 if (amdgpu_tmz < 1) { 594 adev->gmc.tmz_enabled = false; 595 dev_info(adev->dev, 596 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 597 } else { 598 adev->gmc.tmz_enabled = true; 599 dev_info(adev->dev, 600 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 601 } 602 break; 603 default: 604 adev->gmc.tmz_enabled = false; 605 dev_info(adev->dev, 606 "Trusted Memory Zone (TMZ) feature not supported\n"); 607 break; 608 } 609 } 610 611 /** 612 * amdgpu_gmc_noretry_set -- set per asic noretry defaults 613 * @adev: amdgpu_device pointer 614 * 615 * Set a per asic default for the no-retry parameter. 616 * 617 */ 618 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 619 { 620 struct amdgpu_gmc *gmc = &adev->gmc; 621 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 622 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || 623 gc_ver == IP_VERSION(9, 3, 0) || 624 gc_ver == IP_VERSION(9, 4, 0) || 625 gc_ver == IP_VERSION(9, 4, 1) || 626 gc_ver == IP_VERSION(9, 4, 2) || 627 gc_ver == IP_VERSION(9, 4, 3) || 628 gc_ver >= IP_VERSION(10, 3, 0)); 629 630 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 631 } 632 633 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 634 bool enable) 635 { 636 struct amdgpu_vmhub *hub; 637 u32 tmp, reg, i; 638 639 hub = &adev->vmhub[hub_type]; 640 for (i = 0; i < 16; i++) { 641 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 642 643 tmp = (hub_type == AMDGPU_GFXHUB_0) ? 644 RREG32_SOC15_IP(GC, reg) : 645 RREG32_SOC15_IP(MMHUB, reg); 646 647 if (enable) 648 tmp |= hub->vm_cntx_cntl_vm_fault; 649 else 650 tmp &= ~hub->vm_cntx_cntl_vm_fault; 651 652 (hub_type == AMDGPU_GFXHUB_0) ? 653 WREG32_SOC15_IP(GC, reg, tmp) : 654 WREG32_SOC15_IP(MMHUB, reg, tmp); 655 } 656 } 657 658 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 659 { 660 unsigned size; 661 662 /* 663 * Some ASICs need to reserve a region of video memory to avoid access 664 * from driver 665 */ 666 adev->mman.stolen_reserved_offset = 0; 667 adev->mman.stolen_reserved_size = 0; 668 669 /* 670 * TODO: 671 * Currently there is a bug where some memory client outside 672 * of the driver writes to first 8M of VRAM on S3 resume, 673 * this overrides GART which by default gets placed in first 8M and 674 * causes VM_FAULTS once GTT is accessed. 675 * Keep the stolen memory reservation until the while this is not solved. 676 */ 677 switch (adev->asic_type) { 678 case CHIP_VEGA10: 679 adev->mman.keep_stolen_vga_memory = true; 680 /* 681 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area. 682 */ 683 #ifdef CONFIG_X86 684 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 685 adev->mman.stolen_reserved_offset = 0x500000; 686 adev->mman.stolen_reserved_size = 0x200000; 687 } 688 #endif 689 break; 690 case CHIP_RAVEN: 691 case CHIP_RENOIR: 692 adev->mman.keep_stolen_vga_memory = true; 693 break; 694 case CHIP_YELLOW_CARP: 695 if (amdgpu_discovery == 0) { 696 adev->mman.stolen_reserved_offset = 0x1ffb0000; 697 adev->mman.stolen_reserved_size = 64 * PAGE_SIZE; 698 } 699 break; 700 default: 701 adev->mman.keep_stolen_vga_memory = false; 702 break; 703 } 704 705 if (amdgpu_sriov_vf(adev) || 706 !amdgpu_device_has_display_hardware(adev)) { 707 size = 0; 708 } else { 709 size = amdgpu_gmc_get_vbios_fb_size(adev); 710 711 if (adev->mman.keep_stolen_vga_memory) 712 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 713 } 714 715 /* set to 0 if the pre-OS buffer uses up most of vram */ 716 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 717 size = 0; 718 719 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 720 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 721 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 722 } else { 723 adev->mman.stolen_vga_size = size; 724 adev->mman.stolen_extended_size = 0; 725 } 726 } 727 728 /** 729 * amdgpu_gmc_init_pdb0 - initialize PDB0 730 * 731 * @adev: amdgpu_device pointer 732 * 733 * This function is only used when GART page table is used 734 * for FB address translatioin. In such a case, we construct 735 * a 2-level system VM page table: PDB0->PTB, to cover both 736 * VRAM of the hive and system memory. 737 * 738 * PDB0 is static, initialized once on driver initialization. 739 * The first n entries of PDB0 are used as PTE by setting 740 * P bit to 1, pointing to VRAM. The n+1'th entry points 741 * to a big PTB covering system memory. 742 * 743 */ 744 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 745 { 746 int i; 747 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 748 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 749 */ 750 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 751 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 752 u64 vram_addr = adev->vm_manager.vram_base_offset - 753 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 754 u64 vram_end = vram_addr + vram_size; 755 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 756 int idx; 757 758 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 759 return; 760 761 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 762 flags |= AMDGPU_PTE_WRITEABLE; 763 flags |= AMDGPU_PTE_SNOOPED; 764 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 765 flags |= AMDGPU_PDE_PTE; 766 767 /* The first n PDE0 entries are used as PTE, 768 * pointing to vram 769 */ 770 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 771 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 772 773 /* The n+1'th PDE0 entry points to a huge 774 * PTB who has more than 512 entries each 775 * pointing to a 4K system page 776 */ 777 flags = AMDGPU_PTE_VALID; 778 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 779 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 780 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 781 drm_dev_exit(idx); 782 } 783 784 /** 785 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 786 * address 787 * 788 * @adev: amdgpu_device pointer 789 * @mc_addr: MC address of buffer 790 */ 791 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 792 { 793 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 794 } 795 796 /** 797 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 798 * GPU's view 799 * 800 * @adev: amdgpu_device pointer 801 * @bo: amdgpu buffer object 802 */ 803 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 804 { 805 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 806 } 807 808 /** 809 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address 810 * from CPU's view 811 * 812 * @adev: amdgpu_device pointer 813 * @bo: amdgpu buffer object 814 */ 815 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 816 { 817 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; 818 } 819 820 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) 821 { 822 struct amdgpu_bo *vram_bo = NULL; 823 uint64_t vram_gpu = 0; 824 void *vram_ptr = NULL; 825 826 int ret, size = 0x100000; 827 uint8_t cptr[10]; 828 829 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 830 AMDGPU_GEM_DOMAIN_VRAM, 831 &vram_bo, 832 &vram_gpu, 833 &vram_ptr); 834 if (ret) 835 return ret; 836 837 memset(vram_ptr, 0x86, size); 838 memset(cptr, 0x86, 10); 839 840 /** 841 * Check the start, the mid, and the end of the memory if the content of 842 * each byte is the pattern "0x86". If yes, we suppose the vram bo is 843 * workable. 844 * 845 * Note: If check the each byte of whole 1M bo, it will cost too many 846 * seconds, so here, we just pick up three parts for emulation. 847 */ 848 ret = memcmp(vram_ptr, cptr, 10); 849 if (ret) 850 return ret; 851 852 ret = memcmp(vram_ptr + (size / 2), cptr, 10); 853 if (ret) 854 return ret; 855 856 ret = memcmp(vram_ptr + size - 10, cptr, 10); 857 if (ret) 858 return ret; 859 860 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu, 861 &vram_ptr); 862 863 return 0; 864 } 865