1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #ifdef CONFIG_X86 29 #include <asm/hypervisor.h> 30 #endif 31 32 #include "amdgpu.h" 33 #include "amdgpu_gmc.h" 34 #include "amdgpu_ras.h" 35 #include "amdgpu_xgmi.h" 36 37 #include <drm/drm_drv.h> 38 39 /** 40 * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0 41 * 42 * @adev: amdgpu_device pointer 43 * 44 * Allocate video memory for pdb0 and map it for CPU access 45 * Returns 0 for success, error for failure. 46 */ 47 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) 48 { 49 int r; 50 struct amdgpu_bo_param bp; 51 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 52 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; 53 uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift; 54 55 memset(&bp, 0, sizeof(bp)); 56 bp.size = PAGE_ALIGN((npdes + 1) * 8); 57 bp.byte_align = PAGE_SIZE; 58 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 59 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 60 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 61 bp.type = ttm_bo_type_kernel; 62 bp.resv = NULL; 63 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 64 65 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); 66 if (r) 67 return r; 68 69 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); 70 if (unlikely(r != 0)) 71 goto bo_reserve_failure; 72 73 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); 74 if (r) 75 goto bo_pin_failure; 76 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); 77 if (r) 78 goto bo_kmap_failure; 79 80 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 81 return 0; 82 83 bo_kmap_failure: 84 amdgpu_bo_unpin(adev->gmc.pdb0_bo); 85 bo_pin_failure: 86 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); 87 bo_reserve_failure: 88 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 89 return r; 90 } 91 92 /** 93 * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO 94 * 95 * @bo: the BO to get the PDE for 96 * @level: the level in the PD hirarchy 97 * @addr: resulting addr 98 * @flags: resulting flags 99 * 100 * Get the address and flags to be used for a PDE (Page Directory Entry). 101 */ 102 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 103 uint64_t *addr, uint64_t *flags) 104 { 105 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 106 107 switch (bo->tbo.resource->mem_type) { 108 case TTM_PL_TT: 109 *addr = bo->tbo.ttm->dma_address[0]; 110 break; 111 case TTM_PL_VRAM: 112 *addr = amdgpu_bo_gpu_offset(bo); 113 break; 114 default: 115 *addr = 0; 116 break; 117 } 118 *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource); 119 amdgpu_gmc_get_vm_pde(adev, level, addr, flags); 120 } 121 122 /* 123 * amdgpu_gmc_pd_addr - return the address of the root directory 124 */ 125 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 128 uint64_t pd_addr; 129 130 /* TODO: move that into ASIC specific code */ 131 if (adev->asic_type >= CHIP_VEGA10) { 132 uint64_t flags = AMDGPU_PTE_VALID; 133 134 amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags); 135 pd_addr |= flags; 136 } else { 137 pd_addr = amdgpu_bo_gpu_offset(bo); 138 } 139 return pd_addr; 140 } 141 142 /** 143 * amdgpu_gmc_set_pte_pde - update the page tables using CPU 144 * 145 * @adev: amdgpu_device pointer 146 * @cpu_pt_addr: cpu address of the page table 147 * @gpu_page_idx: entry in the page table to update 148 * @addr: dst addr to write into pte/pde 149 * @flags: access flags 150 * 151 * Update the page tables using CPU. 152 */ 153 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 154 uint32_t gpu_page_idx, uint64_t addr, 155 uint64_t flags) 156 { 157 void __iomem *ptr = (void *)cpu_pt_addr; 158 uint64_t value; 159 160 /* 161 * The following is for PTE only. GART does not have PDEs. 162 */ 163 value = addr & 0x0000FFFFFFFFF000ULL; 164 value |= flags; 165 writeq(value, ptr + (gpu_page_idx * 8)); 166 167 return 0; 168 } 169 170 /** 171 * amdgpu_gmc_agp_addr - return the address in the AGP address space 172 * 173 * @bo: TTM BO which needs the address, must be in GTT domain 174 * 175 * Tries to figure out how to access the BO through the AGP aperture. Returns 176 * AMDGPU_BO_INVALID_OFFSET if that is not possible. 177 */ 178 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) 179 { 180 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 181 182 if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached) 183 return AMDGPU_BO_INVALID_OFFSET; 184 185 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size) 186 return AMDGPU_BO_INVALID_OFFSET; 187 188 return adev->gmc.agp_start + bo->ttm->dma_address[0]; 189 } 190 191 /** 192 * amdgpu_gmc_vram_location - try to find VRAM location 193 * 194 * @adev: amdgpu device structure holding all necessary information 195 * @mc: memory controller structure holding memory information 196 * @base: base address at which to put VRAM 197 * 198 * Function will try to place VRAM at base address provided 199 * as parameter. 200 */ 201 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 202 u64 base) 203 { 204 uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20; 205 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; 206 207 mc->vram_start = base; 208 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 209 if (limit < mc->real_vram_size) 210 mc->real_vram_size = limit; 211 212 if (vis_limit && vis_limit < mc->visible_vram_size) 213 mc->visible_vram_size = vis_limit; 214 215 if (mc->real_vram_size < mc->visible_vram_size) 216 mc->visible_vram_size = mc->real_vram_size; 217 218 if (mc->xgmi.num_physical_nodes == 0) { 219 mc->fb_start = mc->vram_start; 220 mc->fb_end = mc->vram_end; 221 } 222 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 223 mc->mc_vram_size >> 20, mc->vram_start, 224 mc->vram_end, mc->real_vram_size >> 20); 225 } 226 227 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture 228 * 229 * @adev: amdgpu device structure holding all necessary information 230 * @mc: memory controller structure holding memory information 231 * 232 * This function is only used if use GART for FB translation. In such 233 * case, we use sysvm aperture (vmid0 page tables) for both vram 234 * and gart (aka system memory) access. 235 * 236 * GPUVM (and our organization of vmid0 page tables) require sysvm 237 * aperture to be placed at a location aligned with 8 times of native 238 * page size. For example, if vm_context0_cntl.page_table_block_size 239 * is 12, then native page size is 8G (2M*2^12), sysvm should start 240 * with a 64G aligned address. For simplicity, we just put sysvm at 241 * address 0. So vram start at address 0 and gart is right after vram. 242 */ 243 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 244 { 245 u64 hive_vram_start = 0; 246 u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1; 247 mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id; 248 mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1; 249 mc->gart_start = hive_vram_end + 1; 250 mc->gart_end = mc->gart_start + mc->gart_size - 1; 251 mc->fb_start = hive_vram_start; 252 mc->fb_end = hive_vram_end; 253 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 254 mc->mc_vram_size >> 20, mc->vram_start, 255 mc->vram_end, mc->real_vram_size >> 20); 256 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 257 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 258 } 259 260 /** 261 * amdgpu_gmc_gart_location - try to find GART location 262 * 263 * @adev: amdgpu device structure holding all necessary information 264 * @mc: memory controller structure holding memory information 265 * 266 * Function will place try to place GART before or after VRAM. 267 * If GART size is bigger than space left then we ajust GART size. 268 * Thus function will never fails. 269 */ 270 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 271 { 272 const uint64_t four_gb = 0x100000000ULL; 273 u64 size_af, size_bf; 274 /*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/ 275 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1); 276 277 /* VCE doesn't like it when BOs cross a 4GB segment, so align 278 * the GART base on a 4GB boundary as well. 279 */ 280 size_bf = mc->fb_start; 281 size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb); 282 283 if (mc->gart_size > max(size_bf, size_af)) { 284 dev_warn(adev->dev, "limiting GART\n"); 285 mc->gart_size = max(size_bf, size_af); 286 } 287 288 if ((size_bf >= mc->gart_size && size_bf < size_af) || 289 (size_af < mc->gart_size)) 290 mc->gart_start = 0; 291 else 292 mc->gart_start = max_mc_address - mc->gart_size + 1; 293 294 mc->gart_start &= ~(four_gb - 1); 295 mc->gart_end = mc->gart_start + mc->gart_size - 1; 296 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", 297 mc->gart_size >> 20, mc->gart_start, mc->gart_end); 298 } 299 300 /** 301 * amdgpu_gmc_agp_location - try to find AGP location 302 * @adev: amdgpu device structure holding all necessary information 303 * @mc: memory controller structure holding memory information 304 * 305 * Function will place try to find a place for the AGP BAR in the MC address 306 * space. 307 * 308 * AGP BAR will be assigned the largest available hole in the address space. 309 * Should be called after VRAM and GART locations are setup. 310 */ 311 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) 312 { 313 const uint64_t sixteen_gb = 1ULL << 34; 314 const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1); 315 u64 size_af, size_bf; 316 317 if (amdgpu_sriov_vf(adev)) { 318 mc->agp_start = 0xffffffffffff; 319 mc->agp_end = 0x0; 320 mc->agp_size = 0; 321 322 return; 323 } 324 325 if (mc->fb_start > mc->gart_start) { 326 size_bf = (mc->fb_start & sixteen_gb_mask) - 327 ALIGN(mc->gart_end + 1, sixteen_gb); 328 size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb); 329 } else { 330 size_bf = mc->fb_start & sixteen_gb_mask; 331 size_af = (mc->gart_start & sixteen_gb_mask) - 332 ALIGN(mc->fb_end + 1, sixteen_gb); 333 } 334 335 if (size_bf > size_af) { 336 mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask; 337 mc->agp_size = size_bf; 338 } else { 339 mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb); 340 mc->agp_size = size_af; 341 } 342 343 mc->agp_end = mc->agp_start + mc->agp_size - 1; 344 dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n", 345 mc->agp_size >> 20, mc->agp_start, mc->agp_end); 346 } 347 348 /** 349 * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid 350 * 351 * @addr: 48 bit physical address, page aligned (36 significant bits) 352 * @pasid: 16 bit process address space identifier 353 */ 354 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid) 355 { 356 return addr << 4 | pasid; 357 } 358 359 /** 360 * amdgpu_gmc_filter_faults - filter VM faults 361 * 362 * @adev: amdgpu device structure 363 * @ih: interrupt ring that the fault received from 364 * @addr: address of the VM fault 365 * @pasid: PASID of the process causing the fault 366 * @timestamp: timestamp of the fault 367 * 368 * Returns: 369 * True if the fault was filtered and should not be processed further. 370 * False if the fault is a new one and needs to be handled. 371 */ 372 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 373 struct amdgpu_ih_ring *ih, uint64_t addr, 374 uint16_t pasid, uint64_t timestamp) 375 { 376 struct amdgpu_gmc *gmc = &adev->gmc; 377 uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid); 378 struct amdgpu_gmc_fault *fault; 379 uint32_t hash; 380 381 /* Stale retry fault if timestamp goes backward */ 382 if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp)) 383 return true; 384 385 /* If we don't have space left in the ring buffer return immediately */ 386 stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) - 387 AMDGPU_GMC_FAULT_TIMEOUT; 388 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp) 389 return true; 390 391 /* Try to find the fault in the hash */ 392 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 393 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 394 while (fault->timestamp >= stamp) { 395 uint64_t tmp; 396 397 if (atomic64_read(&fault->key) == key) 398 return true; 399 400 tmp = fault->timestamp; 401 fault = &gmc->fault_ring[fault->next]; 402 403 /* Check if the entry was reused */ 404 if (fault->timestamp >= tmp) 405 break; 406 } 407 408 /* Add the fault to the ring */ 409 fault = &gmc->fault_ring[gmc->last_fault]; 410 atomic64_set(&fault->key, key); 411 fault->timestamp = timestamp; 412 413 /* And update the hash */ 414 fault->next = gmc->fault_hash[hash].idx; 415 gmc->fault_hash[hash].idx = gmc->last_fault++; 416 return false; 417 } 418 419 /** 420 * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter 421 * 422 * @adev: amdgpu device structure 423 * @addr: address of the VM fault 424 * @pasid: PASID of the process causing the fault 425 * 426 * Remove the address from fault filter, then future vm fault on this address 427 * will pass to retry fault handler to recover. 428 */ 429 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 430 uint16_t pasid) 431 { 432 struct amdgpu_gmc *gmc = &adev->gmc; 433 uint64_t key = amdgpu_gmc_fault_key(addr, pasid); 434 struct amdgpu_gmc_fault *fault; 435 uint32_t hash; 436 uint64_t tmp; 437 438 hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER); 439 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx]; 440 do { 441 if (atomic64_cmpxchg(&fault->key, key, 0) == key) 442 break; 443 444 tmp = fault->timestamp; 445 fault = &gmc->fault_ring[fault->next]; 446 } while (fault->timestamp < tmp); 447 } 448 449 int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev) 450 { 451 if (!adev->gmc.xgmi.connected_to_cpu) { 452 adev->gmc.xgmi.ras = &xgmi_ras; 453 amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block); 454 adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm; 455 } 456 457 return 0; 458 } 459 460 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 461 { 462 return 0; 463 } 464 465 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev) 466 { 467 468 } 469 470 /* 471 * The latest engine allocation on gfx9/10 is: 472 * Engine 2, 3: firmware 473 * Engine 0, 1, 4~16: amdgpu ring, 474 * subject to change when ring number changes 475 * Engine 17: Gart flushes 476 */ 477 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 478 #define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3 479 480 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 481 { 482 struct amdgpu_ring *ring; 483 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 484 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 485 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 486 unsigned i; 487 unsigned vmhub, inv_eng; 488 489 if (adev->enable_mes) { 490 /* reserve engine 5 for firmware */ 491 for (vmhub = 0; vmhub < AMDGPU_MAX_VMHUBS; vmhub++) 492 vm_inv_engs[vmhub] &= ~(1 << 5); 493 } 494 495 for (i = 0; i < adev->num_rings; ++i) { 496 ring = adev->rings[i]; 497 vmhub = ring->funcs->vmhub; 498 499 if (ring == &adev->mes.ring) 500 continue; 501 502 inv_eng = ffs(vm_inv_engs[vmhub]); 503 if (!inv_eng) { 504 dev_err(adev->dev, "no VM inv eng for ring %s\n", 505 ring->name); 506 return -EINVAL; 507 } 508 509 ring->vm_inv_eng = inv_eng - 1; 510 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 511 512 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 513 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 514 } 515 516 return 0; 517 } 518 519 /** 520 * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ 521 * @adev: amdgpu_device pointer 522 * 523 * Check and set if an the device @adev supports Trusted Memory 524 * Zones (TMZ). 525 */ 526 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 527 { 528 switch (adev->ip_versions[GC_HWIP][0]) { 529 /* RAVEN */ 530 case IP_VERSION(9, 2, 2): 531 case IP_VERSION(9, 1, 0): 532 /* RENOIR looks like RAVEN */ 533 case IP_VERSION(9, 3, 0): 534 /* GC 10.3.7 */ 535 case IP_VERSION(10, 3, 7): 536 if (amdgpu_tmz == 0) { 537 adev->gmc.tmz_enabled = false; 538 dev_info(adev->dev, 539 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n"); 540 } else { 541 adev->gmc.tmz_enabled = true; 542 dev_info(adev->dev, 543 "Trusted Memory Zone (TMZ) feature enabled\n"); 544 } 545 break; 546 case IP_VERSION(10, 1, 10): 547 case IP_VERSION(10, 1, 1): 548 case IP_VERSION(10, 1, 2): 549 case IP_VERSION(10, 1, 3): 550 case IP_VERSION(10, 3, 0): 551 case IP_VERSION(10, 3, 2): 552 case IP_VERSION(10, 3, 4): 553 case IP_VERSION(10, 3, 5): 554 /* VANGOGH */ 555 case IP_VERSION(10, 3, 1): 556 /* YELLOW_CARP*/ 557 case IP_VERSION(10, 3, 3): 558 case IP_VERSION(11, 0, 1): 559 case IP_VERSION(11, 0, 4): 560 /* Don't enable it by default yet. 561 */ 562 if (amdgpu_tmz < 1) { 563 adev->gmc.tmz_enabled = false; 564 dev_info(adev->dev, 565 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n"); 566 } else { 567 adev->gmc.tmz_enabled = true; 568 dev_info(adev->dev, 569 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n"); 570 } 571 break; 572 default: 573 adev->gmc.tmz_enabled = false; 574 dev_info(adev->dev, 575 "Trusted Memory Zone (TMZ) feature not supported\n"); 576 break; 577 } 578 } 579 580 /** 581 * amdgpu_gmc_noretry_set -- set per asic noretry defaults 582 * @adev: amdgpu_device pointer 583 * 584 * Set a per asic default for the no-retry parameter. 585 * 586 */ 587 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) 588 { 589 struct amdgpu_gmc *gmc = &adev->gmc; 590 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 591 bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) || 592 gc_ver == IP_VERSION(9, 3, 0) || 593 gc_ver == IP_VERSION(9, 4, 0) || 594 gc_ver == IP_VERSION(9, 4, 1) || 595 gc_ver == IP_VERSION(9, 4, 2) || 596 gc_ver >= IP_VERSION(10, 3, 0)); 597 598 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; 599 } 600 601 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 602 bool enable) 603 { 604 struct amdgpu_vmhub *hub; 605 u32 tmp, reg, i; 606 607 hub = &adev->vmhub[hub_type]; 608 for (i = 0; i < 16; i++) { 609 reg = hub->vm_context0_cntl + hub->ctx_distance * i; 610 611 tmp = (hub_type == AMDGPU_GFXHUB_0) ? 612 RREG32_SOC15_IP(GC, reg) : 613 RREG32_SOC15_IP(MMHUB, reg); 614 615 if (enable) 616 tmp |= hub->vm_cntx_cntl_vm_fault; 617 else 618 tmp &= ~hub->vm_cntx_cntl_vm_fault; 619 620 (hub_type == AMDGPU_GFXHUB_0) ? 621 WREG32_SOC15_IP(GC, reg, tmp) : 622 WREG32_SOC15_IP(MMHUB, reg, tmp); 623 } 624 } 625 626 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) 627 { 628 unsigned size; 629 630 /* 631 * Some ASICs need to reserve a region of video memory to avoid access 632 * from driver 633 */ 634 adev->mman.stolen_reserved_offset = 0; 635 adev->mman.stolen_reserved_size = 0; 636 637 /* 638 * TODO: 639 * Currently there is a bug where some memory client outside 640 * of the driver writes to first 8M of VRAM on S3 resume, 641 * this overrides GART which by default gets placed in first 8M and 642 * causes VM_FAULTS once GTT is accessed. 643 * Keep the stolen memory reservation until the while this is not solved. 644 */ 645 switch (adev->asic_type) { 646 case CHIP_VEGA10: 647 adev->mman.keep_stolen_vga_memory = true; 648 /* 649 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area. 650 */ 651 #ifdef CONFIG_X86 652 if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) { 653 adev->mman.stolen_reserved_offset = 0x500000; 654 adev->mman.stolen_reserved_size = 0x200000; 655 } 656 #endif 657 break; 658 case CHIP_RAVEN: 659 case CHIP_RENOIR: 660 adev->mman.keep_stolen_vga_memory = true; 661 break; 662 case CHIP_YELLOW_CARP: 663 if (amdgpu_discovery == 0) { 664 adev->mman.stolen_reserved_offset = 0x1ffb0000; 665 adev->mman.stolen_reserved_size = 64 * PAGE_SIZE; 666 } 667 break; 668 default: 669 adev->mman.keep_stolen_vga_memory = false; 670 break; 671 } 672 673 if (amdgpu_sriov_vf(adev) || 674 !amdgpu_device_has_display_hardware(adev)) { 675 size = 0; 676 } else { 677 size = amdgpu_gmc_get_vbios_fb_size(adev); 678 679 if (adev->mman.keep_stolen_vga_memory) 680 size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION); 681 } 682 683 /* set to 0 if the pre-OS buffer uses up most of vram */ 684 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 685 size = 0; 686 687 if (size > AMDGPU_VBIOS_VGA_ALLOCATION) { 688 adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION; 689 adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size; 690 } else { 691 adev->mman.stolen_vga_size = size; 692 adev->mman.stolen_extended_size = 0; 693 } 694 } 695 696 /** 697 * amdgpu_gmc_init_pdb0 - initialize PDB0 698 * 699 * @adev: amdgpu_device pointer 700 * 701 * This function is only used when GART page table is used 702 * for FB address translatioin. In such a case, we construct 703 * a 2-level system VM page table: PDB0->PTB, to cover both 704 * VRAM of the hive and system memory. 705 * 706 * PDB0 is static, initialized once on driver initialization. 707 * The first n entries of PDB0 are used as PTE by setting 708 * P bit to 1, pointing to VRAM. The n+1'th entry points 709 * to a big PTB covering system memory. 710 * 711 */ 712 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) 713 { 714 int i; 715 uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW? 716 /* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M 717 */ 718 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; 719 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21; 720 u64 vram_addr = adev->vm_manager.vram_base_offset - 721 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 722 u64 vram_end = vram_addr + vram_size; 723 u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo); 724 int idx; 725 726 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 727 return; 728 729 flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE; 730 flags |= AMDGPU_PTE_WRITEABLE; 731 flags |= AMDGPU_PTE_SNOOPED; 732 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1)); 733 flags |= AMDGPU_PDE_PTE; 734 735 /* The first n PDE0 entries are used as PTE, 736 * pointing to vram 737 */ 738 for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size) 739 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags); 740 741 /* The n+1'th PDE0 entry points to a huge 742 * PTB who has more than 512 entries each 743 * pointing to a 4K system page 744 */ 745 flags = AMDGPU_PTE_VALID; 746 flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; 747 /* Requires gart_ptb_gpu_pa to be 4K aligned */ 748 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags); 749 drm_dev_exit(idx); 750 } 751 752 /** 753 * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC 754 * address 755 * 756 * @adev: amdgpu_device pointer 757 * @mc_addr: MC address of buffer 758 */ 759 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr) 760 { 761 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; 762 } 763 764 /** 765 * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from 766 * GPU's view 767 * 768 * @adev: amdgpu_device pointer 769 * @bo: amdgpu buffer object 770 */ 771 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 772 { 773 return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); 774 } 775 776 /** 777 * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address 778 * from CPU's view 779 * 780 * @adev: amdgpu_device pointer 781 * @bo: amdgpu buffer object 782 */ 783 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) 784 { 785 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; 786 } 787 788 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) 789 { 790 struct amdgpu_bo *vram_bo = NULL; 791 uint64_t vram_gpu = 0; 792 void *vram_ptr = NULL; 793 794 int ret, size = 0x100000; 795 uint8_t cptr[10]; 796 797 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 798 AMDGPU_GEM_DOMAIN_VRAM, 799 &vram_bo, 800 &vram_gpu, 801 &vram_ptr); 802 if (ret) 803 return ret; 804 805 memset(vram_ptr, 0x86, size); 806 memset(cptr, 0x86, 10); 807 808 /** 809 * Check the start, the mid, and the end of the memory if the content of 810 * each byte is the pattern "0x86". If yes, we suppose the vram bo is 811 * workable. 812 * 813 * Note: If check the each byte of whole 1M bo, it will cost too many 814 * seconds, so here, we just pick up three parts for emulation. 815 */ 816 ret = memcmp(vram_ptr, cptr, 10); 817 if (ret) 818 return ret; 819 820 ret = memcmp(vram_ptr + (size / 2), cptr, 10); 821 if (ret) 822 return ret; 823 824 ret = memcmp(vram_ptr + size - 10, cptr, 10); 825 if (ret) 826 return ret; 827 828 amdgpu_bo_free_kernel(&vram_bo, &vram_gpu, 829 &vram_ptr); 830 831 return 0; 832 } 833