1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #ifdef CONFIG_X86
29 #include <asm/hypervisor.h>
30 #endif
31 
32 #include "amdgpu.h"
33 #include "amdgpu_gmc.h"
34 #include "amdgpu_ras.h"
35 #include "amdgpu_xgmi.h"
36 
37 #include <drm/drm_drv.h>
38 #include <drm/ttm/ttm_tt.h>
39 
40 /**
41  * amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
42  *
43  * @adev: amdgpu_device pointer
44  *
45  * Allocate video memory for pdb0 and map it for CPU access
46  * Returns 0 for success, error for failure.
47  */
48 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)
49 {
50 	int r;
51 	struct amdgpu_bo_param bp;
52 	u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
53 	uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
54 	uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift;
55 
56 	memset(&bp, 0, sizeof(bp));
57 	bp.size = PAGE_ALIGN((npdes + 1) * 8);
58 	bp.byte_align = PAGE_SIZE;
59 	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
60 	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
61 		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
62 	bp.type = ttm_bo_type_kernel;
63 	bp.resv = NULL;
64 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
65 
66 	r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
67 	if (r)
68 		return r;
69 
70 	r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
71 	if (unlikely(r != 0))
72 		goto bo_reserve_failure;
73 
74 	r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
75 	if (r)
76 		goto bo_pin_failure;
77 	r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
78 	if (r)
79 		goto bo_kmap_failure;
80 
81 	amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
82 	return 0;
83 
84 bo_kmap_failure:
85 	amdgpu_bo_unpin(adev->gmc.pdb0_bo);
86 bo_pin_failure:
87 	amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
88 bo_reserve_failure:
89 	amdgpu_bo_unref(&adev->gmc.pdb0_bo);
90 	return r;
91 }
92 
93 /**
94  * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
95  *
96  * @bo: the BO to get the PDE for
97  * @level: the level in the PD hirarchy
98  * @addr: resulting addr
99  * @flags: resulting flags
100  *
101  * Get the address and flags to be used for a PDE (Page Directory Entry).
102  */
103 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
104 			       uint64_t *addr, uint64_t *flags)
105 {
106 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
107 
108 	switch (bo->tbo.resource->mem_type) {
109 	case TTM_PL_TT:
110 		*addr = bo->tbo.ttm->dma_address[0];
111 		break;
112 	case TTM_PL_VRAM:
113 		*addr = amdgpu_bo_gpu_offset(bo);
114 		break;
115 	default:
116 		*addr = 0;
117 		break;
118 	}
119 	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
120 	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
121 }
122 
123 /*
124  * amdgpu_gmc_pd_addr - return the address of the root directory
125  */
126 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
127 {
128 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
129 	uint64_t pd_addr;
130 
131 	/* TODO: move that into ASIC specific code */
132 	if (adev->asic_type >= CHIP_VEGA10) {
133 		uint64_t flags = AMDGPU_PTE_VALID;
134 
135 		amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
136 		pd_addr |= flags;
137 	} else {
138 		pd_addr = amdgpu_bo_gpu_offset(bo);
139 	}
140 	return pd_addr;
141 }
142 
143 /**
144  * amdgpu_gmc_set_pte_pde - update the page tables using CPU
145  *
146  * @adev: amdgpu_device pointer
147  * @cpu_pt_addr: cpu address of the page table
148  * @gpu_page_idx: entry in the page table to update
149  * @addr: dst addr to write into pte/pde
150  * @flags: access flags
151  *
152  * Update the page tables using CPU.
153  */
154 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
155 				uint32_t gpu_page_idx, uint64_t addr,
156 				uint64_t flags)
157 {
158 	void __iomem *ptr = (void *)cpu_pt_addr;
159 	uint64_t value;
160 
161 	/*
162 	 * The following is for PTE only. GART does not have PDEs.
163 	*/
164 	value = addr & 0x0000FFFFFFFFF000ULL;
165 	value |= flags;
166 	writeq(value, ptr + (gpu_page_idx * 8));
167 
168 	return 0;
169 }
170 
171 /**
172  * amdgpu_gmc_agp_addr - return the address in the AGP address space
173  *
174  * @bo: TTM BO which needs the address, must be in GTT domain
175  *
176  * Tries to figure out how to access the BO through the AGP aperture. Returns
177  * AMDGPU_BO_INVALID_OFFSET if that is not possible.
178  */
179 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
180 {
181 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
182 
183 	if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
184 		return AMDGPU_BO_INVALID_OFFSET;
185 
186 	if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
187 		return AMDGPU_BO_INVALID_OFFSET;
188 
189 	return adev->gmc.agp_start + bo->ttm->dma_address[0];
190 }
191 
192 /**
193  * amdgpu_gmc_vram_location - try to find VRAM location
194  *
195  * @adev: amdgpu device structure holding all necessary information
196  * @mc: memory controller structure holding memory information
197  * @base: base address at which to put VRAM
198  *
199  * Function will try to place VRAM at base address provided
200  * as parameter.
201  */
202 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
203 			      u64 base)
204 {
205 	uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20;
206 	uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
207 
208 	mc->vram_start = base;
209 	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
210 	if (limit < mc->real_vram_size)
211 		mc->real_vram_size = limit;
212 
213 	if (vis_limit && vis_limit < mc->visible_vram_size)
214 		mc->visible_vram_size = vis_limit;
215 
216 	if (mc->real_vram_size < mc->visible_vram_size)
217 		mc->visible_vram_size = mc->real_vram_size;
218 
219 	if (mc->xgmi.num_physical_nodes == 0) {
220 		mc->fb_start = mc->vram_start;
221 		mc->fb_end = mc->vram_end;
222 	}
223 	dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
224 			mc->mc_vram_size >> 20, mc->vram_start,
225 			mc->vram_end, mc->real_vram_size >> 20);
226 }
227 
228 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
229  *
230  * @adev: amdgpu device structure holding all necessary information
231  * @mc: memory controller structure holding memory information
232  *
233  * This function is only used if use GART for FB translation. In such
234  * case, we use sysvm aperture (vmid0 page tables) for both vram
235  * and gart (aka system memory) access.
236  *
237  * GPUVM (and our organization of vmid0 page tables) require sysvm
238  * aperture to be placed at a location aligned with 8 times of native
239  * page size. For example, if vm_context0_cntl.page_table_block_size
240  * is 12, then native page size is 8G (2M*2^12), sysvm should start
241  * with a 64G aligned address. For simplicity, we just put sysvm at
242  * address 0. So vram start at address 0 and gart is right after vram.
243  */
244 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
245 {
246 	u64 hive_vram_start = 0;
247 	u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
248 	mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
249 	mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
250 	mc->gart_start = hive_vram_end + 1;
251 	mc->gart_end = mc->gart_start + mc->gart_size - 1;
252 	mc->fb_start = hive_vram_start;
253 	mc->fb_end = hive_vram_end;
254 	dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
255 			mc->mc_vram_size >> 20, mc->vram_start,
256 			mc->vram_end, mc->real_vram_size >> 20);
257 	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
258 			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
259 }
260 
261 /**
262  * amdgpu_gmc_gart_location - try to find GART location
263  *
264  * @adev: amdgpu device structure holding all necessary information
265  * @mc: memory controller structure holding memory information
266  *
267  * Function will place try to place GART before or after VRAM.
268  * If GART size is bigger than space left then we ajust GART size.
269  * Thus function will never fails.
270  */
271 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
272 {
273 	const uint64_t four_gb = 0x100000000ULL;
274 	u64 size_af, size_bf;
275 	/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
276 	u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
277 
278 	/* VCE doesn't like it when BOs cross a 4GB segment, so align
279 	 * the GART base on a 4GB boundary as well.
280 	 */
281 	size_bf = mc->fb_start;
282 	size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
283 
284 	if (mc->gart_size > max(size_bf, size_af)) {
285 		dev_warn(adev->dev, "limiting GART\n");
286 		mc->gart_size = max(size_bf, size_af);
287 	}
288 
289 	if ((size_bf >= mc->gart_size && size_bf < size_af) ||
290 	    (size_af < mc->gart_size))
291 		mc->gart_start = 0;
292 	else
293 		mc->gart_start = max_mc_address - mc->gart_size + 1;
294 
295 	mc->gart_start &= ~(four_gb - 1);
296 	mc->gart_end = mc->gart_start + mc->gart_size - 1;
297 	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
298 			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
299 }
300 
301 /**
302  * amdgpu_gmc_agp_location - try to find AGP location
303  * @adev: amdgpu device structure holding all necessary information
304  * @mc: memory controller structure holding memory information
305  *
306  * Function will place try to find a place for the AGP BAR in the MC address
307  * space.
308  *
309  * AGP BAR will be assigned the largest available hole in the address space.
310  * Should be called after VRAM and GART locations are setup.
311  */
312 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
313 {
314 	const uint64_t sixteen_gb = 1ULL << 34;
315 	const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
316 	u64 size_af, size_bf;
317 
318 	if (amdgpu_sriov_vf(adev)) {
319 		mc->agp_start = 0xffffffffffff;
320 		mc->agp_end = 0x0;
321 		mc->agp_size = 0;
322 
323 		return;
324 	}
325 
326 	if (mc->fb_start > mc->gart_start) {
327 		size_bf = (mc->fb_start & sixteen_gb_mask) -
328 			ALIGN(mc->gart_end + 1, sixteen_gb);
329 		size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
330 	} else {
331 		size_bf = mc->fb_start & sixteen_gb_mask;
332 		size_af = (mc->gart_start & sixteen_gb_mask) -
333 			ALIGN(mc->fb_end + 1, sixteen_gb);
334 	}
335 
336 	if (size_bf > size_af) {
337 		mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
338 		mc->agp_size = size_bf;
339 	} else {
340 		mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
341 		mc->agp_size = size_af;
342 	}
343 
344 	mc->agp_end = mc->agp_start + mc->agp_size - 1;
345 	dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
346 			mc->agp_size >> 20, mc->agp_start, mc->agp_end);
347 }
348 
349 /**
350  * amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
351  *
352  * @addr: 48 bit physical address, page aligned (36 significant bits)
353  * @pasid: 16 bit process address space identifier
354  */
355 static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
356 {
357 	return addr << 4 | pasid;
358 }
359 
360 /**
361  * amdgpu_gmc_filter_faults - filter VM faults
362  *
363  * @adev: amdgpu device structure
364  * @ih: interrupt ring that the fault received from
365  * @addr: address of the VM fault
366  * @pasid: PASID of the process causing the fault
367  * @timestamp: timestamp of the fault
368  *
369  * Returns:
370  * True if the fault was filtered and should not be processed further.
371  * False if the fault is a new one and needs to be handled.
372  */
373 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
374 			      struct amdgpu_ih_ring *ih, uint64_t addr,
375 			      uint16_t pasid, uint64_t timestamp)
376 {
377 	struct amdgpu_gmc *gmc = &adev->gmc;
378 	uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
379 	struct amdgpu_gmc_fault *fault;
380 	uint32_t hash;
381 
382 	/* Stale retry fault if timestamp goes backward */
383 	if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))
384 		return true;
385 
386 	/* If we don't have space left in the ring buffer return immediately */
387 	stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
388 		AMDGPU_GMC_FAULT_TIMEOUT;
389 	if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
390 		return true;
391 
392 	/* Try to find the fault in the hash */
393 	hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
394 	fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
395 	while (fault->timestamp >= stamp) {
396 		uint64_t tmp;
397 
398 		if (atomic64_read(&fault->key) == key)
399 			return true;
400 
401 		tmp = fault->timestamp;
402 		fault = &gmc->fault_ring[fault->next];
403 
404 		/* Check if the entry was reused */
405 		if (fault->timestamp >= tmp)
406 			break;
407 	}
408 
409 	/* Add the fault to the ring */
410 	fault = &gmc->fault_ring[gmc->last_fault];
411 	atomic64_set(&fault->key, key);
412 	fault->timestamp = timestamp;
413 
414 	/* And update the hash */
415 	fault->next = gmc->fault_hash[hash].idx;
416 	gmc->fault_hash[hash].idx = gmc->last_fault++;
417 	return false;
418 }
419 
420 /**
421  * amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
422  *
423  * @adev: amdgpu device structure
424  * @addr: address of the VM fault
425  * @pasid: PASID of the process causing the fault
426  *
427  * Remove the address from fault filter, then future vm fault on this address
428  * will pass to retry fault handler to recover.
429  */
430 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
431 				     uint16_t pasid)
432 {
433 	struct amdgpu_gmc *gmc = &adev->gmc;
434 	uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
435 	struct amdgpu_gmc_fault *fault;
436 	uint32_t hash;
437 	uint64_t tmp;
438 
439 	hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
440 	fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
441 	do {
442 		if (atomic64_cmpxchg(&fault->key, key, 0) == key)
443 			break;
444 
445 		tmp = fault->timestamp;
446 		fault = &gmc->fault_ring[fault->next];
447 	} while (fault->timestamp < tmp);
448 }
449 
450 int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev)
451 {
452 	if (!adev->gmc.xgmi.connected_to_cpu) {
453 		adev->gmc.xgmi.ras = &xgmi_ras;
454 		amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
455 		adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm;
456 	}
457 
458 	return 0;
459 }
460 
461 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
462 {
463 	return 0;
464 }
465 
466 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
467 {
468 
469 }
470 
471 	/*
472 	 * The latest engine allocation on gfx9/10 is:
473 	 * Engine 2, 3: firmware
474 	 * Engine 0, 1, 4~16: amdgpu ring,
475 	 *                    subject to change when ring number changes
476 	 * Engine 17: Gart flushes
477 	 */
478 #define GFXHUB_FREE_VM_INV_ENGS_BITMAP		0x1FFF3
479 #define MMHUB_FREE_VM_INV_ENGS_BITMAP		0x1FFF3
480 
481 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
482 {
483 	struct amdgpu_ring *ring;
484 	unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
485 		{GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
486 		GFXHUB_FREE_VM_INV_ENGS_BITMAP};
487 	unsigned i;
488 	unsigned vmhub, inv_eng;
489 
490 	if (adev->enable_mes) {
491 		/* reserve engine 5 for firmware */
492 		for (vmhub = 0; vmhub < AMDGPU_MAX_VMHUBS; vmhub++)
493 			vm_inv_engs[vmhub] &= ~(1 << 5);
494 	}
495 
496 	for (i = 0; i < adev->num_rings; ++i) {
497 		ring = adev->rings[i];
498 		vmhub = ring->funcs->vmhub;
499 
500 		if (ring == &adev->mes.ring)
501 			continue;
502 
503 		inv_eng = ffs(vm_inv_engs[vmhub]);
504 		if (!inv_eng) {
505 			dev_err(adev->dev, "no VM inv eng for ring %s\n",
506 				ring->name);
507 			return -EINVAL;
508 		}
509 
510 		ring->vm_inv_eng = inv_eng - 1;
511 		vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
512 
513 		dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
514 			 ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
515 	}
516 
517 	return 0;
518 }
519 
520 /**
521  * amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
522  * @adev: amdgpu_device pointer
523  *
524  * Check and set if an the device @adev supports Trusted Memory
525  * Zones (TMZ).
526  */
527 void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
528 {
529 	switch (adev->ip_versions[GC_HWIP][0]) {
530 	/* RAVEN */
531 	case IP_VERSION(9, 2, 2):
532 	case IP_VERSION(9, 1, 0):
533 	/* RENOIR looks like RAVEN */
534 	case IP_VERSION(9, 3, 0):
535 	/* GC 10.3.7 */
536 	case IP_VERSION(10, 3, 7):
537 		if (amdgpu_tmz == 0) {
538 			adev->gmc.tmz_enabled = false;
539 			dev_info(adev->dev,
540 				 "Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");
541 		} else {
542 			adev->gmc.tmz_enabled = true;
543 			dev_info(adev->dev,
544 				 "Trusted Memory Zone (TMZ) feature enabled\n");
545 		}
546 		break;
547 	case IP_VERSION(10, 1, 10):
548 	case IP_VERSION(10, 1, 1):
549 	case IP_VERSION(10, 1, 2):
550 	case IP_VERSION(10, 1, 3):
551 	case IP_VERSION(10, 3, 0):
552 	case IP_VERSION(10, 3, 2):
553 	case IP_VERSION(10, 3, 4):
554 	case IP_VERSION(10, 3, 5):
555 	case IP_VERSION(10, 3, 6):
556 	/* VANGOGH */
557 	case IP_VERSION(10, 3, 1):
558 	/* YELLOW_CARP*/
559 	case IP_VERSION(10, 3, 3):
560 	case IP_VERSION(11, 0, 1):
561 	case IP_VERSION(11, 0, 4):
562 		/* Don't enable it by default yet.
563 		 */
564 		if (amdgpu_tmz < 1) {
565 			adev->gmc.tmz_enabled = false;
566 			dev_info(adev->dev,
567 				 "Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");
568 		} else {
569 			adev->gmc.tmz_enabled = true;
570 			dev_info(adev->dev,
571 				 "Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");
572 		}
573 		break;
574 	default:
575 		adev->gmc.tmz_enabled = false;
576 		dev_info(adev->dev,
577 			 "Trusted Memory Zone (TMZ) feature not supported\n");
578 		break;
579 	}
580 }
581 
582 /**
583  * amdgpu_gmc_noretry_set -- set per asic noretry defaults
584  * @adev: amdgpu_device pointer
585  *
586  * Set a per asic default for the no-retry parameter.
587  *
588  */
589 void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
590 {
591 	struct amdgpu_gmc *gmc = &adev->gmc;
592 	uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
593 	bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||
594 				gc_ver == IP_VERSION(9, 3, 0) ||
595 				gc_ver == IP_VERSION(9, 4, 0) ||
596 				gc_ver == IP_VERSION(9, 4, 1) ||
597 				gc_ver == IP_VERSION(9, 4, 2) ||
598 				gc_ver >= IP_VERSION(10, 3, 0));
599 
600 	gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
601 }
602 
603 void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
604 				   bool enable)
605 {
606 	struct amdgpu_vmhub *hub;
607 	u32 tmp, reg, i;
608 
609 	hub = &adev->vmhub[hub_type];
610 	for (i = 0; i < 16; i++) {
611 		reg = hub->vm_context0_cntl + hub->ctx_distance * i;
612 
613 		tmp = (hub_type == AMDGPU_GFXHUB_0) ?
614 			RREG32_SOC15_IP(GC, reg) :
615 			RREG32_SOC15_IP(MMHUB, reg);
616 
617 		if (enable)
618 			tmp |= hub->vm_cntx_cntl_vm_fault;
619 		else
620 			tmp &= ~hub->vm_cntx_cntl_vm_fault;
621 
622 		(hub_type == AMDGPU_GFXHUB_0) ?
623 			WREG32_SOC15_IP(GC, reg, tmp) :
624 			WREG32_SOC15_IP(MMHUB, reg, tmp);
625 	}
626 }
627 
628 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
629 {
630 	unsigned size;
631 
632 	/*
633 	 * Some ASICs need to reserve a region of video memory to avoid access
634 	 * from driver
635 	 */
636 	adev->mman.stolen_reserved_offset = 0;
637 	adev->mman.stolen_reserved_size = 0;
638 
639 	/*
640 	 * TODO:
641 	 * Currently there is a bug where some memory client outside
642 	 * of the driver writes to first 8M of VRAM on S3 resume,
643 	 * this overrides GART which by default gets placed in first 8M and
644 	 * causes VM_FAULTS once GTT is accessed.
645 	 * Keep the stolen memory reservation until the while this is not solved.
646 	 */
647 	switch (adev->asic_type) {
648 	case CHIP_VEGA10:
649 		adev->mman.keep_stolen_vga_memory = true;
650 		/*
651 		 * VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area.
652 		 */
653 #ifdef CONFIG_X86
654 		if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) {
655 			adev->mman.stolen_reserved_offset = 0x500000;
656 			adev->mman.stolen_reserved_size = 0x200000;
657 		}
658 #endif
659 		break;
660 	case CHIP_RAVEN:
661 	case CHIP_RENOIR:
662 		adev->mman.keep_stolen_vga_memory = true;
663 		break;
664 	case CHIP_YELLOW_CARP:
665 		if (amdgpu_discovery == 0) {
666 			adev->mman.stolen_reserved_offset = 0x1ffb0000;
667 			adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
668 		}
669 		break;
670 	default:
671 		adev->mman.keep_stolen_vga_memory = false;
672 		break;
673 	}
674 
675 	if (amdgpu_sriov_vf(adev) ||
676 	    !amdgpu_device_has_display_hardware(adev)) {
677 		size = 0;
678 	} else {
679 		size = amdgpu_gmc_get_vbios_fb_size(adev);
680 
681 		if (adev->mman.keep_stolen_vga_memory)
682 			size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
683 	}
684 
685 	/* set to 0 if the pre-OS buffer uses up most of vram */
686 	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
687 		size = 0;
688 
689 	if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {
690 		adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;
691 		adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;
692 	} else {
693 		adev->mman.stolen_vga_size = size;
694 		adev->mman.stolen_extended_size = 0;
695 	}
696 }
697 
698 /**
699  * amdgpu_gmc_init_pdb0 - initialize PDB0
700  *
701  * @adev: amdgpu_device pointer
702  *
703  * This function is only used when GART page table is used
704  * for FB address translatioin. In such a case, we construct
705  * a 2-level system VM page table: PDB0->PTB, to cover both
706  * VRAM of the hive and system memory.
707  *
708  * PDB0 is static, initialized once on driver initialization.
709  * The first n entries of PDB0 are used as PTE by setting
710  * P bit to 1, pointing to VRAM. The n+1'th entry points
711  * to a big PTB covering system memory.
712  *
713  */
714 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
715 {
716 	int i;
717 	uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?
718 	/* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M
719 	 */
720 	u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
721 	u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
722 	u64 vram_addr = adev->vm_manager.vram_base_offset -
723 		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
724 	u64 vram_end = vram_addr + vram_size;
725 	u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
726 	int idx;
727 
728 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
729 		return;
730 
731 	flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
732 	flags |= AMDGPU_PTE_WRITEABLE;
733 	flags |= AMDGPU_PTE_SNOOPED;
734 	flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
735 	flags |= AMDGPU_PDE_PTE;
736 
737 	/* The first n PDE0 entries are used as PTE,
738 	 * pointing to vram
739 	 */
740 	for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)
741 		amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
742 
743 	/* The n+1'th PDE0 entry points to a huge
744 	 * PTB who has more than 512 entries each
745 	 * pointing to a 4K system page
746 	 */
747 	flags = AMDGPU_PTE_VALID;
748 	flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
749 	/* Requires gart_ptb_gpu_pa to be 4K aligned */
750 	amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
751 	drm_dev_exit(idx);
752 }
753 
754 /**
755  * amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
756  * address
757  *
758  * @adev: amdgpu_device pointer
759  * @mc_addr: MC address of buffer
760  */
761 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
762 {
763 	return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
764 }
765 
766 /**
767  * amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
768  * GPU's view
769  *
770  * @adev: amdgpu_device pointer
771  * @bo: amdgpu buffer object
772  */
773 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
774 {
775 	return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
776 }
777 
778 /**
779  * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
780  * from CPU's view
781  *
782  * @adev: amdgpu_device pointer
783  * @bo: amdgpu buffer object
784  */
785 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
786 {
787 	return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
788 }
789 
790 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
791 {
792 	struct amdgpu_bo *vram_bo = NULL;
793 	uint64_t vram_gpu = 0;
794 	void *vram_ptr = NULL;
795 
796 	int ret, size = 0x100000;
797 	uint8_t cptr[10];
798 
799 	ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
800 				AMDGPU_GEM_DOMAIN_VRAM,
801 				&vram_bo,
802 				&vram_gpu,
803 				&vram_ptr);
804 	if (ret)
805 		return ret;
806 
807 	memset(vram_ptr, 0x86, size);
808 	memset(cptr, 0x86, 10);
809 
810 	/**
811 	 * Check the start, the mid, and the end of the memory if the content of
812 	 * each byte is the pattern "0x86". If yes, we suppose the vram bo is
813 	 * workable.
814 	 *
815 	 * Note: If check the each byte of whole 1M bo, it will cost too many
816 	 * seconds, so here, we just pick up three parts for emulation.
817 	 */
818 	ret = memcmp(vram_ptr, cptr, 10);
819 	if (ret)
820 		return ret;
821 
822 	ret = memcmp(vram_ptr + (size / 2), cptr, 10);
823 	if (ret)
824 		return ret;
825 
826 	ret = memcmp(vram_ptr + size - 10, cptr, 10);
827 	if (ret)
828 		return ret;
829 
830 	amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,
831 			&vram_ptr);
832 
833 	return 0;
834 }
835