1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 37 /* GFX current status */ 38 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 39 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 40 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 41 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 42 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 43 44 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 45 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 46 47 enum amdgpu_gfx_pipe_priority { 48 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 49 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 50 }; 51 52 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 53 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 54 55 struct amdgpu_mec { 56 struct amdgpu_bo *hpd_eop_obj; 57 u64 hpd_eop_gpu_addr; 58 struct amdgpu_bo *mec_fw_obj; 59 u64 mec_fw_gpu_addr; 60 struct amdgpu_bo *mec_fw_data_obj; 61 u64 mec_fw_data_gpu_addr; 62 63 u32 num_mec; 64 u32 num_pipe_per_mec; 65 u32 num_queue_per_pipe; 66 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 67 68 /* These are the resources for which amdgpu takes ownership */ 69 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 70 }; 71 72 enum amdgpu_unmap_queues_action { 73 PREEMPT_QUEUES = 0, 74 RESET_QUEUES, 75 DISABLE_PROCESS_QUEUES, 76 PREEMPT_QUEUES_NO_UNMAP, 77 }; 78 79 struct kiq_pm4_funcs { 80 /* Support ASIC-specific kiq pm4 packets*/ 81 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 82 uint64_t queue_mask); 83 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 84 struct amdgpu_ring *ring); 85 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 86 struct amdgpu_ring *ring, 87 enum amdgpu_unmap_queues_action action, 88 u64 gpu_addr, u64 seq); 89 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 90 struct amdgpu_ring *ring, 91 u64 addr, 92 u64 seq); 93 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 94 uint16_t pasid, uint32_t flush_type, 95 bool all_hub); 96 /* Packet sizes */ 97 int set_resources_size; 98 int map_queues_size; 99 int unmap_queues_size; 100 int query_status_size; 101 int invalidate_tlbs_size; 102 }; 103 104 struct amdgpu_kiq { 105 u64 eop_gpu_addr; 106 struct amdgpu_bo *eop_obj; 107 spinlock_t ring_lock; 108 struct amdgpu_ring ring; 109 struct amdgpu_irq_src irq; 110 const struct kiq_pm4_funcs *pmf; 111 }; 112 113 /* 114 * GPU scratch registers structures, functions & helpers 115 */ 116 struct amdgpu_scratch { 117 unsigned num_reg; 118 uint32_t reg_base; 119 uint32_t free_mask; 120 }; 121 122 /* 123 * GFX configurations 124 */ 125 #define AMDGPU_GFX_MAX_SE 4 126 #define AMDGPU_GFX_MAX_SH_PER_SE 2 127 128 struct amdgpu_rb_config { 129 uint32_t rb_backend_disable; 130 uint32_t user_rb_backend_disable; 131 uint32_t raster_config; 132 uint32_t raster_config_1; 133 }; 134 135 struct gb_addr_config { 136 uint16_t pipe_interleave_size; 137 uint8_t num_pipes; 138 uint8_t max_compress_frags; 139 uint8_t num_banks; 140 uint8_t num_se; 141 uint8_t num_rb_per_se; 142 uint8_t num_pkrs; 143 }; 144 145 struct amdgpu_gfx_config { 146 unsigned max_shader_engines; 147 unsigned max_tile_pipes; 148 unsigned max_cu_per_sh; 149 unsigned max_sh_per_se; 150 unsigned max_backends_per_se; 151 unsigned max_texture_channel_caches; 152 unsigned max_gprs; 153 unsigned max_gs_threads; 154 unsigned max_hw_contexts; 155 unsigned sc_prim_fifo_size_frontend; 156 unsigned sc_prim_fifo_size_backend; 157 unsigned sc_hiz_tile_fifo_size; 158 unsigned sc_earlyz_tile_fifo_size; 159 160 unsigned num_tile_pipes; 161 unsigned backend_enable_mask; 162 unsigned mem_max_burst_length_bytes; 163 unsigned mem_row_size_in_kb; 164 unsigned shader_engine_tile_size; 165 unsigned num_gpus; 166 unsigned multi_gpu_tile_size; 167 unsigned mc_arb_ramcfg; 168 unsigned num_banks; 169 unsigned num_ranks; 170 unsigned gb_addr_config; 171 unsigned num_rbs; 172 unsigned gs_vgt_table_depth; 173 unsigned gs_prim_buffer_depth; 174 175 uint32_t tile_mode_array[32]; 176 uint32_t macrotile_mode_array[16]; 177 178 struct gb_addr_config gb_addr_config_fields; 179 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 180 181 /* gfx configure feature */ 182 uint32_t double_offchip_lds_buf; 183 /* cached value of DB_DEBUG2 */ 184 uint32_t db_debug2; 185 /* gfx10 specific config */ 186 uint32_t num_sc_per_sh; 187 uint32_t num_packer_per_sc; 188 uint32_t pa_sc_tile_steering_override; 189 uint64_t tcc_disabled_mask; 190 uint32_t gc_num_tcp_per_sa; 191 uint32_t gc_num_sdp_interface; 192 uint32_t gc_num_tcps; 193 uint32_t gc_num_tcp_per_wpg; 194 uint32_t gc_tcp_l1_size; 195 uint32_t gc_num_sqc_per_wgp; 196 uint32_t gc_l1_instruction_cache_size_per_sqc; 197 uint32_t gc_l1_data_cache_size_per_sqc; 198 uint32_t gc_gl1c_per_sa; 199 uint32_t gc_gl1c_size_per_instance; 200 uint32_t gc_gl2c_per_gpu; 201 }; 202 203 struct amdgpu_cu_info { 204 uint32_t simd_per_cu; 205 uint32_t max_waves_per_simd; 206 uint32_t wave_front_size; 207 uint32_t max_scratch_slots_per_cu; 208 uint32_t lds_size; 209 210 /* total active CU number */ 211 uint32_t number; 212 uint32_t ao_cu_mask; 213 uint32_t ao_cu_bitmap[4][4]; 214 uint32_t bitmap[4][4]; 215 }; 216 217 struct amdgpu_gfx_ras { 218 struct amdgpu_ras_block_object ras_block; 219 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 220 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev); 221 }; 222 223 struct amdgpu_gfx_funcs { 224 /* get the gpu clock counter */ 225 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 226 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 227 u32 sh_num, u32 instance); 228 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 229 uint32_t wave, uint32_t *dst, int *no_fields); 230 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 231 uint32_t wave, uint32_t thread, uint32_t start, 232 uint32_t size, uint32_t *dst); 233 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 234 uint32_t wave, uint32_t start, uint32_t size, 235 uint32_t *dst); 236 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 237 u32 queue, u32 vmid); 238 void (*init_spm_golden)(struct amdgpu_device *adev); 239 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 240 }; 241 242 struct sq_work { 243 struct work_struct work; 244 unsigned ih_data; 245 }; 246 247 struct amdgpu_pfp { 248 struct amdgpu_bo *pfp_fw_obj; 249 uint64_t pfp_fw_gpu_addr; 250 uint32_t *pfp_fw_ptr; 251 252 struct amdgpu_bo *pfp_fw_data_obj; 253 uint64_t pfp_fw_data_gpu_addr; 254 uint32_t *pfp_fw_data_ptr; 255 }; 256 257 struct amdgpu_ce { 258 struct amdgpu_bo *ce_fw_obj; 259 uint64_t ce_fw_gpu_addr; 260 uint32_t *ce_fw_ptr; 261 }; 262 263 struct amdgpu_me { 264 struct amdgpu_bo *me_fw_obj; 265 uint64_t me_fw_gpu_addr; 266 uint32_t *me_fw_ptr; 267 268 struct amdgpu_bo *me_fw_data_obj; 269 uint64_t me_fw_data_gpu_addr; 270 uint32_t *me_fw_data_ptr; 271 272 uint32_t num_me; 273 uint32_t num_pipe_per_me; 274 uint32_t num_queue_per_pipe; 275 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 276 277 /* These are the resources for which amdgpu takes ownership */ 278 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 279 }; 280 281 struct amdgpu_gfx { 282 struct mutex gpu_clock_mutex; 283 struct amdgpu_gfx_config config; 284 struct amdgpu_rlc rlc; 285 struct amdgpu_pfp pfp; 286 struct amdgpu_ce ce; 287 struct amdgpu_me me; 288 struct amdgpu_mec mec; 289 struct amdgpu_kiq kiq; 290 struct amdgpu_imu imu; 291 struct amdgpu_scratch scratch; 292 bool rs64_enable; /* firmware format */ 293 const struct firmware *me_fw; /* ME firmware */ 294 uint32_t me_fw_version; 295 const struct firmware *pfp_fw; /* PFP firmware */ 296 uint32_t pfp_fw_version; 297 const struct firmware *ce_fw; /* CE firmware */ 298 uint32_t ce_fw_version; 299 const struct firmware *rlc_fw; /* RLC firmware */ 300 uint32_t rlc_fw_version; 301 const struct firmware *mec_fw; /* MEC firmware */ 302 uint32_t mec_fw_version; 303 const struct firmware *mec2_fw; /* MEC2 firmware */ 304 uint32_t mec2_fw_version; 305 const struct firmware *imu_fw; /* IMU firmware */ 306 uint32_t imu_fw_version; 307 uint32_t me_feature_version; 308 uint32_t ce_feature_version; 309 uint32_t pfp_feature_version; 310 uint32_t rlc_feature_version; 311 uint32_t rlc_srlc_fw_version; 312 uint32_t rlc_srlc_feature_version; 313 uint32_t rlc_srlg_fw_version; 314 uint32_t rlc_srlg_feature_version; 315 uint32_t rlc_srls_fw_version; 316 uint32_t rlc_srls_feature_version; 317 uint32_t mec_feature_version; 318 uint32_t mec2_feature_version; 319 bool mec_fw_write_wait; 320 bool me_fw_write_wait; 321 bool cp_fw_write_wait; 322 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 323 unsigned num_gfx_rings; 324 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 325 unsigned num_compute_rings; 326 struct amdgpu_irq_src eop_irq; 327 struct amdgpu_irq_src priv_reg_irq; 328 struct amdgpu_irq_src priv_inst_irq; 329 struct amdgpu_irq_src cp_ecc_error_irq; 330 struct amdgpu_irq_src sq_irq; 331 struct sq_work sq_work; 332 333 /* gfx status */ 334 uint32_t gfx_current_status; 335 /* ce ram size*/ 336 unsigned ce_ram_size; 337 struct amdgpu_cu_info cu_info; 338 const struct amdgpu_gfx_funcs *funcs; 339 340 /* reset mask */ 341 uint32_t grbm_soft_reset; 342 uint32_t srbm_soft_reset; 343 344 /* gfx off */ 345 bool gfx_off_state; /* true: enabled, false: disabled */ 346 struct mutex gfx_off_mutex; 347 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 348 struct delayed_work gfx_off_delay_work; 349 350 /* pipe reservation */ 351 struct mutex pipe_reserve_mutex; 352 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 353 354 /*ras */ 355 struct ras_common_if *ras_if; 356 struct amdgpu_gfx_ras *ras; 357 358 bool is_poweron; 359 }; 360 361 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 362 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 363 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 364 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 365 366 /** 367 * amdgpu_gfx_create_bitmask - create a bitmask 368 * 369 * @bit_width: length of the mask 370 * 371 * create a variable length bit mask. 372 * Returns the bitmask. 373 */ 374 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 375 { 376 return (u32)((1ULL << bit_width) - 1); 377 } 378 379 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 380 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 381 382 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 383 unsigned max_sh); 384 385 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 386 struct amdgpu_ring *ring, 387 struct amdgpu_irq_src *irq); 388 389 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 390 391 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 392 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 393 unsigned hpd_size); 394 395 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 396 unsigned mqd_size); 397 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 398 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 399 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 400 401 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 402 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 403 404 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 405 int pipe, int queue); 406 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 407 int *mec, int *pipe, int *queue); 408 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 409 int pipe, int queue); 410 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 411 struct amdgpu_ring *ring); 412 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 413 int pipe, int queue); 414 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 415 int *me, int *pipe, int *queue); 416 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 417 int pipe, int queue); 418 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 419 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 420 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 421 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 422 void *err_data, 423 struct amdgpu_iv_entry *entry); 424 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 425 struct amdgpu_irq_src *source, 426 struct amdgpu_iv_entry *entry); 427 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 428 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 429 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 430 #endif 431