1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "soc15.h" 34 #include "amdgpu_ras.h" 35 36 /* GFX current status */ 37 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 38 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 39 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 40 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 41 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 42 43 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 44 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 45 46 enum amdgpu_gfx_pipe_priority { 47 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 48 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 49 }; 50 51 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 52 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 53 54 struct amdgpu_mec { 55 struct amdgpu_bo *hpd_eop_obj; 56 u64 hpd_eop_gpu_addr; 57 struct amdgpu_bo *mec_fw_obj; 58 u64 mec_fw_gpu_addr; 59 u32 num_mec; 60 u32 num_pipe_per_mec; 61 u32 num_queue_per_pipe; 62 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 63 64 /* These are the resources for which amdgpu takes ownership */ 65 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 66 }; 67 68 enum amdgpu_unmap_queues_action { 69 PREEMPT_QUEUES = 0, 70 RESET_QUEUES, 71 DISABLE_PROCESS_QUEUES, 72 PREEMPT_QUEUES_NO_UNMAP, 73 }; 74 75 struct kiq_pm4_funcs { 76 /* Support ASIC-specific kiq pm4 packets*/ 77 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 78 uint64_t queue_mask); 79 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 80 struct amdgpu_ring *ring); 81 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 82 struct amdgpu_ring *ring, 83 enum amdgpu_unmap_queues_action action, 84 u64 gpu_addr, u64 seq); 85 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 86 struct amdgpu_ring *ring, 87 u64 addr, 88 u64 seq); 89 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 90 uint16_t pasid, uint32_t flush_type, 91 bool all_hub); 92 /* Packet sizes */ 93 int set_resources_size; 94 int map_queues_size; 95 int unmap_queues_size; 96 int query_status_size; 97 int invalidate_tlbs_size; 98 }; 99 100 struct amdgpu_kiq { 101 u64 eop_gpu_addr; 102 struct amdgpu_bo *eop_obj; 103 spinlock_t ring_lock; 104 struct amdgpu_ring ring; 105 struct amdgpu_irq_src irq; 106 const struct kiq_pm4_funcs *pmf; 107 }; 108 109 /* 110 * GPU scratch registers structures, functions & helpers 111 */ 112 struct amdgpu_scratch { 113 unsigned num_reg; 114 uint32_t reg_base; 115 uint32_t free_mask; 116 }; 117 118 /* 119 * GFX configurations 120 */ 121 #define AMDGPU_GFX_MAX_SE 4 122 #define AMDGPU_GFX_MAX_SH_PER_SE 2 123 124 struct amdgpu_rb_config { 125 uint32_t rb_backend_disable; 126 uint32_t user_rb_backend_disable; 127 uint32_t raster_config; 128 uint32_t raster_config_1; 129 }; 130 131 struct gb_addr_config { 132 uint16_t pipe_interleave_size; 133 uint8_t num_pipes; 134 uint8_t max_compress_frags; 135 uint8_t num_banks; 136 uint8_t num_se; 137 uint8_t num_rb_per_se; 138 uint8_t num_pkrs; 139 }; 140 141 struct amdgpu_gfx_config { 142 unsigned max_shader_engines; 143 unsigned max_tile_pipes; 144 unsigned max_cu_per_sh; 145 unsigned max_sh_per_se; 146 unsigned max_backends_per_se; 147 unsigned max_texture_channel_caches; 148 unsigned max_gprs; 149 unsigned max_gs_threads; 150 unsigned max_hw_contexts; 151 unsigned sc_prim_fifo_size_frontend; 152 unsigned sc_prim_fifo_size_backend; 153 unsigned sc_hiz_tile_fifo_size; 154 unsigned sc_earlyz_tile_fifo_size; 155 156 unsigned num_tile_pipes; 157 unsigned backend_enable_mask; 158 unsigned mem_max_burst_length_bytes; 159 unsigned mem_row_size_in_kb; 160 unsigned shader_engine_tile_size; 161 unsigned num_gpus; 162 unsigned multi_gpu_tile_size; 163 unsigned mc_arb_ramcfg; 164 unsigned num_banks; 165 unsigned num_ranks; 166 unsigned gb_addr_config; 167 unsigned num_rbs; 168 unsigned gs_vgt_table_depth; 169 unsigned gs_prim_buffer_depth; 170 171 uint32_t tile_mode_array[32]; 172 uint32_t macrotile_mode_array[16]; 173 174 struct gb_addr_config gb_addr_config_fields; 175 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 176 177 /* gfx configure feature */ 178 uint32_t double_offchip_lds_buf; 179 /* cached value of DB_DEBUG2 */ 180 uint32_t db_debug2; 181 /* gfx10 specific config */ 182 uint32_t num_sc_per_sh; 183 uint32_t num_packer_per_sc; 184 uint32_t pa_sc_tile_steering_override; 185 uint64_t tcc_disabled_mask; 186 uint32_t gc_num_tcp_per_sa; 187 uint32_t gc_num_sdp_interface; 188 uint32_t gc_num_tcps; 189 uint32_t gc_num_tcp_per_wpg; 190 uint32_t gc_tcp_l1_size; 191 uint32_t gc_num_sqc_per_wgp; 192 uint32_t gc_l1_instruction_cache_size_per_sqc; 193 uint32_t gc_l1_data_cache_size_per_sqc; 194 uint32_t gc_gl1c_per_sa; 195 uint32_t gc_gl1c_size_per_instance; 196 uint32_t gc_gl2c_per_gpu; 197 }; 198 199 struct amdgpu_cu_info { 200 uint32_t simd_per_cu; 201 uint32_t max_waves_per_simd; 202 uint32_t wave_front_size; 203 uint32_t max_scratch_slots_per_cu; 204 uint32_t lds_size; 205 206 /* total active CU number */ 207 uint32_t number; 208 uint32_t ao_cu_mask; 209 uint32_t ao_cu_bitmap[4][4]; 210 uint32_t bitmap[4][4]; 211 }; 212 213 struct amdgpu_gfx_ras { 214 struct amdgpu_ras_block_object ras_block; 215 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 216 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev); 217 }; 218 219 struct amdgpu_gfx_funcs { 220 /* get the gpu clock counter */ 221 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 222 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 223 u32 sh_num, u32 instance); 224 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 225 uint32_t wave, uint32_t *dst, int *no_fields); 226 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 227 uint32_t wave, uint32_t thread, uint32_t start, 228 uint32_t size, uint32_t *dst); 229 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 230 uint32_t wave, uint32_t start, uint32_t size, 231 uint32_t *dst); 232 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 233 u32 queue, u32 vmid); 234 void (*init_spm_golden)(struct amdgpu_device *adev); 235 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 236 }; 237 238 struct sq_work { 239 struct work_struct work; 240 unsigned ih_data; 241 }; 242 243 struct amdgpu_pfp { 244 struct amdgpu_bo *pfp_fw_obj; 245 uint64_t pfp_fw_gpu_addr; 246 uint32_t *pfp_fw_ptr; 247 }; 248 249 struct amdgpu_ce { 250 struct amdgpu_bo *ce_fw_obj; 251 uint64_t ce_fw_gpu_addr; 252 uint32_t *ce_fw_ptr; 253 }; 254 255 struct amdgpu_me { 256 struct amdgpu_bo *me_fw_obj; 257 uint64_t me_fw_gpu_addr; 258 uint32_t *me_fw_ptr; 259 uint32_t num_me; 260 uint32_t num_pipe_per_me; 261 uint32_t num_queue_per_pipe; 262 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 263 264 /* These are the resources for which amdgpu takes ownership */ 265 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 266 }; 267 268 struct amdgpu_gfx { 269 struct mutex gpu_clock_mutex; 270 struct amdgpu_gfx_config config; 271 struct amdgpu_rlc rlc; 272 struct amdgpu_pfp pfp; 273 struct amdgpu_ce ce; 274 struct amdgpu_me me; 275 struct amdgpu_mec mec; 276 struct amdgpu_kiq kiq; 277 struct amdgpu_scratch scratch; 278 const struct firmware *me_fw; /* ME firmware */ 279 uint32_t me_fw_version; 280 const struct firmware *pfp_fw; /* PFP firmware */ 281 uint32_t pfp_fw_version; 282 const struct firmware *ce_fw; /* CE firmware */ 283 uint32_t ce_fw_version; 284 const struct firmware *rlc_fw; /* RLC firmware */ 285 uint32_t rlc_fw_version; 286 const struct firmware *mec_fw; /* MEC firmware */ 287 uint32_t mec_fw_version; 288 const struct firmware *mec2_fw; /* MEC2 firmware */ 289 uint32_t mec2_fw_version; 290 uint32_t me_feature_version; 291 uint32_t ce_feature_version; 292 uint32_t pfp_feature_version; 293 uint32_t rlc_feature_version; 294 uint32_t rlc_srlc_fw_version; 295 uint32_t rlc_srlc_feature_version; 296 uint32_t rlc_srlg_fw_version; 297 uint32_t rlc_srlg_feature_version; 298 uint32_t rlc_srls_fw_version; 299 uint32_t rlc_srls_feature_version; 300 uint32_t mec_feature_version; 301 uint32_t mec2_feature_version; 302 bool mec_fw_write_wait; 303 bool me_fw_write_wait; 304 bool cp_fw_write_wait; 305 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 306 unsigned num_gfx_rings; 307 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 308 unsigned num_compute_rings; 309 struct amdgpu_irq_src eop_irq; 310 struct amdgpu_irq_src priv_reg_irq; 311 struct amdgpu_irq_src priv_inst_irq; 312 struct amdgpu_irq_src cp_ecc_error_irq; 313 struct amdgpu_irq_src sq_irq; 314 struct sq_work sq_work; 315 316 /* gfx status */ 317 uint32_t gfx_current_status; 318 /* ce ram size*/ 319 unsigned ce_ram_size; 320 struct amdgpu_cu_info cu_info; 321 const struct amdgpu_gfx_funcs *funcs; 322 323 /* reset mask */ 324 uint32_t grbm_soft_reset; 325 uint32_t srbm_soft_reset; 326 327 /* gfx off */ 328 bool gfx_off_state; /* true: enabled, false: disabled */ 329 struct mutex gfx_off_mutex; 330 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 331 struct delayed_work gfx_off_delay_work; 332 333 /* pipe reservation */ 334 struct mutex pipe_reserve_mutex; 335 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 336 337 /*ras */ 338 struct ras_common_if *ras_if; 339 struct amdgpu_gfx_ras *ras; 340 341 bool is_poweron; 342 }; 343 344 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 345 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 346 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 347 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 348 349 /** 350 * amdgpu_gfx_create_bitmask - create a bitmask 351 * 352 * @bit_width: length of the mask 353 * 354 * create a variable length bit mask. 355 * Returns the bitmask. 356 */ 357 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 358 { 359 return (u32)((1ULL << bit_width) - 1); 360 } 361 362 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 363 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 364 365 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 366 unsigned max_sh); 367 368 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 369 struct amdgpu_ring *ring, 370 struct amdgpu_irq_src *irq); 371 372 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 373 374 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 375 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 376 unsigned hpd_size); 377 378 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 379 unsigned mqd_size); 380 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 381 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 382 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 383 384 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 385 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 386 387 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 388 int pipe, int queue); 389 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 390 int *mec, int *pipe, int *queue); 391 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 392 int pipe, int queue); 393 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 394 struct amdgpu_ring *ring); 395 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 396 int pipe, int queue); 397 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 398 int *me, int *pipe, int *queue); 399 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 400 int pipe, int queue); 401 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 402 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 403 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 404 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 405 void *err_data, 406 struct amdgpu_iv_entry *entry); 407 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 408 struct amdgpu_irq_src *source, 409 struct amdgpu_iv_entry *entry); 410 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 411 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 412 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 413 #endif 414