1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 #include "amdgpu_ring_mux.h" 37 38 /* GFX current status */ 39 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 40 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 41 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 42 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 43 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 44 45 #define AMDGPU_MAX_GC_INSTANCES 8 46 47 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 48 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 49 50 enum amdgpu_gfx_pipe_priority { 51 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 52 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 53 }; 54 55 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 56 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 57 58 enum amdgpu_gfx_partition { 59 AMDGPU_SPX_PARTITION_MODE = 0, 60 AMDGPU_DPX_PARTITION_MODE = 1, 61 AMDGPU_TPX_PARTITION_MODE = 2, 62 AMDGPU_QPX_PARTITION_MODE = 3, 63 AMDGPU_CPX_PARTITION_MODE = 4, 64 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 65 }; 66 67 struct amdgpu_mec { 68 struct amdgpu_bo *hpd_eop_obj; 69 u64 hpd_eop_gpu_addr; 70 struct amdgpu_bo *mec_fw_obj; 71 u64 mec_fw_gpu_addr; 72 struct amdgpu_bo *mec_fw_data_obj; 73 u64 mec_fw_data_gpu_addr; 74 75 u32 num_mec; 76 u32 num_pipe_per_mec; 77 u32 num_queue_per_pipe; 78 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 79 80 /* These are the resources for which amdgpu takes ownership */ 81 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 82 }; 83 84 enum amdgpu_unmap_queues_action { 85 PREEMPT_QUEUES = 0, 86 RESET_QUEUES, 87 DISABLE_PROCESS_QUEUES, 88 PREEMPT_QUEUES_NO_UNMAP, 89 }; 90 91 struct kiq_pm4_funcs { 92 /* Support ASIC-specific kiq pm4 packets*/ 93 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 94 uint64_t queue_mask); 95 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 96 struct amdgpu_ring *ring); 97 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 98 struct amdgpu_ring *ring, 99 enum amdgpu_unmap_queues_action action, 100 u64 gpu_addr, u64 seq); 101 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 102 struct amdgpu_ring *ring, 103 u64 addr, 104 u64 seq); 105 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 106 uint16_t pasid, uint32_t flush_type, 107 bool all_hub); 108 /* Packet sizes */ 109 int set_resources_size; 110 int map_queues_size; 111 int unmap_queues_size; 112 int query_status_size; 113 int invalidate_tlbs_size; 114 }; 115 116 struct amdgpu_kiq { 117 u64 eop_gpu_addr; 118 struct amdgpu_bo *eop_obj; 119 spinlock_t ring_lock; 120 struct amdgpu_ring ring; 121 struct amdgpu_irq_src irq; 122 const struct kiq_pm4_funcs *pmf; 123 }; 124 125 /* 126 * GFX configurations 127 */ 128 #define AMDGPU_GFX_MAX_SE 4 129 #define AMDGPU_GFX_MAX_SH_PER_SE 2 130 131 struct amdgpu_rb_config { 132 uint32_t rb_backend_disable; 133 uint32_t user_rb_backend_disable; 134 uint32_t raster_config; 135 uint32_t raster_config_1; 136 }; 137 138 struct gb_addr_config { 139 uint16_t pipe_interleave_size; 140 uint8_t num_pipes; 141 uint8_t max_compress_frags; 142 uint8_t num_banks; 143 uint8_t num_se; 144 uint8_t num_rb_per_se; 145 uint8_t num_pkrs; 146 }; 147 148 struct amdgpu_gfx_config { 149 unsigned max_shader_engines; 150 unsigned max_tile_pipes; 151 unsigned max_cu_per_sh; 152 unsigned max_sh_per_se; 153 unsigned max_backends_per_se; 154 unsigned max_texture_channel_caches; 155 unsigned max_gprs; 156 unsigned max_gs_threads; 157 unsigned max_hw_contexts; 158 unsigned sc_prim_fifo_size_frontend; 159 unsigned sc_prim_fifo_size_backend; 160 unsigned sc_hiz_tile_fifo_size; 161 unsigned sc_earlyz_tile_fifo_size; 162 163 unsigned num_tile_pipes; 164 unsigned backend_enable_mask; 165 unsigned mem_max_burst_length_bytes; 166 unsigned mem_row_size_in_kb; 167 unsigned shader_engine_tile_size; 168 unsigned num_gpus; 169 unsigned multi_gpu_tile_size; 170 unsigned mc_arb_ramcfg; 171 unsigned num_banks; 172 unsigned num_ranks; 173 unsigned gb_addr_config; 174 unsigned num_rbs; 175 unsigned gs_vgt_table_depth; 176 unsigned gs_prim_buffer_depth; 177 178 uint32_t tile_mode_array[32]; 179 uint32_t macrotile_mode_array[16]; 180 181 struct gb_addr_config gb_addr_config_fields; 182 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 183 184 /* gfx configure feature */ 185 uint32_t double_offchip_lds_buf; 186 /* cached value of DB_DEBUG2 */ 187 uint32_t db_debug2; 188 /* gfx10 specific config */ 189 uint32_t num_sc_per_sh; 190 uint32_t num_packer_per_sc; 191 uint32_t pa_sc_tile_steering_override; 192 /* Whether texture coordinate truncation is conformant. */ 193 bool ta_cntl2_truncate_coord_mode; 194 uint64_t tcc_disabled_mask; 195 uint32_t gc_num_tcp_per_sa; 196 uint32_t gc_num_sdp_interface; 197 uint32_t gc_num_tcps; 198 uint32_t gc_num_tcp_per_wpg; 199 uint32_t gc_tcp_l1_size; 200 uint32_t gc_num_sqc_per_wgp; 201 uint32_t gc_l1_instruction_cache_size_per_sqc; 202 uint32_t gc_l1_data_cache_size_per_sqc; 203 uint32_t gc_gl1c_per_sa; 204 uint32_t gc_gl1c_size_per_instance; 205 uint32_t gc_gl2c_per_gpu; 206 }; 207 208 struct amdgpu_cu_info { 209 uint32_t simd_per_cu; 210 uint32_t max_waves_per_simd; 211 uint32_t wave_front_size; 212 uint32_t max_scratch_slots_per_cu; 213 uint32_t lds_size; 214 215 /* total active CU number */ 216 uint32_t number; 217 uint32_t ao_cu_mask; 218 uint32_t ao_cu_bitmap[4][4]; 219 uint32_t bitmap[4][4]; 220 }; 221 222 struct amdgpu_gfx_ras { 223 struct amdgpu_ras_block_object ras_block; 224 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 225 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev); 226 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 227 struct amdgpu_irq_src *source, 228 struct amdgpu_iv_entry *entry); 229 int (*poison_consumption_handler)(struct amdgpu_device *adev, 230 struct amdgpu_iv_entry *entry); 231 }; 232 233 struct amdgpu_gfx_funcs { 234 /* get the gpu clock counter */ 235 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 236 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 237 u32 sh_num, u32 instance); 238 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 239 uint32_t wave, uint32_t *dst, int *no_fields); 240 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 241 uint32_t wave, uint32_t thread, uint32_t start, 242 uint32_t size, uint32_t *dst); 243 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 244 uint32_t wave, uint32_t start, uint32_t size, 245 uint32_t *dst); 246 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 247 u32 queue, u32 vmid); 248 void (*init_spm_golden)(struct amdgpu_device *adev); 249 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 250 }; 251 252 struct sq_work { 253 struct work_struct work; 254 unsigned ih_data; 255 }; 256 257 struct amdgpu_pfp { 258 struct amdgpu_bo *pfp_fw_obj; 259 uint64_t pfp_fw_gpu_addr; 260 uint32_t *pfp_fw_ptr; 261 262 struct amdgpu_bo *pfp_fw_data_obj; 263 uint64_t pfp_fw_data_gpu_addr; 264 uint32_t *pfp_fw_data_ptr; 265 }; 266 267 struct amdgpu_ce { 268 struct amdgpu_bo *ce_fw_obj; 269 uint64_t ce_fw_gpu_addr; 270 uint32_t *ce_fw_ptr; 271 }; 272 273 struct amdgpu_me { 274 struct amdgpu_bo *me_fw_obj; 275 uint64_t me_fw_gpu_addr; 276 uint32_t *me_fw_ptr; 277 278 struct amdgpu_bo *me_fw_data_obj; 279 uint64_t me_fw_data_gpu_addr; 280 uint32_t *me_fw_data_ptr; 281 282 uint32_t num_me; 283 uint32_t num_pipe_per_me; 284 uint32_t num_queue_per_pipe; 285 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 286 287 /* These are the resources for which amdgpu takes ownership */ 288 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 289 }; 290 291 struct amdgpu_gfx { 292 struct mutex gpu_clock_mutex; 293 struct amdgpu_gfx_config config; 294 struct amdgpu_rlc rlc; 295 struct amdgpu_pfp pfp; 296 struct amdgpu_ce ce; 297 struct amdgpu_me me; 298 struct amdgpu_mec mec; 299 struct amdgpu_kiq kiq; 300 struct amdgpu_imu imu; 301 bool rs64_enable; /* firmware format */ 302 const struct firmware *me_fw; /* ME firmware */ 303 uint32_t me_fw_version; 304 const struct firmware *pfp_fw; /* PFP firmware */ 305 uint32_t pfp_fw_version; 306 const struct firmware *ce_fw; /* CE firmware */ 307 uint32_t ce_fw_version; 308 const struct firmware *rlc_fw; /* RLC firmware */ 309 uint32_t rlc_fw_version; 310 const struct firmware *mec_fw; /* MEC firmware */ 311 uint32_t mec_fw_version; 312 const struct firmware *mec2_fw; /* MEC2 firmware */ 313 uint32_t mec2_fw_version; 314 const struct firmware *imu_fw; /* IMU firmware */ 315 uint32_t imu_fw_version; 316 uint32_t me_feature_version; 317 uint32_t ce_feature_version; 318 uint32_t pfp_feature_version; 319 uint32_t rlc_feature_version; 320 uint32_t rlc_srlc_fw_version; 321 uint32_t rlc_srlc_feature_version; 322 uint32_t rlc_srlg_fw_version; 323 uint32_t rlc_srlg_feature_version; 324 uint32_t rlc_srls_fw_version; 325 uint32_t rlc_srls_feature_version; 326 uint32_t rlcp_ucode_version; 327 uint32_t rlcp_ucode_feature_version; 328 uint32_t rlcv_ucode_version; 329 uint32_t rlcv_ucode_feature_version; 330 uint32_t mec_feature_version; 331 uint32_t mec2_feature_version; 332 bool mec_fw_write_wait; 333 bool me_fw_write_wait; 334 bool cp_fw_write_wait; 335 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 336 unsigned num_gfx_rings; 337 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 338 unsigned num_compute_rings; 339 struct amdgpu_irq_src eop_irq; 340 struct amdgpu_irq_src priv_reg_irq; 341 struct amdgpu_irq_src priv_inst_irq; 342 struct amdgpu_irq_src cp_ecc_error_irq; 343 struct amdgpu_irq_src sq_irq; 344 struct amdgpu_irq_src rlc_gc_fed_irq; 345 struct sq_work sq_work; 346 347 /* gfx status */ 348 uint32_t gfx_current_status; 349 /* ce ram size*/ 350 unsigned ce_ram_size; 351 struct amdgpu_cu_info cu_info; 352 const struct amdgpu_gfx_funcs *funcs; 353 354 /* reset mask */ 355 uint32_t grbm_soft_reset; 356 uint32_t srbm_soft_reset; 357 358 /* gfx off */ 359 bool gfx_off_state; /* true: enabled, false: disabled */ 360 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 361 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 362 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 363 uint32_t gfx_off_residency; /* last logged residency */ 364 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 365 366 /* pipe reservation */ 367 struct mutex pipe_reserve_mutex; 368 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 369 370 /*ras */ 371 struct ras_common_if *ras_if; 372 struct amdgpu_gfx_ras *ras; 373 374 bool is_poweron; 375 376 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 377 struct amdgpu_ring_mux muxer; 378 379 enum amdgpu_gfx_partition partition_mode; 380 uint32_t num_xcd; 381 uint32_t num_xcc_per_xcp; 382 }; 383 384 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 385 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 386 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 387 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 388 389 /** 390 * amdgpu_gfx_create_bitmask - create a bitmask 391 * 392 * @bit_width: length of the mask 393 * 394 * create a variable length bit mask. 395 * Returns the bitmask. 396 */ 397 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 398 { 399 return (u32)((1ULL << bit_width) - 1); 400 } 401 402 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 403 unsigned max_sh); 404 405 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 406 struct amdgpu_ring *ring, 407 struct amdgpu_irq_src *irq); 408 409 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 410 411 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 412 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 413 unsigned hpd_size); 414 415 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 416 unsigned mqd_size); 417 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 418 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 419 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 420 421 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 422 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 423 424 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 425 int pipe, int queue); 426 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 427 int *mec, int *pipe, int *queue); 428 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 429 int pipe, int queue); 430 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 431 struct amdgpu_ring *ring); 432 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 433 struct amdgpu_ring *ring); 434 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 435 int pipe, int queue); 436 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 437 int *me, int *pipe, int *queue); 438 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 439 int pipe, int queue); 440 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 441 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 442 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 443 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 444 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 445 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 446 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 447 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 448 void *err_data, 449 struct amdgpu_iv_entry *entry); 450 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 451 struct amdgpu_irq_src *source, 452 struct amdgpu_iv_entry *entry); 453 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 454 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 455 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 456 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 457 458 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 459 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 460 struct amdgpu_iv_entry *entry); 461 #endif 462