1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 34 /* GFX current status */ 35 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 36 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 37 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 38 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 39 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 40 41 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 42 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 43 44 struct amdgpu_mec { 45 struct amdgpu_bo *hpd_eop_obj; 46 u64 hpd_eop_gpu_addr; 47 struct amdgpu_bo *mec_fw_obj; 48 u64 mec_fw_gpu_addr; 49 u32 num_mec; 50 u32 num_pipe_per_mec; 51 u32 num_queue_per_pipe; 52 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 53 54 /* These are the resources for which amdgpu takes ownership */ 55 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 56 }; 57 58 enum amdgpu_unmap_queues_action { 59 PREEMPT_QUEUES = 0, 60 RESET_QUEUES, 61 DISABLE_PROCESS_QUEUES, 62 PREEMPT_QUEUES_NO_UNMAP, 63 }; 64 65 struct kiq_pm4_funcs { 66 /* Support ASIC-specific kiq pm4 packets*/ 67 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 68 uint64_t queue_mask); 69 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 70 struct amdgpu_ring *ring); 71 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 72 struct amdgpu_ring *ring, 73 enum amdgpu_unmap_queues_action action, 74 u64 gpu_addr, u64 seq); 75 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 76 struct amdgpu_ring *ring, 77 u64 addr, 78 u64 seq); 79 /* Packet sizes */ 80 int set_resources_size; 81 int map_queues_size; 82 int unmap_queues_size; 83 int query_status_size; 84 }; 85 86 struct amdgpu_kiq { 87 u64 eop_gpu_addr; 88 struct amdgpu_bo *eop_obj; 89 spinlock_t ring_lock; 90 struct amdgpu_ring ring; 91 struct amdgpu_irq_src irq; 92 const struct kiq_pm4_funcs *pmf; 93 }; 94 95 /* 96 * GPU scratch registers structures, functions & helpers 97 */ 98 struct amdgpu_scratch { 99 unsigned num_reg; 100 uint32_t reg_base; 101 uint32_t free_mask; 102 }; 103 104 /* 105 * GFX configurations 106 */ 107 #define AMDGPU_GFX_MAX_SE 4 108 #define AMDGPU_GFX_MAX_SH_PER_SE 2 109 110 struct amdgpu_rb_config { 111 uint32_t rb_backend_disable; 112 uint32_t user_rb_backend_disable; 113 uint32_t raster_config; 114 uint32_t raster_config_1; 115 }; 116 117 struct gb_addr_config { 118 uint16_t pipe_interleave_size; 119 uint8_t num_pipes; 120 uint8_t max_compress_frags; 121 uint8_t num_banks; 122 uint8_t num_se; 123 uint8_t num_rb_per_se; 124 }; 125 126 struct amdgpu_gfx_config { 127 unsigned max_shader_engines; 128 unsigned max_tile_pipes; 129 unsigned max_cu_per_sh; 130 unsigned max_sh_per_se; 131 unsigned max_backends_per_se; 132 unsigned max_texture_channel_caches; 133 unsigned max_gprs; 134 unsigned max_gs_threads; 135 unsigned max_hw_contexts; 136 unsigned sc_prim_fifo_size_frontend; 137 unsigned sc_prim_fifo_size_backend; 138 unsigned sc_hiz_tile_fifo_size; 139 unsigned sc_earlyz_tile_fifo_size; 140 141 unsigned num_tile_pipes; 142 unsigned backend_enable_mask; 143 unsigned mem_max_burst_length_bytes; 144 unsigned mem_row_size_in_kb; 145 unsigned shader_engine_tile_size; 146 unsigned num_gpus; 147 unsigned multi_gpu_tile_size; 148 unsigned mc_arb_ramcfg; 149 unsigned gb_addr_config; 150 unsigned num_rbs; 151 unsigned gs_vgt_table_depth; 152 unsigned gs_prim_buffer_depth; 153 154 uint32_t tile_mode_array[32]; 155 uint32_t macrotile_mode_array[16]; 156 157 struct gb_addr_config gb_addr_config_fields; 158 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 159 160 /* gfx configure feature */ 161 uint32_t double_offchip_lds_buf; 162 /* cached value of DB_DEBUG2 */ 163 uint32_t db_debug2; 164 /* gfx10 specific config */ 165 uint32_t num_sc_per_sh; 166 uint32_t num_packer_per_sc; 167 uint32_t pa_sc_tile_steering_override; 168 uint64_t tcc_disabled_mask; 169 }; 170 171 struct amdgpu_cu_info { 172 uint32_t simd_per_cu; 173 uint32_t max_waves_per_simd; 174 uint32_t wave_front_size; 175 uint32_t max_scratch_slots_per_cu; 176 uint32_t lds_size; 177 178 /* total active CU number */ 179 uint32_t number; 180 uint32_t ao_cu_mask; 181 uint32_t ao_cu_bitmap[4][4]; 182 uint32_t bitmap[4][4]; 183 }; 184 185 struct amdgpu_gfx_funcs { 186 /* get the gpu clock counter */ 187 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 188 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 189 u32 sh_num, u32 instance); 190 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 191 uint32_t wave, uint32_t *dst, int *no_fields); 192 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 193 uint32_t wave, uint32_t thread, uint32_t start, 194 uint32_t size, uint32_t *dst); 195 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 196 uint32_t wave, uint32_t start, uint32_t size, 197 uint32_t *dst); 198 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 199 u32 queue, u32 vmid); 200 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 201 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); 202 }; 203 204 struct amdgpu_ngg_buf { 205 struct amdgpu_bo *bo; 206 uint64_t gpu_addr; 207 uint32_t size; 208 uint32_t bo_size; 209 }; 210 211 enum { 212 NGG_PRIM = 0, 213 NGG_POS, 214 NGG_CNTL, 215 NGG_PARAM, 216 NGG_BUF_MAX 217 }; 218 219 struct amdgpu_ngg { 220 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 221 uint32_t gds_reserve_addr; 222 uint32_t gds_reserve_size; 223 bool init; 224 }; 225 226 struct sq_work { 227 struct work_struct work; 228 unsigned ih_data; 229 }; 230 231 struct amdgpu_pfp { 232 struct amdgpu_bo *pfp_fw_obj; 233 uint64_t pfp_fw_gpu_addr; 234 uint32_t *pfp_fw_ptr; 235 }; 236 237 struct amdgpu_ce { 238 struct amdgpu_bo *ce_fw_obj; 239 uint64_t ce_fw_gpu_addr; 240 uint32_t *ce_fw_ptr; 241 }; 242 243 struct amdgpu_me { 244 struct amdgpu_bo *me_fw_obj; 245 uint64_t me_fw_gpu_addr; 246 uint32_t *me_fw_ptr; 247 uint32_t num_me; 248 uint32_t num_pipe_per_me; 249 uint32_t num_queue_per_pipe; 250 void *mqd_backup[AMDGPU_MAX_GFX_RINGS + 1]; 251 252 /* These are the resources for which amdgpu takes ownership */ 253 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 254 }; 255 256 struct amdgpu_gfx { 257 struct mutex gpu_clock_mutex; 258 struct amdgpu_gfx_config config; 259 struct amdgpu_rlc rlc; 260 struct amdgpu_pfp pfp; 261 struct amdgpu_ce ce; 262 struct amdgpu_me me; 263 struct amdgpu_mec mec; 264 struct amdgpu_kiq kiq; 265 struct amdgpu_scratch scratch; 266 const struct firmware *me_fw; /* ME firmware */ 267 uint32_t me_fw_version; 268 const struct firmware *pfp_fw; /* PFP firmware */ 269 uint32_t pfp_fw_version; 270 const struct firmware *ce_fw; /* CE firmware */ 271 uint32_t ce_fw_version; 272 const struct firmware *rlc_fw; /* RLC firmware */ 273 uint32_t rlc_fw_version; 274 const struct firmware *mec_fw; /* MEC firmware */ 275 uint32_t mec_fw_version; 276 const struct firmware *mec2_fw; /* MEC2 firmware */ 277 uint32_t mec2_fw_version; 278 uint32_t me_feature_version; 279 uint32_t ce_feature_version; 280 uint32_t pfp_feature_version; 281 uint32_t rlc_feature_version; 282 uint32_t rlc_srlc_fw_version; 283 uint32_t rlc_srlc_feature_version; 284 uint32_t rlc_srlg_fw_version; 285 uint32_t rlc_srlg_feature_version; 286 uint32_t rlc_srls_fw_version; 287 uint32_t rlc_srls_feature_version; 288 uint32_t mec_feature_version; 289 uint32_t mec2_feature_version; 290 bool mec_fw_write_wait; 291 bool me_fw_write_wait; 292 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 293 unsigned num_gfx_rings; 294 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 295 unsigned num_compute_rings; 296 struct amdgpu_irq_src eop_irq; 297 struct amdgpu_irq_src priv_reg_irq; 298 struct amdgpu_irq_src priv_inst_irq; 299 struct amdgpu_irq_src cp_ecc_error_irq; 300 struct amdgpu_irq_src sq_irq; 301 struct sq_work sq_work; 302 303 /* gfx status */ 304 uint32_t gfx_current_status; 305 /* ce ram size*/ 306 unsigned ce_ram_size; 307 struct amdgpu_cu_info cu_info; 308 const struct amdgpu_gfx_funcs *funcs; 309 310 /* reset mask */ 311 uint32_t grbm_soft_reset; 312 uint32_t srbm_soft_reset; 313 314 /* NGG */ 315 struct amdgpu_ngg ngg; 316 317 /* gfx off */ 318 bool gfx_off_state; /* true: enabled, false: disabled */ 319 struct mutex gfx_off_mutex; 320 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 321 struct delayed_work gfx_off_delay_work; 322 323 /* pipe reservation */ 324 struct mutex pipe_reserve_mutex; 325 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 326 327 /*ras */ 328 struct ras_common_if *ras_if; 329 }; 330 331 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 332 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 333 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 334 335 /** 336 * amdgpu_gfx_create_bitmask - create a bitmask 337 * 338 * @bit_width: length of the mask 339 * 340 * create a variable length bit mask. 341 * Returns the bitmask. 342 */ 343 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 344 { 345 return (u32)((1ULL << bit_width) - 1); 346 } 347 348 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 349 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 350 351 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 352 unsigned max_sh); 353 354 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 355 struct amdgpu_ring *ring, 356 struct amdgpu_irq_src *irq); 357 358 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, 359 struct amdgpu_irq_src *irq); 360 361 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 362 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 363 unsigned hpd_size); 364 365 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 366 unsigned mqd_size); 367 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 368 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 369 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 370 371 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 372 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 373 374 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 375 int pipe, int queue); 376 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 377 int *mec, int *pipe, int *queue); 378 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 379 int pipe, int queue); 380 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 381 int pipe, int queue); 382 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 383 int *me, int *pipe, int *queue); 384 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 385 int pipe, int queue); 386 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 387 388 #endif 389