1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 #include "amdgpu_ring_mux.h" 37 38 /* GFX current status */ 39 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 40 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 41 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 42 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 43 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 44 45 #define AMDGPU_MAX_GC_INSTANCES 8 46 47 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 48 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 49 50 enum amdgpu_gfx_pipe_priority { 51 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 52 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 53 }; 54 55 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 56 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 57 58 enum amdgpu_gfx_partition { 59 AMDGPU_SPX_PARTITION_MODE = 0, 60 AMDGPU_DPX_PARTITION_MODE = 1, 61 AMDGPU_TPX_PARTITION_MODE = 2, 62 AMDGPU_QPX_PARTITION_MODE = 3, 63 AMDGPU_CPX_PARTITION_MODE = 4, 64 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE = -1, 65 }; 66 67 #define NUM_XCC(x) hweight16(x) 68 69 enum amdgpu_pkg_type { 70 AMDGPU_PKG_TYPE_APU = 2, 71 AMDGPU_PKG_TYPE_UNKNOWN, 72 }; 73 74 enum amdgpu_memory_partition { 75 UNKNOWN_MEMORY_PARTITION_MODE = 0, 76 AMDGPU_NPS1_PARTITION_MODE = 1, 77 AMDGPU_NPS2_PARTITION_MODE = 2, 78 AMDGPU_NPS4_PARTITION_MODE = 3, 79 AMDGPU_NPS8_PARTITION_MODE = 4, 80 }; 81 82 struct amdgpu_mec { 83 struct amdgpu_bo *hpd_eop_obj; 84 u64 hpd_eop_gpu_addr; 85 struct amdgpu_bo *mec_fw_obj; 86 u64 mec_fw_gpu_addr; 87 struct amdgpu_bo *mec_fw_data_obj; 88 u64 mec_fw_data_gpu_addr; 89 90 u32 num_mec; 91 u32 num_pipe_per_mec; 92 u32 num_queue_per_pipe; 93 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 94 }; 95 96 struct amdgpu_mec_bitmap { 97 /* These are the resources for which amdgpu takes ownership */ 98 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 99 }; 100 101 enum amdgpu_unmap_queues_action { 102 PREEMPT_QUEUES = 0, 103 RESET_QUEUES, 104 DISABLE_PROCESS_QUEUES, 105 PREEMPT_QUEUES_NO_UNMAP, 106 }; 107 108 struct kiq_pm4_funcs { 109 /* Support ASIC-specific kiq pm4 packets*/ 110 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 111 uint64_t queue_mask); 112 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 113 struct amdgpu_ring *ring); 114 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 115 struct amdgpu_ring *ring, 116 enum amdgpu_unmap_queues_action action, 117 u64 gpu_addr, u64 seq); 118 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 119 struct amdgpu_ring *ring, 120 u64 addr, 121 u64 seq); 122 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 123 uint16_t pasid, uint32_t flush_type, 124 bool all_hub); 125 /* Packet sizes */ 126 int set_resources_size; 127 int map_queues_size; 128 int unmap_queues_size; 129 int query_status_size; 130 int invalidate_tlbs_size; 131 }; 132 133 struct amdgpu_kiq { 134 u64 eop_gpu_addr; 135 struct amdgpu_bo *eop_obj; 136 spinlock_t ring_lock; 137 struct amdgpu_ring ring; 138 struct amdgpu_irq_src irq; 139 const struct kiq_pm4_funcs *pmf; 140 void *mqd_backup; 141 }; 142 143 /* 144 * GFX configurations 145 */ 146 #define AMDGPU_GFX_MAX_SE 4 147 #define AMDGPU_GFX_MAX_SH_PER_SE 2 148 149 struct amdgpu_rb_config { 150 uint32_t rb_backend_disable; 151 uint32_t user_rb_backend_disable; 152 uint32_t raster_config; 153 uint32_t raster_config_1; 154 }; 155 156 struct gb_addr_config { 157 uint16_t pipe_interleave_size; 158 uint8_t num_pipes; 159 uint8_t max_compress_frags; 160 uint8_t num_banks; 161 uint8_t num_se; 162 uint8_t num_rb_per_se; 163 uint8_t num_pkrs; 164 }; 165 166 struct amdgpu_gfx_config { 167 unsigned max_shader_engines; 168 unsigned max_tile_pipes; 169 unsigned max_cu_per_sh; 170 unsigned max_sh_per_se; 171 unsigned max_backends_per_se; 172 unsigned max_texture_channel_caches; 173 unsigned max_gprs; 174 unsigned max_gs_threads; 175 unsigned max_hw_contexts; 176 unsigned sc_prim_fifo_size_frontend; 177 unsigned sc_prim_fifo_size_backend; 178 unsigned sc_hiz_tile_fifo_size; 179 unsigned sc_earlyz_tile_fifo_size; 180 181 unsigned num_tile_pipes; 182 unsigned backend_enable_mask; 183 unsigned mem_max_burst_length_bytes; 184 unsigned mem_row_size_in_kb; 185 unsigned shader_engine_tile_size; 186 unsigned num_gpus; 187 unsigned multi_gpu_tile_size; 188 unsigned mc_arb_ramcfg; 189 unsigned num_banks; 190 unsigned num_ranks; 191 unsigned gb_addr_config; 192 unsigned num_rbs; 193 unsigned gs_vgt_table_depth; 194 unsigned gs_prim_buffer_depth; 195 196 uint32_t tile_mode_array[32]; 197 uint32_t macrotile_mode_array[16]; 198 199 struct gb_addr_config gb_addr_config_fields; 200 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 201 202 /* gfx configure feature */ 203 uint32_t double_offchip_lds_buf; 204 /* cached value of DB_DEBUG2 */ 205 uint32_t db_debug2; 206 /* gfx10 specific config */ 207 uint32_t num_sc_per_sh; 208 uint32_t num_packer_per_sc; 209 uint32_t pa_sc_tile_steering_override; 210 /* Whether texture coordinate truncation is conformant. */ 211 bool ta_cntl2_truncate_coord_mode; 212 uint64_t tcc_disabled_mask; 213 uint32_t gc_num_tcp_per_sa; 214 uint32_t gc_num_sdp_interface; 215 uint32_t gc_num_tcps; 216 uint32_t gc_num_tcp_per_wpg; 217 uint32_t gc_tcp_l1_size; 218 uint32_t gc_num_sqc_per_wgp; 219 uint32_t gc_l1_instruction_cache_size_per_sqc; 220 uint32_t gc_l1_data_cache_size_per_sqc; 221 uint32_t gc_gl1c_per_sa; 222 uint32_t gc_gl1c_size_per_instance; 223 uint32_t gc_gl2c_per_gpu; 224 }; 225 226 struct amdgpu_cu_info { 227 uint32_t simd_per_cu; 228 uint32_t max_waves_per_simd; 229 uint32_t wave_front_size; 230 uint32_t max_scratch_slots_per_cu; 231 uint32_t lds_size; 232 233 /* total active CU number */ 234 uint32_t number; 235 uint32_t ao_cu_mask; 236 uint32_t ao_cu_bitmap[4][4]; 237 uint32_t bitmap[4][4]; 238 }; 239 240 struct amdgpu_gfx_ras { 241 struct amdgpu_ras_block_object ras_block; 242 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 243 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev); 244 int (*rlc_gc_fed_irq)(struct amdgpu_device *adev, 245 struct amdgpu_irq_src *source, 246 struct amdgpu_iv_entry *entry); 247 int (*poison_consumption_handler)(struct amdgpu_device *adev, 248 struct amdgpu_iv_entry *entry); 249 }; 250 251 struct amdgpu_gfx_shadow_info { 252 u32 shadow_size; 253 u32 shadow_alignment; 254 u32 csa_size; 255 u32 csa_alignment; 256 }; 257 258 struct amdgpu_gfx_funcs { 259 /* get the gpu clock counter */ 260 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 261 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 262 u32 sh_num, u32 instance, int xcc_id); 263 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 264 uint32_t wave, uint32_t *dst, int *no_fields); 265 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 266 uint32_t wave, uint32_t thread, uint32_t start, 267 uint32_t size, uint32_t *dst); 268 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 269 uint32_t wave, uint32_t start, uint32_t size, 270 uint32_t *dst); 271 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 272 u32 queue, u32 vmid, u32 xcc_id); 273 void (*init_spm_golden)(struct amdgpu_device *adev); 274 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 275 int (*get_gfx_shadow_info)(struct amdgpu_device *adev, 276 struct amdgpu_gfx_shadow_info *shadow_info); 277 enum amdgpu_gfx_partition 278 (*query_partition_mode)(struct amdgpu_device *adev); 279 enum amdgpu_memory_partition 280 (*query_mem_partition_mode)(struct amdgpu_device *adev); 281 int (*switch_partition_mode)(struct amdgpu_device *adev, 282 int num_xccs_per_xcp); 283 int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); 284 }; 285 286 struct sq_work { 287 struct work_struct work; 288 unsigned ih_data; 289 }; 290 291 struct amdgpu_pfp { 292 struct amdgpu_bo *pfp_fw_obj; 293 uint64_t pfp_fw_gpu_addr; 294 uint32_t *pfp_fw_ptr; 295 296 struct amdgpu_bo *pfp_fw_data_obj; 297 uint64_t pfp_fw_data_gpu_addr; 298 uint32_t *pfp_fw_data_ptr; 299 }; 300 301 struct amdgpu_ce { 302 struct amdgpu_bo *ce_fw_obj; 303 uint64_t ce_fw_gpu_addr; 304 uint32_t *ce_fw_ptr; 305 }; 306 307 struct amdgpu_me { 308 struct amdgpu_bo *me_fw_obj; 309 uint64_t me_fw_gpu_addr; 310 uint32_t *me_fw_ptr; 311 312 struct amdgpu_bo *me_fw_data_obj; 313 uint64_t me_fw_data_gpu_addr; 314 uint32_t *me_fw_data_ptr; 315 316 uint32_t num_me; 317 uint32_t num_pipe_per_me; 318 uint32_t num_queue_per_pipe; 319 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 320 321 /* These are the resources for which amdgpu takes ownership */ 322 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 323 }; 324 325 struct amdgpu_gfx { 326 struct mutex gpu_clock_mutex; 327 struct amdgpu_gfx_config config; 328 struct amdgpu_rlc rlc; 329 struct amdgpu_pfp pfp; 330 struct amdgpu_ce ce; 331 struct amdgpu_me me; 332 struct amdgpu_mec mec; 333 struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; 334 struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; 335 struct amdgpu_imu imu; 336 bool rs64_enable; /* firmware format */ 337 const struct firmware *me_fw; /* ME firmware */ 338 uint32_t me_fw_version; 339 const struct firmware *pfp_fw; /* PFP firmware */ 340 uint32_t pfp_fw_version; 341 const struct firmware *ce_fw; /* CE firmware */ 342 uint32_t ce_fw_version; 343 const struct firmware *rlc_fw; /* RLC firmware */ 344 uint32_t rlc_fw_version; 345 const struct firmware *mec_fw; /* MEC firmware */ 346 uint32_t mec_fw_version; 347 const struct firmware *mec2_fw; /* MEC2 firmware */ 348 uint32_t mec2_fw_version; 349 const struct firmware *imu_fw; /* IMU firmware */ 350 uint32_t imu_fw_version; 351 uint32_t me_feature_version; 352 uint32_t ce_feature_version; 353 uint32_t pfp_feature_version; 354 uint32_t rlc_feature_version; 355 uint32_t rlc_srlc_fw_version; 356 uint32_t rlc_srlc_feature_version; 357 uint32_t rlc_srlg_fw_version; 358 uint32_t rlc_srlg_feature_version; 359 uint32_t rlc_srls_fw_version; 360 uint32_t rlc_srls_feature_version; 361 uint32_t rlcp_ucode_version; 362 uint32_t rlcp_ucode_feature_version; 363 uint32_t rlcv_ucode_version; 364 uint32_t rlcv_ucode_feature_version; 365 uint32_t mec_feature_version; 366 uint32_t mec2_feature_version; 367 bool mec_fw_write_wait; 368 bool me_fw_write_wait; 369 bool cp_fw_write_wait; 370 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 371 unsigned num_gfx_rings; 372 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES]; 373 unsigned num_compute_rings; 374 struct amdgpu_irq_src eop_irq; 375 struct amdgpu_irq_src priv_reg_irq; 376 struct amdgpu_irq_src priv_inst_irq; 377 struct amdgpu_irq_src cp_ecc_error_irq; 378 struct amdgpu_irq_src sq_irq; 379 struct amdgpu_irq_src rlc_gc_fed_irq; 380 struct sq_work sq_work; 381 382 /* gfx status */ 383 uint32_t gfx_current_status; 384 /* ce ram size*/ 385 unsigned ce_ram_size; 386 struct amdgpu_cu_info cu_info; 387 const struct amdgpu_gfx_funcs *funcs; 388 389 /* reset mask */ 390 uint32_t grbm_soft_reset; 391 uint32_t srbm_soft_reset; 392 393 /* gfx off */ 394 bool gfx_off_state; /* true: enabled, false: disabled */ 395 struct mutex gfx_off_mutex; /* mutex to change gfxoff state */ 396 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 397 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */ 398 uint32_t gfx_off_residency; /* last logged residency */ 399 uint64_t gfx_off_entrycount; /* count of times GPU has get into GFXOFF state */ 400 401 /* pipe reservation */ 402 struct mutex pipe_reserve_mutex; 403 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 404 405 /*ras */ 406 struct ras_common_if *ras_if; 407 struct amdgpu_gfx_ras *ras; 408 409 bool is_poweron; 410 411 struct amdgpu_ring sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS]; 412 struct amdgpu_ring_mux muxer; 413 414 bool cp_gfx_shadow; /* for gfx11 */ 415 416 uint16_t xcc_mask; 417 enum amdgpu_memory_partition mem_partition_mode; 418 uint32_t num_xcc_per_xcp; 419 struct mutex partition_mutex; 420 }; 421 422 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 423 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 424 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id))) 425 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 426 #define amdgpu_gfx_get_gfx_shadow_info(adev, si) ((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si))) 427 428 /** 429 * amdgpu_gfx_create_bitmask - create a bitmask 430 * 431 * @bit_width: length of the mask 432 * 433 * create a variable length bit mask. 434 * Returns the bitmask. 435 */ 436 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 437 { 438 return (u32)((1ULL << bit_width) - 1); 439 } 440 441 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 442 unsigned max_sh); 443 444 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 445 struct amdgpu_ring *ring, 446 struct amdgpu_irq_src *irq, int xcc_id); 447 448 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 449 450 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id); 451 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 452 unsigned hpd_size, int xcc_id); 453 454 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 455 unsigned mqd_size, int xcc_id); 456 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 457 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 458 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 459 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); 460 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id); 461 462 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 463 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 464 465 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 466 int pipe, int queue); 467 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 468 int *mec, int *pipe, int *queue); 469 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int xcc_id, 470 int mec, int pipe, int queue); 471 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 472 struct amdgpu_ring *ring); 473 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 474 struct amdgpu_ring *ring); 475 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 476 int pipe, int queue); 477 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 478 int *me, int *pipe, int *queue); 479 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 480 int pipe, int queue); 481 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 482 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 483 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 484 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 485 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value); 486 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *residency); 487 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value); 488 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 489 void *err_data, 490 struct amdgpu_iv_entry *entry); 491 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 492 struct amdgpu_irq_src *source, 493 struct amdgpu_iv_entry *entry); 494 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 495 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 496 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 497 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); 498 499 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev); 500 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 501 struct amdgpu_iv_entry *entry); 502 503 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id); 504 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev); 505 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev); 506 #endif 507