1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __AMDGPU_GFX_H__
25 #define __AMDGPU_GFX_H__
26 
27 /*
28  * GFX stuff
29  */
30 #include "clearstate_defs.h"
31 #include "amdgpu_ring.h"
32 #include "amdgpu_rlc.h"
33 #include "soc15.h"
34 
35 /* GFX current status */
36 #define AMDGPU_GFX_NORMAL_MODE			0x00000000L
37 #define AMDGPU_GFX_SAFE_MODE			0x00000001L
38 #define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
39 #define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
40 #define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L
41 
42 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
43 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
44 
45 enum gfx_pipe_priority {
46 	AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,
47 	AMDGPU_GFX_PIPE_PRIO_HIGH,
48 	AMDGPU_GFX_PIPE_PRIO_MAX
49 };
50 
51 /* Argument for PPSMC_MSG_GpuChangeState */
52 enum gfx_change_state {
53 	sGpuChangeState_D0Entry = 1,
54 	sGpuChangeState_D3Entry,
55 };
56 
57 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
58 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
59 
60 struct amdgpu_mec {
61 	struct amdgpu_bo	*hpd_eop_obj;
62 	u64			hpd_eop_gpu_addr;
63 	struct amdgpu_bo	*mec_fw_obj;
64 	u64			mec_fw_gpu_addr;
65 	u32 num_mec;
66 	u32 num_pipe_per_mec;
67 	u32 num_queue_per_pipe;
68 	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
69 
70 	/* These are the resources for which amdgpu takes ownership */
71 	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
72 };
73 
74 enum amdgpu_unmap_queues_action {
75 	PREEMPT_QUEUES = 0,
76 	RESET_QUEUES,
77 	DISABLE_PROCESS_QUEUES,
78 	PREEMPT_QUEUES_NO_UNMAP,
79 };
80 
81 struct kiq_pm4_funcs {
82 	/* Support ASIC-specific kiq pm4 packets*/
83 	void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
84 					uint64_t queue_mask);
85 	void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
86 					struct amdgpu_ring *ring);
87 	void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
88 				 struct amdgpu_ring *ring,
89 				 enum amdgpu_unmap_queues_action action,
90 				 u64 gpu_addr, u64 seq);
91 	void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
92 					struct amdgpu_ring *ring,
93 					u64 addr,
94 					u64 seq);
95 	void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
96 				uint16_t pasid, uint32_t flush_type,
97 				bool all_hub);
98 	/* Packet sizes */
99 	int set_resources_size;
100 	int map_queues_size;
101 	int unmap_queues_size;
102 	int query_status_size;
103 	int invalidate_tlbs_size;
104 };
105 
106 struct amdgpu_kiq {
107 	u64			eop_gpu_addr;
108 	struct amdgpu_bo	*eop_obj;
109 	spinlock_t              ring_lock;
110 	struct amdgpu_ring	ring;
111 	struct amdgpu_irq_src	irq;
112 	const struct kiq_pm4_funcs *pmf;
113 };
114 
115 /*
116  * GPU scratch registers structures, functions & helpers
117  */
118 struct amdgpu_scratch {
119 	unsigned		num_reg;
120 	uint32_t                reg_base;
121 	uint32_t		free_mask;
122 };
123 
124 /*
125  * GFX configurations
126  */
127 #define AMDGPU_GFX_MAX_SE 4
128 #define AMDGPU_GFX_MAX_SH_PER_SE 2
129 
130 struct amdgpu_rb_config {
131 	uint32_t rb_backend_disable;
132 	uint32_t user_rb_backend_disable;
133 	uint32_t raster_config;
134 	uint32_t raster_config_1;
135 };
136 
137 struct gb_addr_config {
138 	uint16_t pipe_interleave_size;
139 	uint8_t num_pipes;
140 	uint8_t max_compress_frags;
141 	uint8_t num_banks;
142 	uint8_t num_se;
143 	uint8_t num_rb_per_se;
144 	uint8_t num_pkrs;
145 };
146 
147 struct amdgpu_gfx_config {
148 	unsigned max_shader_engines;
149 	unsigned max_tile_pipes;
150 	unsigned max_cu_per_sh;
151 	unsigned max_sh_per_se;
152 	unsigned max_backends_per_se;
153 	unsigned max_texture_channel_caches;
154 	unsigned max_gprs;
155 	unsigned max_gs_threads;
156 	unsigned max_hw_contexts;
157 	unsigned sc_prim_fifo_size_frontend;
158 	unsigned sc_prim_fifo_size_backend;
159 	unsigned sc_hiz_tile_fifo_size;
160 	unsigned sc_earlyz_tile_fifo_size;
161 
162 	unsigned num_tile_pipes;
163 	unsigned backend_enable_mask;
164 	unsigned mem_max_burst_length_bytes;
165 	unsigned mem_row_size_in_kb;
166 	unsigned shader_engine_tile_size;
167 	unsigned num_gpus;
168 	unsigned multi_gpu_tile_size;
169 	unsigned mc_arb_ramcfg;
170 	unsigned num_banks;
171 	unsigned num_ranks;
172 	unsigned gb_addr_config;
173 	unsigned num_rbs;
174 	unsigned gs_vgt_table_depth;
175 	unsigned gs_prim_buffer_depth;
176 
177 	uint32_t tile_mode_array[32];
178 	uint32_t macrotile_mode_array[16];
179 
180 	struct gb_addr_config gb_addr_config_fields;
181 	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
182 
183 	/* gfx configure feature */
184 	uint32_t double_offchip_lds_buf;
185 	/* cached value of DB_DEBUG2 */
186 	uint32_t db_debug2;
187 	/* gfx10 specific config */
188 	uint32_t num_sc_per_sh;
189 	uint32_t num_packer_per_sc;
190 	uint32_t pa_sc_tile_steering_override;
191 	uint64_t tcc_disabled_mask;
192 };
193 
194 struct amdgpu_cu_info {
195 	uint32_t simd_per_cu;
196 	uint32_t max_waves_per_simd;
197 	uint32_t wave_front_size;
198 	uint32_t max_scratch_slots_per_cu;
199 	uint32_t lds_size;
200 
201 	/* total active CU number */
202 	uint32_t number;
203 	uint32_t ao_cu_mask;
204 	uint32_t ao_cu_bitmap[4][4];
205 	uint32_t bitmap[4][4];
206 };
207 
208 struct amdgpu_gfx_ras_funcs {
209 	int (*ras_late_init)(struct amdgpu_device *adev);
210 	void (*ras_fini)(struct amdgpu_device *adev);
211 	int (*ras_error_inject)(struct amdgpu_device *adev,
212 				void *inject_if);
213 	int (*query_ras_error_count)(struct amdgpu_device *adev,
214 				     void *ras_error_status);
215 	void (*reset_ras_error_count)(struct amdgpu_device *adev);
216 	void (*query_ras_error_status)(struct amdgpu_device *adev);
217 	void (*reset_ras_error_status)(struct amdgpu_device *adev);
218 	void (*enable_watchdog_timer)(struct amdgpu_device *adev);
219 };
220 
221 struct amdgpu_gfx_funcs {
222 	/* get the gpu clock counter */
223 	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
224 	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
225 			     u32 sh_num, u32 instance);
226 	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
227 			       uint32_t wave, uint32_t *dst, int *no_fields);
228 	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
229 				uint32_t wave, uint32_t thread, uint32_t start,
230 				uint32_t size, uint32_t *dst);
231 	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
232 				uint32_t wave, uint32_t start, uint32_t size,
233 				uint32_t *dst);
234 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
235 				 u32 queue, u32 vmid);
236 	void (*init_spm_golden)(struct amdgpu_device *adev);
237 	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
238 };
239 
240 struct sq_work {
241 	struct work_struct	work;
242 	unsigned ih_data;
243 };
244 
245 struct amdgpu_pfp {
246 	struct amdgpu_bo		*pfp_fw_obj;
247 	uint64_t			pfp_fw_gpu_addr;
248 	uint32_t			*pfp_fw_ptr;
249 };
250 
251 struct amdgpu_ce {
252 	struct amdgpu_bo		*ce_fw_obj;
253 	uint64_t			ce_fw_gpu_addr;
254 	uint32_t			*ce_fw_ptr;
255 };
256 
257 struct amdgpu_me {
258 	struct amdgpu_bo		*me_fw_obj;
259 	uint64_t			me_fw_gpu_addr;
260 	uint32_t			*me_fw_ptr;
261 	uint32_t			num_me;
262 	uint32_t			num_pipe_per_me;
263 	uint32_t			num_queue_per_pipe;
264 	void				*mqd_backup[AMDGPU_MAX_GFX_RINGS];
265 
266 	/* These are the resources for which amdgpu takes ownership */
267 	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
268 };
269 
270 struct amdgpu_gfx {
271 	struct mutex			gpu_clock_mutex;
272 	struct amdgpu_gfx_config	config;
273 	struct amdgpu_rlc		rlc;
274 	struct amdgpu_pfp		pfp;
275 	struct amdgpu_ce		ce;
276 	struct amdgpu_me		me;
277 	struct amdgpu_mec		mec;
278 	struct amdgpu_kiq		kiq;
279 	struct amdgpu_scratch		scratch;
280 	const struct firmware		*me_fw;	/* ME firmware */
281 	uint32_t			me_fw_version;
282 	const struct firmware		*pfp_fw; /* PFP firmware */
283 	uint32_t			pfp_fw_version;
284 	const struct firmware		*ce_fw;	/* CE firmware */
285 	uint32_t			ce_fw_version;
286 	const struct firmware		*rlc_fw; /* RLC firmware */
287 	uint32_t			rlc_fw_version;
288 	const struct firmware		*mec_fw; /* MEC firmware */
289 	uint32_t			mec_fw_version;
290 	const struct firmware		*mec2_fw; /* MEC2 firmware */
291 	uint32_t			mec2_fw_version;
292 	uint32_t			me_feature_version;
293 	uint32_t			ce_feature_version;
294 	uint32_t			pfp_feature_version;
295 	uint32_t			rlc_feature_version;
296 	uint32_t			rlc_srlc_fw_version;
297 	uint32_t			rlc_srlc_feature_version;
298 	uint32_t			rlc_srlg_fw_version;
299 	uint32_t			rlc_srlg_feature_version;
300 	uint32_t			rlc_srls_fw_version;
301 	uint32_t			rlc_srls_feature_version;
302 	uint32_t			mec_feature_version;
303 	uint32_t			mec2_feature_version;
304 	bool				mec_fw_write_wait;
305 	bool				me_fw_write_wait;
306 	bool				cp_fw_write_wait;
307 	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
308 	unsigned			num_gfx_rings;
309 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
310 	unsigned			num_compute_rings;
311 	struct amdgpu_irq_src		eop_irq;
312 	struct amdgpu_irq_src		priv_reg_irq;
313 	struct amdgpu_irq_src		priv_inst_irq;
314 	struct amdgpu_irq_src		cp_ecc_error_irq;
315 	struct amdgpu_irq_src		sq_irq;
316 	struct sq_work			sq_work;
317 
318 	/* gfx status */
319 	uint32_t			gfx_current_status;
320 	/* ce ram size*/
321 	unsigned			ce_ram_size;
322 	struct amdgpu_cu_info		cu_info;
323 	const struct amdgpu_gfx_funcs	*funcs;
324 
325 	/* reset mask */
326 	uint32_t                        grbm_soft_reset;
327 	uint32_t                        srbm_soft_reset;
328 
329 	/* gfx off */
330 	bool                            gfx_off_state; /* true: enabled, false: disabled */
331 	struct mutex                    gfx_off_mutex;
332 	uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
333 	struct delayed_work             gfx_off_delay_work;
334 
335 	/* pipe reservation */
336 	struct mutex			pipe_reserve_mutex;
337 	DECLARE_BITMAP			(pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
338 
339 	/*ras */
340 	struct ras_common_if			*ras_if;
341 	const struct amdgpu_gfx_ras_funcs	*ras_funcs;
342 };
343 
344 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
345 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
346 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
347 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
348 
349 /**
350  * amdgpu_gfx_create_bitmask - create a bitmask
351  *
352  * @bit_width: length of the mask
353  *
354  * create a variable length bit mask.
355  * Returns the bitmask.
356  */
357 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
358 {
359 	return (u32)((1ULL << bit_width) - 1);
360 }
361 
362 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
363 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
364 
365 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
366 				 unsigned max_sh);
367 
368 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
369 			     struct amdgpu_ring *ring,
370 			     struct amdgpu_irq_src *irq);
371 
372 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
373 
374 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
375 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
376 			unsigned hpd_size);
377 
378 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
379 			   unsigned mqd_size);
380 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
381 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
382 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
383 
384 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
385 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
386 
387 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
388 				int pipe, int queue);
389 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
390 				 int *mec, int *pipe, int *queue);
391 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
392 				     int pipe, int queue);
393 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
394 					       struct amdgpu_ring *ring);
395 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
396 			       int pipe, int queue);
397 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
398 				int *me, int *pipe, int *queue);
399 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
400 				    int pipe, int queue);
401 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
402 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
403 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
404 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
405 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
406 		void *err_data,
407 		struct amdgpu_iv_entry *entry);
408 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
409 				  struct amdgpu_irq_src *source,
410 				  struct amdgpu_iv_entry *entry);
411 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
412 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
413 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
414 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
415 #endif
416