1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 #include "amdgpu_imu.h" 34 #include "soc15.h" 35 #include "amdgpu_ras.h" 36 37 /* GFX current status */ 38 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 39 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 40 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 41 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 42 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 43 44 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 45 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 46 47 enum amdgpu_gfx_pipe_priority { 48 AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1, 49 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2 50 }; 51 52 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 53 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 54 55 struct amdgpu_mec { 56 struct amdgpu_bo *hpd_eop_obj; 57 u64 hpd_eop_gpu_addr; 58 struct amdgpu_bo *mec_fw_obj; 59 u64 mec_fw_gpu_addr; 60 struct amdgpu_bo *mec_fw_data_obj; 61 u64 mec_fw_data_gpu_addr; 62 63 u32 num_mec; 64 u32 num_pipe_per_mec; 65 u32 num_queue_per_pipe; 66 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 67 68 /* These are the resources for which amdgpu takes ownership */ 69 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 70 }; 71 72 enum amdgpu_unmap_queues_action { 73 PREEMPT_QUEUES = 0, 74 RESET_QUEUES, 75 DISABLE_PROCESS_QUEUES, 76 PREEMPT_QUEUES_NO_UNMAP, 77 }; 78 79 struct kiq_pm4_funcs { 80 /* Support ASIC-specific kiq pm4 packets*/ 81 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 82 uint64_t queue_mask); 83 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 84 struct amdgpu_ring *ring); 85 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 86 struct amdgpu_ring *ring, 87 enum amdgpu_unmap_queues_action action, 88 u64 gpu_addr, u64 seq); 89 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 90 struct amdgpu_ring *ring, 91 u64 addr, 92 u64 seq); 93 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 94 uint16_t pasid, uint32_t flush_type, 95 bool all_hub); 96 /* Packet sizes */ 97 int set_resources_size; 98 int map_queues_size; 99 int unmap_queues_size; 100 int query_status_size; 101 int invalidate_tlbs_size; 102 }; 103 104 struct amdgpu_kiq { 105 u64 eop_gpu_addr; 106 struct amdgpu_bo *eop_obj; 107 spinlock_t ring_lock; 108 struct amdgpu_ring ring; 109 struct amdgpu_irq_src irq; 110 const struct kiq_pm4_funcs *pmf; 111 }; 112 113 /* 114 * GFX configurations 115 */ 116 #define AMDGPU_GFX_MAX_SE 4 117 #define AMDGPU_GFX_MAX_SH_PER_SE 2 118 119 struct amdgpu_rb_config { 120 uint32_t rb_backend_disable; 121 uint32_t user_rb_backend_disable; 122 uint32_t raster_config; 123 uint32_t raster_config_1; 124 }; 125 126 struct gb_addr_config { 127 uint16_t pipe_interleave_size; 128 uint8_t num_pipes; 129 uint8_t max_compress_frags; 130 uint8_t num_banks; 131 uint8_t num_se; 132 uint8_t num_rb_per_se; 133 uint8_t num_pkrs; 134 }; 135 136 struct amdgpu_gfx_config { 137 unsigned max_shader_engines; 138 unsigned max_tile_pipes; 139 unsigned max_cu_per_sh; 140 unsigned max_sh_per_se; 141 unsigned max_backends_per_se; 142 unsigned max_texture_channel_caches; 143 unsigned max_gprs; 144 unsigned max_gs_threads; 145 unsigned max_hw_contexts; 146 unsigned sc_prim_fifo_size_frontend; 147 unsigned sc_prim_fifo_size_backend; 148 unsigned sc_hiz_tile_fifo_size; 149 unsigned sc_earlyz_tile_fifo_size; 150 151 unsigned num_tile_pipes; 152 unsigned backend_enable_mask; 153 unsigned mem_max_burst_length_bytes; 154 unsigned mem_row_size_in_kb; 155 unsigned shader_engine_tile_size; 156 unsigned num_gpus; 157 unsigned multi_gpu_tile_size; 158 unsigned mc_arb_ramcfg; 159 unsigned num_banks; 160 unsigned num_ranks; 161 unsigned gb_addr_config; 162 unsigned num_rbs; 163 unsigned gs_vgt_table_depth; 164 unsigned gs_prim_buffer_depth; 165 166 uint32_t tile_mode_array[32]; 167 uint32_t macrotile_mode_array[16]; 168 169 struct gb_addr_config gb_addr_config_fields; 170 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 171 172 /* gfx configure feature */ 173 uint32_t double_offchip_lds_buf; 174 /* cached value of DB_DEBUG2 */ 175 uint32_t db_debug2; 176 /* gfx10 specific config */ 177 uint32_t num_sc_per_sh; 178 uint32_t num_packer_per_sc; 179 uint32_t pa_sc_tile_steering_override; 180 uint64_t tcc_disabled_mask; 181 uint32_t gc_num_tcp_per_sa; 182 uint32_t gc_num_sdp_interface; 183 uint32_t gc_num_tcps; 184 uint32_t gc_num_tcp_per_wpg; 185 uint32_t gc_tcp_l1_size; 186 uint32_t gc_num_sqc_per_wgp; 187 uint32_t gc_l1_instruction_cache_size_per_sqc; 188 uint32_t gc_l1_data_cache_size_per_sqc; 189 uint32_t gc_gl1c_per_sa; 190 uint32_t gc_gl1c_size_per_instance; 191 uint32_t gc_gl2c_per_gpu; 192 }; 193 194 struct amdgpu_cu_info { 195 uint32_t simd_per_cu; 196 uint32_t max_waves_per_simd; 197 uint32_t wave_front_size; 198 uint32_t max_scratch_slots_per_cu; 199 uint32_t lds_size; 200 201 /* total active CU number */ 202 uint32_t number; 203 uint32_t ao_cu_mask; 204 uint32_t ao_cu_bitmap[4][4]; 205 uint32_t bitmap[4][4]; 206 }; 207 208 struct amdgpu_gfx_ras { 209 struct amdgpu_ras_block_object ras_block; 210 void (*enable_watchdog_timer)(struct amdgpu_device *adev); 211 bool (*query_utcl2_poison_status)(struct amdgpu_device *adev); 212 }; 213 214 struct amdgpu_gfx_funcs { 215 /* get the gpu clock counter */ 216 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 217 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 218 u32 sh_num, u32 instance); 219 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 220 uint32_t wave, uint32_t *dst, int *no_fields); 221 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 222 uint32_t wave, uint32_t thread, uint32_t start, 223 uint32_t size, uint32_t *dst); 224 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 225 uint32_t wave, uint32_t start, uint32_t size, 226 uint32_t *dst); 227 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 228 u32 queue, u32 vmid); 229 void (*init_spm_golden)(struct amdgpu_device *adev); 230 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 231 }; 232 233 struct sq_work { 234 struct work_struct work; 235 unsigned ih_data; 236 }; 237 238 struct amdgpu_pfp { 239 struct amdgpu_bo *pfp_fw_obj; 240 uint64_t pfp_fw_gpu_addr; 241 uint32_t *pfp_fw_ptr; 242 243 struct amdgpu_bo *pfp_fw_data_obj; 244 uint64_t pfp_fw_data_gpu_addr; 245 uint32_t *pfp_fw_data_ptr; 246 }; 247 248 struct amdgpu_ce { 249 struct amdgpu_bo *ce_fw_obj; 250 uint64_t ce_fw_gpu_addr; 251 uint32_t *ce_fw_ptr; 252 }; 253 254 struct amdgpu_me { 255 struct amdgpu_bo *me_fw_obj; 256 uint64_t me_fw_gpu_addr; 257 uint32_t *me_fw_ptr; 258 259 struct amdgpu_bo *me_fw_data_obj; 260 uint64_t me_fw_data_gpu_addr; 261 uint32_t *me_fw_data_ptr; 262 263 uint32_t num_me; 264 uint32_t num_pipe_per_me; 265 uint32_t num_queue_per_pipe; 266 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 267 268 /* These are the resources for which amdgpu takes ownership */ 269 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 270 }; 271 272 struct amdgpu_gfx { 273 struct mutex gpu_clock_mutex; 274 struct amdgpu_gfx_config config; 275 struct amdgpu_rlc rlc; 276 struct amdgpu_pfp pfp; 277 struct amdgpu_ce ce; 278 struct amdgpu_me me; 279 struct amdgpu_mec mec; 280 struct amdgpu_kiq kiq; 281 struct amdgpu_imu imu; 282 bool rs64_enable; /* firmware format */ 283 const struct firmware *me_fw; /* ME firmware */ 284 uint32_t me_fw_version; 285 const struct firmware *pfp_fw; /* PFP firmware */ 286 uint32_t pfp_fw_version; 287 const struct firmware *ce_fw; /* CE firmware */ 288 uint32_t ce_fw_version; 289 const struct firmware *rlc_fw; /* RLC firmware */ 290 uint32_t rlc_fw_version; 291 const struct firmware *mec_fw; /* MEC firmware */ 292 uint32_t mec_fw_version; 293 const struct firmware *mec2_fw; /* MEC2 firmware */ 294 uint32_t mec2_fw_version; 295 const struct firmware *imu_fw; /* IMU firmware */ 296 uint32_t imu_fw_version; 297 uint32_t me_feature_version; 298 uint32_t ce_feature_version; 299 uint32_t pfp_feature_version; 300 uint32_t rlc_feature_version; 301 uint32_t rlc_srlc_fw_version; 302 uint32_t rlc_srlc_feature_version; 303 uint32_t rlc_srlg_fw_version; 304 uint32_t rlc_srlg_feature_version; 305 uint32_t rlc_srls_fw_version; 306 uint32_t rlc_srls_feature_version; 307 uint32_t mec_feature_version; 308 uint32_t mec2_feature_version; 309 bool mec_fw_write_wait; 310 bool me_fw_write_wait; 311 bool cp_fw_write_wait; 312 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 313 unsigned num_gfx_rings; 314 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 315 unsigned num_compute_rings; 316 struct amdgpu_irq_src eop_irq; 317 struct amdgpu_irq_src priv_reg_irq; 318 struct amdgpu_irq_src priv_inst_irq; 319 struct amdgpu_irq_src cp_ecc_error_irq; 320 struct amdgpu_irq_src sq_irq; 321 struct sq_work sq_work; 322 323 /* gfx status */ 324 uint32_t gfx_current_status; 325 /* ce ram size*/ 326 unsigned ce_ram_size; 327 struct amdgpu_cu_info cu_info; 328 const struct amdgpu_gfx_funcs *funcs; 329 330 /* reset mask */ 331 uint32_t grbm_soft_reset; 332 uint32_t srbm_soft_reset; 333 334 /* gfx off */ 335 bool gfx_off_state; /* true: enabled, false: disabled */ 336 struct mutex gfx_off_mutex; 337 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 338 struct delayed_work gfx_off_delay_work; 339 340 /* pipe reservation */ 341 struct mutex pipe_reserve_mutex; 342 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 343 344 /*ras */ 345 struct ras_common_if *ras_if; 346 struct amdgpu_gfx_ras *ras; 347 348 bool is_poweron; 349 }; 350 351 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 352 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 353 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 354 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 355 356 /** 357 * amdgpu_gfx_create_bitmask - create a bitmask 358 * 359 * @bit_width: length of the mask 360 * 361 * create a variable length bit mask. 362 * Returns the bitmask. 363 */ 364 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 365 { 366 return (u32)((1ULL << bit_width) - 1); 367 } 368 369 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 370 unsigned max_sh); 371 372 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 373 struct amdgpu_ring *ring, 374 struct amdgpu_irq_src *irq); 375 376 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 377 378 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 379 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 380 unsigned hpd_size); 381 382 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 383 unsigned mqd_size); 384 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 385 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 386 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 387 388 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 389 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 390 391 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 392 int pipe, int queue); 393 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 394 int *mec, int *pipe, int *queue); 395 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 396 int pipe, int queue); 397 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 398 struct amdgpu_ring *ring); 399 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 400 struct amdgpu_ring *ring); 401 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 402 int pipe, int queue); 403 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 404 int *me, int *pipe, int *queue); 405 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 406 int pipe, int queue); 407 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 408 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 409 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block); 410 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 411 void *err_data, 412 struct amdgpu_iv_entry *entry); 413 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 414 struct amdgpu_irq_src *source, 415 struct amdgpu_iv_entry *entry); 416 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 417 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 418 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 419 #endif 420