1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 34 /* GFX current status */ 35 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 36 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 37 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 38 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 39 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 40 41 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 42 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 43 44 enum gfx_pipe_priority { 45 AMDGPU_GFX_PIPE_PRIO_NORMAL = 1, 46 AMDGPU_GFX_PIPE_PRIO_HIGH, 47 AMDGPU_GFX_PIPE_PRIO_MAX 48 }; 49 50 /* Argument for PPSMC_MSG_GpuChangeState */ 51 enum gfx_change_state { 52 sGpuChangeState_D0Entry = 1, 53 sGpuChangeState_D3Entry, 54 }; 55 56 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0 57 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15 58 59 struct amdgpu_mec { 60 struct amdgpu_bo *hpd_eop_obj; 61 u64 hpd_eop_gpu_addr; 62 struct amdgpu_bo *mec_fw_obj; 63 u64 mec_fw_gpu_addr; 64 u32 num_mec; 65 u32 num_pipe_per_mec; 66 u32 num_queue_per_pipe; 67 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 68 69 /* These are the resources for which amdgpu takes ownership */ 70 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 71 }; 72 73 enum amdgpu_unmap_queues_action { 74 PREEMPT_QUEUES = 0, 75 RESET_QUEUES, 76 DISABLE_PROCESS_QUEUES, 77 PREEMPT_QUEUES_NO_UNMAP, 78 }; 79 80 struct kiq_pm4_funcs { 81 /* Support ASIC-specific kiq pm4 packets*/ 82 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 83 uint64_t queue_mask); 84 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 85 struct amdgpu_ring *ring); 86 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 87 struct amdgpu_ring *ring, 88 enum amdgpu_unmap_queues_action action, 89 u64 gpu_addr, u64 seq); 90 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 91 struct amdgpu_ring *ring, 92 u64 addr, 93 u64 seq); 94 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 95 uint16_t pasid, uint32_t flush_type, 96 bool all_hub); 97 /* Packet sizes */ 98 int set_resources_size; 99 int map_queues_size; 100 int unmap_queues_size; 101 int query_status_size; 102 int invalidate_tlbs_size; 103 }; 104 105 struct amdgpu_kiq { 106 u64 eop_gpu_addr; 107 struct amdgpu_bo *eop_obj; 108 spinlock_t ring_lock; 109 struct amdgpu_ring ring; 110 struct amdgpu_irq_src irq; 111 const struct kiq_pm4_funcs *pmf; 112 }; 113 114 /* 115 * GPU scratch registers structures, functions & helpers 116 */ 117 struct amdgpu_scratch { 118 unsigned num_reg; 119 uint32_t reg_base; 120 uint32_t free_mask; 121 }; 122 123 /* 124 * GFX configurations 125 */ 126 #define AMDGPU_GFX_MAX_SE 4 127 #define AMDGPU_GFX_MAX_SH_PER_SE 2 128 129 struct amdgpu_rb_config { 130 uint32_t rb_backend_disable; 131 uint32_t user_rb_backend_disable; 132 uint32_t raster_config; 133 uint32_t raster_config_1; 134 }; 135 136 struct gb_addr_config { 137 uint16_t pipe_interleave_size; 138 uint8_t num_pipes; 139 uint8_t max_compress_frags; 140 uint8_t num_banks; 141 uint8_t num_se; 142 uint8_t num_rb_per_se; 143 uint8_t num_pkrs; 144 }; 145 146 struct amdgpu_gfx_config { 147 unsigned max_shader_engines; 148 unsigned max_tile_pipes; 149 unsigned max_cu_per_sh; 150 unsigned max_sh_per_se; 151 unsigned max_backends_per_se; 152 unsigned max_texture_channel_caches; 153 unsigned max_gprs; 154 unsigned max_gs_threads; 155 unsigned max_hw_contexts; 156 unsigned sc_prim_fifo_size_frontend; 157 unsigned sc_prim_fifo_size_backend; 158 unsigned sc_hiz_tile_fifo_size; 159 unsigned sc_earlyz_tile_fifo_size; 160 161 unsigned num_tile_pipes; 162 unsigned backend_enable_mask; 163 unsigned mem_max_burst_length_bytes; 164 unsigned mem_row_size_in_kb; 165 unsigned shader_engine_tile_size; 166 unsigned num_gpus; 167 unsigned multi_gpu_tile_size; 168 unsigned mc_arb_ramcfg; 169 unsigned num_banks; 170 unsigned num_ranks; 171 unsigned gb_addr_config; 172 unsigned num_rbs; 173 unsigned gs_vgt_table_depth; 174 unsigned gs_prim_buffer_depth; 175 176 uint32_t tile_mode_array[32]; 177 uint32_t macrotile_mode_array[16]; 178 179 struct gb_addr_config gb_addr_config_fields; 180 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 181 182 /* gfx configure feature */ 183 uint32_t double_offchip_lds_buf; 184 /* cached value of DB_DEBUG2 */ 185 uint32_t db_debug2; 186 /* gfx10 specific config */ 187 uint32_t num_sc_per_sh; 188 uint32_t num_packer_per_sc; 189 uint32_t pa_sc_tile_steering_override; 190 uint64_t tcc_disabled_mask; 191 }; 192 193 struct amdgpu_cu_info { 194 uint32_t simd_per_cu; 195 uint32_t max_waves_per_simd; 196 uint32_t wave_front_size; 197 uint32_t max_scratch_slots_per_cu; 198 uint32_t lds_size; 199 200 /* total active CU number */ 201 uint32_t number; 202 uint32_t ao_cu_mask; 203 uint32_t ao_cu_bitmap[4][4]; 204 uint32_t bitmap[4][4]; 205 }; 206 207 struct amdgpu_gfx_funcs { 208 /* get the gpu clock counter */ 209 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 210 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 211 u32 sh_num, u32 instance); 212 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 213 uint32_t wave, uint32_t *dst, int *no_fields); 214 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 215 uint32_t wave, uint32_t thread, uint32_t start, 216 uint32_t size, uint32_t *dst); 217 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 218 uint32_t wave, uint32_t start, uint32_t size, 219 uint32_t *dst); 220 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 221 u32 queue, u32 vmid); 222 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 223 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); 224 void (*reset_ras_error_count) (struct amdgpu_device *adev); 225 void (*init_spm_golden)(struct amdgpu_device *adev); 226 void (*query_ras_error_status) (struct amdgpu_device *adev); 227 void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable); 228 }; 229 230 struct sq_work { 231 struct work_struct work; 232 unsigned ih_data; 233 }; 234 235 struct amdgpu_pfp { 236 struct amdgpu_bo *pfp_fw_obj; 237 uint64_t pfp_fw_gpu_addr; 238 uint32_t *pfp_fw_ptr; 239 }; 240 241 struct amdgpu_ce { 242 struct amdgpu_bo *ce_fw_obj; 243 uint64_t ce_fw_gpu_addr; 244 uint32_t *ce_fw_ptr; 245 }; 246 247 struct amdgpu_me { 248 struct amdgpu_bo *me_fw_obj; 249 uint64_t me_fw_gpu_addr; 250 uint32_t *me_fw_ptr; 251 uint32_t num_me; 252 uint32_t num_pipe_per_me; 253 uint32_t num_queue_per_pipe; 254 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 255 256 /* These are the resources for which amdgpu takes ownership */ 257 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 258 }; 259 260 struct amdgpu_gfx { 261 struct mutex gpu_clock_mutex; 262 struct amdgpu_gfx_config config; 263 struct amdgpu_rlc rlc; 264 struct amdgpu_pfp pfp; 265 struct amdgpu_ce ce; 266 struct amdgpu_me me; 267 struct amdgpu_mec mec; 268 struct amdgpu_kiq kiq; 269 struct amdgpu_scratch scratch; 270 const struct firmware *me_fw; /* ME firmware */ 271 uint32_t me_fw_version; 272 const struct firmware *pfp_fw; /* PFP firmware */ 273 uint32_t pfp_fw_version; 274 const struct firmware *ce_fw; /* CE firmware */ 275 uint32_t ce_fw_version; 276 const struct firmware *rlc_fw; /* RLC firmware */ 277 uint32_t rlc_fw_version; 278 const struct firmware *mec_fw; /* MEC firmware */ 279 uint32_t mec_fw_version; 280 const struct firmware *mec2_fw; /* MEC2 firmware */ 281 uint32_t mec2_fw_version; 282 uint32_t me_feature_version; 283 uint32_t ce_feature_version; 284 uint32_t pfp_feature_version; 285 uint32_t rlc_feature_version; 286 uint32_t rlc_srlc_fw_version; 287 uint32_t rlc_srlc_feature_version; 288 uint32_t rlc_srlg_fw_version; 289 uint32_t rlc_srlg_feature_version; 290 uint32_t rlc_srls_fw_version; 291 uint32_t rlc_srls_feature_version; 292 uint32_t mec_feature_version; 293 uint32_t mec2_feature_version; 294 bool mec_fw_write_wait; 295 bool me_fw_write_wait; 296 bool cp_fw_write_wait; 297 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 298 unsigned num_gfx_rings; 299 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 300 unsigned num_compute_rings; 301 struct amdgpu_irq_src eop_irq; 302 struct amdgpu_irq_src priv_reg_irq; 303 struct amdgpu_irq_src priv_inst_irq; 304 struct amdgpu_irq_src cp_ecc_error_irq; 305 struct amdgpu_irq_src sq_irq; 306 struct sq_work sq_work; 307 308 /* gfx status */ 309 uint32_t gfx_current_status; 310 /* ce ram size*/ 311 unsigned ce_ram_size; 312 struct amdgpu_cu_info cu_info; 313 const struct amdgpu_gfx_funcs *funcs; 314 315 /* reset mask */ 316 uint32_t grbm_soft_reset; 317 uint32_t srbm_soft_reset; 318 319 /* gfx off */ 320 bool gfx_off_state; /* true: enabled, false: disabled */ 321 struct mutex gfx_off_mutex; 322 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 323 struct delayed_work gfx_off_delay_work; 324 325 /* pipe reservation */ 326 struct mutex pipe_reserve_mutex; 327 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 328 329 /*ras */ 330 struct ras_common_if *ras_if; 331 }; 332 333 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 334 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 335 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 336 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 337 338 /** 339 * amdgpu_gfx_create_bitmask - create a bitmask 340 * 341 * @bit_width: length of the mask 342 * 343 * create a variable length bit mask. 344 * Returns the bitmask. 345 */ 346 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 347 { 348 return (u32)((1ULL << bit_width) - 1); 349 } 350 351 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 352 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 353 354 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 355 unsigned max_sh); 356 357 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 358 struct amdgpu_ring *ring, 359 struct amdgpu_irq_src *irq); 360 361 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 362 363 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 364 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 365 unsigned hpd_size); 366 367 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 368 unsigned mqd_size); 369 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 370 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 371 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 372 373 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 374 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 375 376 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 377 int pipe, int queue); 378 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 379 int *mec, int *pipe, int *queue); 380 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 381 int pipe, int queue); 382 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 383 struct amdgpu_ring *ring); 384 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 385 int pipe, int queue); 386 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 387 int *me, int *pipe, int *queue); 388 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 389 int pipe, int queue); 390 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 391 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value); 392 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev); 393 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 394 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 395 void *err_data, 396 struct amdgpu_iv_entry *entry); 397 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 398 struct amdgpu_irq_src *source, 399 struct amdgpu_iv_entry *entry); 400 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 401 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 402 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); 403 void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state); 404 #endif 405