1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 34 /* GFX current status */ 35 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 36 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 37 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 38 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 39 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 40 41 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES 42 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 43 44 struct amdgpu_mec { 45 struct amdgpu_bo *hpd_eop_obj; 46 u64 hpd_eop_gpu_addr; 47 struct amdgpu_bo *mec_fw_obj; 48 u64 mec_fw_gpu_addr; 49 u32 num_mec; 50 u32 num_pipe_per_mec; 51 u32 num_queue_per_pipe; 52 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 53 54 /* These are the resources for which amdgpu takes ownership */ 55 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 56 }; 57 58 enum amdgpu_unmap_queues_action { 59 PREEMPT_QUEUES = 0, 60 RESET_QUEUES, 61 DISABLE_PROCESS_QUEUES, 62 PREEMPT_QUEUES_NO_UNMAP, 63 }; 64 65 struct kiq_pm4_funcs { 66 /* Support ASIC-specific kiq pm4 packets*/ 67 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring, 68 uint64_t queue_mask); 69 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring, 70 struct amdgpu_ring *ring); 71 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring, 72 struct amdgpu_ring *ring, 73 enum amdgpu_unmap_queues_action action, 74 u64 gpu_addr, u64 seq); 75 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring, 76 struct amdgpu_ring *ring, 77 u64 addr, 78 u64 seq); 79 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, 80 uint16_t pasid, uint32_t flush_type, 81 bool all_hub); 82 /* Packet sizes */ 83 int set_resources_size; 84 int map_queues_size; 85 int unmap_queues_size; 86 int query_status_size; 87 int invalidate_tlbs_size; 88 }; 89 90 struct amdgpu_kiq { 91 u64 eop_gpu_addr; 92 struct amdgpu_bo *eop_obj; 93 spinlock_t ring_lock; 94 struct amdgpu_ring ring; 95 struct amdgpu_irq_src irq; 96 const struct kiq_pm4_funcs *pmf; 97 uint32_t reg_val_offs; 98 }; 99 100 /* 101 * GPU scratch registers structures, functions & helpers 102 */ 103 struct amdgpu_scratch { 104 unsigned num_reg; 105 uint32_t reg_base; 106 uint32_t free_mask; 107 }; 108 109 /* 110 * GFX configurations 111 */ 112 #define AMDGPU_GFX_MAX_SE 4 113 #define AMDGPU_GFX_MAX_SH_PER_SE 2 114 115 struct amdgpu_rb_config { 116 uint32_t rb_backend_disable; 117 uint32_t user_rb_backend_disable; 118 uint32_t raster_config; 119 uint32_t raster_config_1; 120 }; 121 122 struct gb_addr_config { 123 uint16_t pipe_interleave_size; 124 uint8_t num_pipes; 125 uint8_t max_compress_frags; 126 uint8_t num_banks; 127 uint8_t num_se; 128 uint8_t num_rb_per_se; 129 }; 130 131 struct amdgpu_gfx_config { 132 unsigned max_shader_engines; 133 unsigned max_tile_pipes; 134 unsigned max_cu_per_sh; 135 unsigned max_sh_per_se; 136 unsigned max_backends_per_se; 137 unsigned max_texture_channel_caches; 138 unsigned max_gprs; 139 unsigned max_gs_threads; 140 unsigned max_hw_contexts; 141 unsigned sc_prim_fifo_size_frontend; 142 unsigned sc_prim_fifo_size_backend; 143 unsigned sc_hiz_tile_fifo_size; 144 unsigned sc_earlyz_tile_fifo_size; 145 146 unsigned num_tile_pipes; 147 unsigned backend_enable_mask; 148 unsigned mem_max_burst_length_bytes; 149 unsigned mem_row_size_in_kb; 150 unsigned shader_engine_tile_size; 151 unsigned num_gpus; 152 unsigned multi_gpu_tile_size; 153 unsigned mc_arb_ramcfg; 154 unsigned num_banks; 155 unsigned num_ranks; 156 unsigned gb_addr_config; 157 unsigned num_rbs; 158 unsigned gs_vgt_table_depth; 159 unsigned gs_prim_buffer_depth; 160 161 uint32_t tile_mode_array[32]; 162 uint32_t macrotile_mode_array[16]; 163 164 struct gb_addr_config gb_addr_config_fields; 165 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 166 167 /* gfx configure feature */ 168 uint32_t double_offchip_lds_buf; 169 /* cached value of DB_DEBUG2 */ 170 uint32_t db_debug2; 171 /* gfx10 specific config */ 172 uint32_t num_sc_per_sh; 173 uint32_t num_packer_per_sc; 174 uint32_t pa_sc_tile_steering_override; 175 uint64_t tcc_disabled_mask; 176 }; 177 178 struct amdgpu_cu_info { 179 uint32_t simd_per_cu; 180 uint32_t max_waves_per_simd; 181 uint32_t wave_front_size; 182 uint32_t max_scratch_slots_per_cu; 183 uint32_t lds_size; 184 185 /* total active CU number */ 186 uint32_t number; 187 uint32_t ao_cu_mask; 188 uint32_t ao_cu_bitmap[4][4]; 189 uint32_t bitmap[4][4]; 190 }; 191 192 struct amdgpu_gfx_funcs { 193 /* get the gpu clock counter */ 194 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 195 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 196 u32 sh_num, u32 instance); 197 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 198 uint32_t wave, uint32_t *dst, int *no_fields); 199 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 200 uint32_t wave, uint32_t thread, uint32_t start, 201 uint32_t size, uint32_t *dst); 202 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 203 uint32_t wave, uint32_t start, uint32_t size, 204 uint32_t *dst); 205 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 206 u32 queue, u32 vmid); 207 int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if); 208 int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status); 209 void (*reset_ras_error_count) (struct amdgpu_device *adev); 210 }; 211 212 struct sq_work { 213 struct work_struct work; 214 unsigned ih_data; 215 }; 216 217 struct amdgpu_pfp { 218 struct amdgpu_bo *pfp_fw_obj; 219 uint64_t pfp_fw_gpu_addr; 220 uint32_t *pfp_fw_ptr; 221 }; 222 223 struct amdgpu_ce { 224 struct amdgpu_bo *ce_fw_obj; 225 uint64_t ce_fw_gpu_addr; 226 uint32_t *ce_fw_ptr; 227 }; 228 229 struct amdgpu_me { 230 struct amdgpu_bo *me_fw_obj; 231 uint64_t me_fw_gpu_addr; 232 uint32_t *me_fw_ptr; 233 uint32_t num_me; 234 uint32_t num_pipe_per_me; 235 uint32_t num_queue_per_pipe; 236 void *mqd_backup[AMDGPU_MAX_GFX_RINGS]; 237 238 /* These are the resources for which amdgpu takes ownership */ 239 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 240 }; 241 242 struct amdgpu_gfx { 243 struct mutex gpu_clock_mutex; 244 struct amdgpu_gfx_config config; 245 struct amdgpu_rlc rlc; 246 struct amdgpu_pfp pfp; 247 struct amdgpu_ce ce; 248 struct amdgpu_me me; 249 struct amdgpu_mec mec; 250 struct amdgpu_kiq kiq; 251 struct amdgpu_scratch scratch; 252 const struct firmware *me_fw; /* ME firmware */ 253 uint32_t me_fw_version; 254 const struct firmware *pfp_fw; /* PFP firmware */ 255 uint32_t pfp_fw_version; 256 const struct firmware *ce_fw; /* CE firmware */ 257 uint32_t ce_fw_version; 258 const struct firmware *rlc_fw; /* RLC firmware */ 259 uint32_t rlc_fw_version; 260 const struct firmware *mec_fw; /* MEC firmware */ 261 uint32_t mec_fw_version; 262 const struct firmware *mec2_fw; /* MEC2 firmware */ 263 uint32_t mec2_fw_version; 264 uint32_t me_feature_version; 265 uint32_t ce_feature_version; 266 uint32_t pfp_feature_version; 267 uint32_t rlc_feature_version; 268 uint32_t rlc_srlc_fw_version; 269 uint32_t rlc_srlc_feature_version; 270 uint32_t rlc_srlg_fw_version; 271 uint32_t rlc_srlg_feature_version; 272 uint32_t rlc_srls_fw_version; 273 uint32_t rlc_srls_feature_version; 274 uint32_t mec_feature_version; 275 uint32_t mec2_feature_version; 276 bool mec_fw_write_wait; 277 bool me_fw_write_wait; 278 bool cp_fw_write_wait; 279 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 280 struct drm_gpu_scheduler *gfx_sched[AMDGPU_MAX_GFX_RINGS]; 281 uint32_t num_gfx_sched; 282 unsigned num_gfx_rings; 283 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 284 struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS]; 285 uint32_t num_compute_sched; 286 unsigned num_compute_rings; 287 struct amdgpu_irq_src eop_irq; 288 struct amdgpu_irq_src priv_reg_irq; 289 struct amdgpu_irq_src priv_inst_irq; 290 struct amdgpu_irq_src cp_ecc_error_irq; 291 struct amdgpu_irq_src sq_irq; 292 struct sq_work sq_work; 293 294 /* gfx status */ 295 uint32_t gfx_current_status; 296 /* ce ram size*/ 297 unsigned ce_ram_size; 298 struct amdgpu_cu_info cu_info; 299 const struct amdgpu_gfx_funcs *funcs; 300 301 /* reset mask */ 302 uint32_t grbm_soft_reset; 303 uint32_t srbm_soft_reset; 304 305 /* gfx off */ 306 bool gfx_off_state; /* true: enabled, false: disabled */ 307 struct mutex gfx_off_mutex; 308 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 309 struct delayed_work gfx_off_delay_work; 310 311 /* pipe reservation */ 312 struct mutex pipe_reserve_mutex; 313 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 314 315 /*ras */ 316 struct ras_common_if *ras_if; 317 }; 318 319 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 320 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 321 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 322 323 /** 324 * amdgpu_gfx_create_bitmask - create a bitmask 325 * 326 * @bit_width: length of the mask 327 * 328 * create a variable length bit mask. 329 * Returns the bitmask. 330 */ 331 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 332 { 333 return (u32)((1ULL << bit_width) - 1); 334 } 335 336 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 337 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 338 339 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 340 unsigned max_sh); 341 342 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 343 struct amdgpu_ring *ring, 344 struct amdgpu_irq_src *irq); 345 346 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring); 347 348 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 349 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 350 unsigned hpd_size); 351 352 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 353 unsigned mqd_size); 354 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev); 355 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev); 356 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev); 357 358 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 359 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev); 360 361 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 362 int pipe, int queue); 363 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 364 int *mec, int *pipe, int *queue); 365 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 366 int pipe, int queue); 367 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, 368 int pipe, int queue); 369 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 370 int *me, int *pipe, int *queue); 371 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, 372 int pipe, int queue); 373 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 374 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev); 375 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); 376 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 377 void *err_data, 378 struct amdgpu_iv_entry *entry); 379 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 380 struct amdgpu_irq_src *source, 381 struct amdgpu_iv_entry *entry); 382 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 383 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 384 #endif 385