1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_GFX_H__ 25 #define __AMDGPU_GFX_H__ 26 27 /* 28 * GFX stuff 29 */ 30 #include "clearstate_defs.h" 31 #include "amdgpu_ring.h" 32 #include "amdgpu_rlc.h" 33 34 /* GFX current status */ 35 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 36 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 37 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 38 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 39 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 40 41 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 42 43 struct amdgpu_mec { 44 struct amdgpu_bo *hpd_eop_obj; 45 u64 hpd_eop_gpu_addr; 46 struct amdgpu_bo *mec_fw_obj; 47 u64 mec_fw_gpu_addr; 48 u32 num_mec; 49 u32 num_pipe_per_mec; 50 u32 num_queue_per_pipe; 51 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 52 53 /* These are the resources for which amdgpu takes ownership */ 54 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 55 }; 56 57 struct amdgpu_kiq { 58 u64 eop_gpu_addr; 59 struct amdgpu_bo *eop_obj; 60 spinlock_t ring_lock; 61 struct amdgpu_ring ring; 62 struct amdgpu_irq_src irq; 63 }; 64 65 /* 66 * GPU scratch registers structures, functions & helpers 67 */ 68 struct amdgpu_scratch { 69 unsigned num_reg; 70 uint32_t reg_base; 71 uint32_t free_mask; 72 }; 73 74 /* 75 * GFX configurations 76 */ 77 #define AMDGPU_GFX_MAX_SE 4 78 #define AMDGPU_GFX_MAX_SH_PER_SE 2 79 80 struct amdgpu_rb_config { 81 uint32_t rb_backend_disable; 82 uint32_t user_rb_backend_disable; 83 uint32_t raster_config; 84 uint32_t raster_config_1; 85 }; 86 87 struct gb_addr_config { 88 uint16_t pipe_interleave_size; 89 uint8_t num_pipes; 90 uint8_t max_compress_frags; 91 uint8_t num_banks; 92 uint8_t num_se; 93 uint8_t num_rb_per_se; 94 }; 95 96 struct amdgpu_gfx_config { 97 unsigned max_shader_engines; 98 unsigned max_tile_pipes; 99 unsigned max_cu_per_sh; 100 unsigned max_sh_per_se; 101 unsigned max_backends_per_se; 102 unsigned max_texture_channel_caches; 103 unsigned max_gprs; 104 unsigned max_gs_threads; 105 unsigned max_hw_contexts; 106 unsigned sc_prim_fifo_size_frontend; 107 unsigned sc_prim_fifo_size_backend; 108 unsigned sc_hiz_tile_fifo_size; 109 unsigned sc_earlyz_tile_fifo_size; 110 111 unsigned num_tile_pipes; 112 unsigned backend_enable_mask; 113 unsigned mem_max_burst_length_bytes; 114 unsigned mem_row_size_in_kb; 115 unsigned shader_engine_tile_size; 116 unsigned num_gpus; 117 unsigned multi_gpu_tile_size; 118 unsigned mc_arb_ramcfg; 119 unsigned gb_addr_config; 120 unsigned num_rbs; 121 unsigned gs_vgt_table_depth; 122 unsigned gs_prim_buffer_depth; 123 124 uint32_t tile_mode_array[32]; 125 uint32_t macrotile_mode_array[16]; 126 127 struct gb_addr_config gb_addr_config_fields; 128 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 129 130 /* gfx configure feature */ 131 uint32_t double_offchip_lds_buf; 132 /* cached value of DB_DEBUG2 */ 133 uint32_t db_debug2; 134 }; 135 136 struct amdgpu_cu_info { 137 uint32_t simd_per_cu; 138 uint32_t max_waves_per_simd; 139 uint32_t wave_front_size; 140 uint32_t max_scratch_slots_per_cu; 141 uint32_t lds_size; 142 143 /* total active CU number */ 144 uint32_t number; 145 uint32_t ao_cu_mask; 146 uint32_t ao_cu_bitmap[4][4]; 147 uint32_t bitmap[4][4]; 148 }; 149 150 struct amdgpu_gfx_funcs { 151 /* get the gpu clock counter */ 152 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 153 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 154 u32 sh_num, u32 instance); 155 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 156 uint32_t wave, uint32_t *dst, int *no_fields); 157 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, 158 uint32_t wave, uint32_t thread, uint32_t start, 159 uint32_t size, uint32_t *dst); 160 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, 161 uint32_t wave, uint32_t start, uint32_t size, 162 uint32_t *dst); 163 void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, 164 u32 queue); 165 }; 166 167 struct amdgpu_ngg_buf { 168 struct amdgpu_bo *bo; 169 uint64_t gpu_addr; 170 uint32_t size; 171 uint32_t bo_size; 172 }; 173 174 enum { 175 NGG_PRIM = 0, 176 NGG_POS, 177 NGG_CNTL, 178 NGG_PARAM, 179 NGG_BUF_MAX 180 }; 181 182 struct amdgpu_ngg { 183 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 184 uint32_t gds_reserve_addr; 185 uint32_t gds_reserve_size; 186 bool init; 187 }; 188 189 struct sq_work { 190 struct work_struct work; 191 unsigned ih_data; 192 }; 193 194 struct amdgpu_gfx { 195 struct mutex gpu_clock_mutex; 196 struct amdgpu_gfx_config config; 197 struct amdgpu_rlc rlc; 198 struct amdgpu_mec mec; 199 struct amdgpu_kiq kiq; 200 struct amdgpu_scratch scratch; 201 const struct firmware *me_fw; /* ME firmware */ 202 uint32_t me_fw_version; 203 const struct firmware *pfp_fw; /* PFP firmware */ 204 uint32_t pfp_fw_version; 205 const struct firmware *ce_fw; /* CE firmware */ 206 uint32_t ce_fw_version; 207 const struct firmware *rlc_fw; /* RLC firmware */ 208 uint32_t rlc_fw_version; 209 const struct firmware *mec_fw; /* MEC firmware */ 210 uint32_t mec_fw_version; 211 const struct firmware *mec2_fw; /* MEC2 firmware */ 212 uint32_t mec2_fw_version; 213 uint32_t me_feature_version; 214 uint32_t ce_feature_version; 215 uint32_t pfp_feature_version; 216 uint32_t rlc_feature_version; 217 uint32_t rlc_srlc_fw_version; 218 uint32_t rlc_srlc_feature_version; 219 uint32_t rlc_srlg_fw_version; 220 uint32_t rlc_srlg_feature_version; 221 uint32_t rlc_srls_fw_version; 222 uint32_t rlc_srls_feature_version; 223 uint32_t mec_feature_version; 224 uint32_t mec2_feature_version; 225 bool mec_fw_write_wait; 226 bool me_fw_write_wait; 227 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 228 unsigned num_gfx_rings; 229 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 230 unsigned num_compute_rings; 231 struct amdgpu_irq_src eop_irq; 232 struct amdgpu_irq_src priv_reg_irq; 233 struct amdgpu_irq_src priv_inst_irq; 234 struct amdgpu_irq_src cp_ecc_error_irq; 235 struct amdgpu_irq_src sq_irq; 236 struct sq_work sq_work; 237 238 /* gfx status */ 239 uint32_t gfx_current_status; 240 /* ce ram size*/ 241 unsigned ce_ram_size; 242 struct amdgpu_cu_info cu_info; 243 const struct amdgpu_gfx_funcs *funcs; 244 245 /* reset mask */ 246 uint32_t grbm_soft_reset; 247 uint32_t srbm_soft_reset; 248 249 /* NGG */ 250 struct amdgpu_ngg ngg; 251 252 /* gfx off */ 253 bool gfx_off_state; /* true: enabled, false: disabled */ 254 struct mutex gfx_off_mutex; 255 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ 256 struct delayed_work gfx_off_delay_work; 257 258 /* pipe reservation */ 259 struct mutex pipe_reserve_mutex; 260 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 261 }; 262 263 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 264 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 265 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) 266 267 /** 268 * amdgpu_gfx_create_bitmask - create a bitmask 269 * 270 * @bit_width: length of the mask 271 * 272 * create a variable length bit mask. 273 * Returns the bitmask. 274 */ 275 static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) 276 { 277 return (u32)((1ULL << bit_width) - 1); 278 } 279 280 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg); 281 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 282 283 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 284 unsigned max_sh); 285 286 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 287 struct amdgpu_ring *ring, 288 struct amdgpu_irq_src *irq); 289 290 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring, 291 struct amdgpu_irq_src *irq); 292 293 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev); 294 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 295 unsigned hpd_size); 296 297 int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev, 298 unsigned mqd_size); 299 void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev); 300 301 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev); 302 int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec, 303 int pipe, int queue); 304 void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit, 305 int *mec, int *pipe, int *queue); 306 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec, 307 int pipe, int queue); 308 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); 309 310 #endif 311