1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "amdgpu_rlc.h" 29 #include "amdgpu_ras.h" 30 31 /* delay 0.1 second to enable gfx off feature */ 32 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100) 33 34 /* 35 * GPU GFX IP block helpers function. 36 */ 37 38 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 39 int pipe, int queue) 40 { 41 int bit = 0; 42 43 bit += mec * adev->gfx.mec.num_pipe_per_mec 44 * adev->gfx.mec.num_queue_per_pipe; 45 bit += pipe * adev->gfx.mec.num_queue_per_pipe; 46 bit += queue; 47 48 return bit; 49 } 50 51 void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 52 int *mec, int *pipe, int *queue) 53 { 54 *queue = bit % adev->gfx.mec.num_queue_per_pipe; 55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) 56 % adev->gfx.mec.num_pipe_per_mec; 57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) 58 / adev->gfx.mec.num_pipe_per_mec; 59 60 } 61 62 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, 63 int mec, int pipe, int queue) 64 { 65 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue), 66 adev->gfx.mec.queue_bitmap); 67 } 68 69 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, 70 int me, int pipe, int queue) 71 { 72 int bit = 0; 73 74 bit += me * adev->gfx.me.num_pipe_per_me 75 * adev->gfx.me.num_queue_per_pipe; 76 bit += pipe * adev->gfx.me.num_queue_per_pipe; 77 bit += queue; 78 79 return bit; 80 } 81 82 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 83 int *me, int *pipe, int *queue) 84 { 85 *queue = bit % adev->gfx.me.num_queue_per_pipe; 86 *pipe = (bit / adev->gfx.me.num_queue_per_pipe) 87 % adev->gfx.me.num_pipe_per_me; 88 *me = (bit / adev->gfx.me.num_queue_per_pipe) 89 / adev->gfx.me.num_pipe_per_me; 90 } 91 92 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, 93 int me, int pipe, int queue) 94 { 95 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue), 96 adev->gfx.me.queue_bitmap); 97 } 98 99 /** 100 * amdgpu_gfx_scratch_get - Allocate a scratch register 101 * 102 * @adev: amdgpu_device pointer 103 * @reg: scratch register mmio offset 104 * 105 * Allocate a CP scratch register for use by the driver (all asics). 106 * Returns 0 on success or -EINVAL on failure. 107 */ 108 int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg) 109 { 110 int i; 111 112 i = ffs(adev->gfx.scratch.free_mask); 113 if (i != 0 && i <= adev->gfx.scratch.num_reg) { 114 i--; 115 adev->gfx.scratch.free_mask &= ~(1u << i); 116 *reg = adev->gfx.scratch.reg_base + i; 117 return 0; 118 } 119 return -EINVAL; 120 } 121 122 /** 123 * amdgpu_gfx_scratch_free - Free a scratch register 124 * 125 * @adev: amdgpu_device pointer 126 * @reg: scratch register mmio offset 127 * 128 * Free a CP scratch register allocated for use by the driver (all asics) 129 */ 130 void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg) 131 { 132 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); 133 } 134 135 /** 136 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter 137 * 138 * @mask: array in which the per-shader array disable masks will be stored 139 * @max_se: number of SEs 140 * @max_sh: number of SHs 141 * 142 * The bitmask of CUs to be disabled in the shader array determined by se and 143 * sh is stored in mask[se * max_sh + sh]. 144 */ 145 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh) 146 { 147 unsigned se, sh, cu; 148 const char *p; 149 150 memset(mask, 0, sizeof(*mask) * max_se * max_sh); 151 152 if (!amdgpu_disable_cu || !*amdgpu_disable_cu) 153 return; 154 155 p = amdgpu_disable_cu; 156 for (;;) { 157 char *next; 158 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu); 159 if (ret < 3) { 160 DRM_ERROR("amdgpu: could not parse disable_cu\n"); 161 return; 162 } 163 164 if (se < max_se && sh < max_sh && cu < 16) { 165 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu); 166 mask[se * max_sh + sh] |= 1u << cu; 167 } else { 168 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n", 169 se, sh, cu); 170 } 171 172 next = strchr(p, ','); 173 if (!next) 174 break; 175 p = next + 1; 176 } 177 } 178 179 static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev) 180 { 181 if (amdgpu_compute_multipipe != -1) { 182 DRM_INFO("amdgpu: forcing compute pipe policy %d\n", 183 amdgpu_compute_multipipe); 184 return amdgpu_compute_multipipe == 1; 185 } 186 187 /* FIXME: spreading the queues across pipes causes perf regressions 188 * on POLARIS11 compute workloads */ 189 if (adev->asic_type == CHIP_POLARIS11) 190 return false; 191 192 return adev->gfx.mec.num_mec > 1; 193 } 194 195 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) 196 { 197 int i, queue, pipe, mec; 198 bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev); 199 200 /* policy for amdgpu compute queue ownership */ 201 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 202 queue = i % adev->gfx.mec.num_queue_per_pipe; 203 pipe = (i / adev->gfx.mec.num_queue_per_pipe) 204 % adev->gfx.mec.num_pipe_per_mec; 205 mec = (i / adev->gfx.mec.num_queue_per_pipe) 206 / adev->gfx.mec.num_pipe_per_mec; 207 208 /* we've run out of HW */ 209 if (mec >= adev->gfx.mec.num_mec) 210 break; 211 212 if (multipipe_policy) { 213 /* policy: amdgpu owns the first two queues of the first MEC */ 214 if (mec == 0 && queue < 2) 215 set_bit(i, adev->gfx.mec.queue_bitmap); 216 } else { 217 /* policy: amdgpu owns all queues in the first pipe */ 218 if (mec == 0 && pipe == 0) 219 set_bit(i, adev->gfx.mec.queue_bitmap); 220 } 221 } 222 223 /* update the number of active compute rings */ 224 adev->gfx.num_compute_rings = 225 bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 226 227 /* If you hit this case and edited the policy, you probably just 228 * need to increase AMDGPU_MAX_COMPUTE_RINGS */ 229 if (WARN_ON(adev->gfx.num_compute_rings > AMDGPU_MAX_COMPUTE_RINGS)) 230 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 231 } 232 233 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) 234 { 235 int i, queue, me; 236 237 for (i = 0; i < AMDGPU_MAX_GFX_QUEUES; ++i) { 238 queue = i % adev->gfx.me.num_queue_per_pipe; 239 me = (i / adev->gfx.me.num_queue_per_pipe) 240 / adev->gfx.me.num_pipe_per_me; 241 242 if (me >= adev->gfx.me.num_me) 243 break; 244 /* policy: amdgpu owns the first queue per pipe at this stage 245 * will extend to mulitple queues per pipe later */ 246 if (me == 0 && queue < 1) 247 set_bit(i, adev->gfx.me.queue_bitmap); 248 } 249 250 /* update the number of active graphics rings */ 251 adev->gfx.num_gfx_rings = 252 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 253 } 254 255 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, 256 struct amdgpu_ring *ring) 257 { 258 int queue_bit; 259 int mec, pipe, queue; 260 261 queue_bit = adev->gfx.mec.num_mec 262 * adev->gfx.mec.num_pipe_per_mec 263 * adev->gfx.mec.num_queue_per_pipe; 264 265 while (queue_bit-- >= 0) { 266 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) 267 continue; 268 269 amdgpu_gfx_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); 270 271 /* 272 * 1. Using pipes 2/3 from MEC 2 seems cause problems. 273 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN 274 * only can be issued on queue 0. 275 */ 276 if ((mec == 1 && pipe > 1) || queue != 0) 277 continue; 278 279 ring->me = mec + 1; 280 ring->pipe = pipe; 281 ring->queue = queue; 282 283 return 0; 284 } 285 286 dev_err(adev->dev, "Failed to find a queue for KIQ\n"); 287 return -EINVAL; 288 } 289 290 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 291 struct amdgpu_ring *ring, 292 struct amdgpu_irq_src *irq) 293 { 294 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 295 int r = 0; 296 297 spin_lock_init(&kiq->ring_lock); 298 299 r = amdgpu_device_wb_get(adev, &adev->virt.reg_val_offs); 300 if (r) 301 return r; 302 303 ring->adev = NULL; 304 ring->ring_obj = NULL; 305 ring->use_doorbell = true; 306 ring->doorbell_index = adev->doorbell_index.kiq; 307 308 r = amdgpu_gfx_kiq_acquire(adev, ring); 309 if (r) 310 return r; 311 312 ring->eop_gpu_addr = kiq->eop_gpu_addr; 313 sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue); 314 r = amdgpu_ring_init(adev, ring, 1024, 315 irq, AMDGPU_CP_KIQ_IRQ_DRIVER0); 316 if (r) 317 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 318 319 return r; 320 } 321 322 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring) 323 { 324 amdgpu_device_wb_free(ring->adev, ring->adev->virt.reg_val_offs); 325 amdgpu_ring_fini(ring); 326 } 327 328 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) 329 { 330 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 331 332 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 333 } 334 335 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 336 unsigned hpd_size) 337 { 338 int r; 339 u32 *hpd; 340 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 341 342 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, 343 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 344 &kiq->eop_gpu_addr, (void **)&hpd); 345 if (r) { 346 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); 347 return r; 348 } 349 350 memset(hpd, 0, hpd_size); 351 352 r = amdgpu_bo_reserve(kiq->eop_obj, true); 353 if (unlikely(r != 0)) 354 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); 355 amdgpu_bo_kunmap(kiq->eop_obj); 356 amdgpu_bo_unreserve(kiq->eop_obj); 357 358 return 0; 359 } 360 361 /* create MQD for each compute/gfx queue */ 362 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 363 unsigned mqd_size) 364 { 365 struct amdgpu_ring *ring = NULL; 366 int r, i; 367 368 /* create MQD for KIQ */ 369 ring = &adev->gfx.kiq.ring; 370 if (!ring->mqd_obj) { 371 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must 372 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD 373 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for 374 * KIQ MQD no matter SRIOV or Bare-metal 375 */ 376 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 377 AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj, 378 &ring->mqd_gpu_addr, &ring->mqd_ptr); 379 if (r) { 380 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 381 return r; 382 } 383 384 /* prepare MQD backup */ 385 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL); 386 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) 387 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 388 } 389 390 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 391 /* create MQD for each KGQ */ 392 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 393 ring = &adev->gfx.gfx_ring[i]; 394 if (!ring->mqd_obj) { 395 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 396 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 397 &ring->mqd_gpu_addr, &ring->mqd_ptr); 398 if (r) { 399 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 400 return r; 401 } 402 403 /* prepare MQD backup */ 404 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); 405 if (!adev->gfx.me.mqd_backup[i]) 406 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 407 } 408 } 409 } 410 411 /* create MQD for each KCQ */ 412 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 413 ring = &adev->gfx.compute_ring[i]; 414 if (!ring->mqd_obj) { 415 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 416 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 417 &ring->mqd_gpu_addr, &ring->mqd_ptr); 418 if (r) { 419 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 420 return r; 421 } 422 423 /* prepare MQD backup */ 424 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); 425 if (!adev->gfx.mec.mqd_backup[i]) 426 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 427 } 428 } 429 430 return 0; 431 } 432 433 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev) 434 { 435 struct amdgpu_ring *ring = NULL; 436 int i; 437 438 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 439 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 440 ring = &adev->gfx.gfx_ring[i]; 441 kfree(adev->gfx.me.mqd_backup[i]); 442 amdgpu_bo_free_kernel(&ring->mqd_obj, 443 &ring->mqd_gpu_addr, 444 &ring->mqd_ptr); 445 } 446 } 447 448 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 449 ring = &adev->gfx.compute_ring[i]; 450 kfree(adev->gfx.mec.mqd_backup[i]); 451 amdgpu_bo_free_kernel(&ring->mqd_obj, 452 &ring->mqd_gpu_addr, 453 &ring->mqd_ptr); 454 } 455 456 ring = &adev->gfx.kiq.ring; 457 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); 458 amdgpu_bo_free_kernel(&ring->mqd_obj, 459 &ring->mqd_gpu_addr, 460 &ring->mqd_ptr); 461 } 462 463 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) 464 { 465 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 466 struct amdgpu_ring *kiq_ring = &kiq->ring; 467 int i; 468 469 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 470 return -EINVAL; 471 472 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 473 adev->gfx.num_compute_rings)) 474 return -ENOMEM; 475 476 for (i = 0; i < adev->gfx.num_compute_rings; i++) 477 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], 478 RESET_QUEUES, 0, 0); 479 480 return amdgpu_ring_test_ring(kiq_ring); 481 } 482 483 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) 484 { 485 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 486 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 487 uint64_t queue_mask = 0; 488 int r, i; 489 490 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources) 491 return -EINVAL; 492 493 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 494 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 495 continue; 496 497 /* This situation may be hit in the future if a new HW 498 * generation exposes more than 64 queues. If so, the 499 * definition of queue_mask needs updating */ 500 if (WARN_ON(i > (sizeof(queue_mask)*8))) { 501 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 502 break; 503 } 504 505 queue_mask |= (1ull << i); 506 } 507 508 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, 509 kiq_ring->queue); 510 511 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 512 adev->gfx.num_compute_rings + 513 kiq->pmf->set_resources_size); 514 if (r) { 515 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 516 return r; 517 } 518 519 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); 520 for (i = 0; i < adev->gfx.num_compute_rings; i++) 521 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); 522 523 r = amdgpu_ring_test_helper(kiq_ring); 524 if (r) 525 DRM_ERROR("KCQ enable failed\n"); 526 527 return r; 528 } 529 530 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable 531 * 532 * @adev: amdgpu_device pointer 533 * @bool enable true: enable gfx off feature, false: disable gfx off feature 534 * 535 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled. 536 * 2. other client can send request to disable gfx off feature, the request should be honored. 537 * 3. other client can cancel their request of disable gfx off feature 538 * 4. other client should not send request to enable gfx off feature before disable gfx off feature. 539 */ 540 541 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) 542 { 543 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 544 return; 545 546 if (!is_support_sw_smu(adev) && 547 (!adev->powerplay.pp_funcs || 548 !adev->powerplay.pp_funcs->set_powergating_by_smu)) 549 return; 550 551 552 mutex_lock(&adev->gfx.gfx_off_mutex); 553 554 if (!enable) 555 adev->gfx.gfx_off_req_count++; 556 else if (adev->gfx.gfx_off_req_count > 0) 557 adev->gfx.gfx_off_req_count--; 558 559 if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { 560 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE); 561 } else if (!enable && adev->gfx.gfx_off_state) { 562 if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) 563 adev->gfx.gfx_off_state = false; 564 } 565 566 mutex_unlock(&adev->gfx.gfx_off_mutex); 567 } 568 569 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) 570 { 571 int r; 572 struct ras_fs_if fs_info = { 573 .sysfs_name = "gfx_err_count", 574 .debugfs_name = "gfx_err_inject", 575 }; 576 struct ras_ih_if ih_info = { 577 .cb = amdgpu_gfx_process_ras_data_cb, 578 }; 579 580 if (!adev->gfx.ras_if) { 581 adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); 582 if (!adev->gfx.ras_if) 583 return -ENOMEM; 584 adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX; 585 adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 586 adev->gfx.ras_if->sub_block_index = 0; 587 strcpy(adev->gfx.ras_if->name, "gfx"); 588 } 589 fs_info.head = ih_info.head = *adev->gfx.ras_if; 590 591 r = amdgpu_ras_late_init(adev, adev->gfx.ras_if, 592 &fs_info, &ih_info); 593 if (r) 594 goto free; 595 596 if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) { 597 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 598 if (r) 599 goto late_fini; 600 } else { 601 /* free gfx ras_if if ras is not supported */ 602 r = 0; 603 goto free; 604 } 605 606 return 0; 607 late_fini: 608 amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info); 609 free: 610 kfree(adev->gfx.ras_if); 611 adev->gfx.ras_if = NULL; 612 return r; 613 } 614 615 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev) 616 { 617 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) && 618 adev->gfx.ras_if) { 619 struct ras_common_if *ras_if = adev->gfx.ras_if; 620 struct ras_ih_if ih_info = { 621 .head = *ras_if, 622 .cb = amdgpu_gfx_process_ras_data_cb, 623 }; 624 625 amdgpu_ras_late_fini(adev, ras_if, &ih_info); 626 kfree(ras_if); 627 } 628 } 629 630 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 631 void *err_data, 632 struct amdgpu_iv_entry *entry) 633 { 634 /* TODO ue will trigger an interrupt. 635 * 636 * When “Full RAS” is enabled, the per-IP interrupt sources should 637 * be disabled and the driver should only look for the aggregated 638 * interrupt via sync flood 639 */ 640 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { 641 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 642 if (adev->gfx.funcs->query_ras_error_count) 643 adev->gfx.funcs->query_ras_error_count(adev, err_data); 644 amdgpu_ras_reset_gpu(adev, 0); 645 } 646 return AMDGPU_RAS_SUCCESS; 647 } 648 649 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 650 struct amdgpu_irq_src *source, 651 struct amdgpu_iv_entry *entry) 652 { 653 struct ras_common_if *ras_if = adev->gfx.ras_if; 654 struct ras_dispatch_if ih_data = { 655 .entry = entry, 656 }; 657 658 if (!ras_if) 659 return 0; 660 661 ih_data.head = *ras_if; 662 663 DRM_ERROR("CP ECC ERROR IRQ\n"); 664 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 665 return 0; 666 } 667