1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 34 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 35 { 36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 37 38 if (robj) { 39 if (robj->gem_base.import_attach) 40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 41 amdgpu_mn_unregister(robj); 42 amdgpu_bo_unref(&robj); 43 } 44 } 45 46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 47 int alignment, u32 initial_domain, 48 u64 flags, bool kernel, 49 struct drm_gem_object **obj) 50 { 51 struct amdgpu_bo *robj; 52 unsigned long max_size; 53 int r; 54 55 *obj = NULL; 56 /* At least align on page size */ 57 if (alignment < PAGE_SIZE) { 58 alignment = PAGE_SIZE; 59 } 60 61 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { 62 /* Maximum bo size is the unpinned gtt size since we use the gtt to 63 * handle vram to system pool migrations. 64 */ 65 max_size = adev->mc.gtt_size - adev->gart_pin_size; 66 if (size > max_size) { 67 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", 68 size >> 20, max_size >> 20); 69 return -ENOMEM; 70 } 71 } 72 retry: 73 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, 74 flags, NULL, NULL, &robj); 75 if (r) { 76 if (r != -ERESTARTSYS) { 77 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 78 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 79 goto retry; 80 } 81 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 82 size, initial_domain, alignment, r); 83 } 84 return r; 85 } 86 *obj = &robj->gem_base; 87 88 return 0; 89 } 90 91 void amdgpu_gem_force_release(struct amdgpu_device *adev) 92 { 93 struct drm_device *ddev = adev->ddev; 94 struct drm_file *file; 95 96 mutex_lock(&ddev->filelist_mutex); 97 98 list_for_each_entry(file, &ddev->filelist, lhead) { 99 struct drm_gem_object *gobj; 100 int handle; 101 102 WARN_ONCE(1, "Still active user space clients!\n"); 103 spin_lock(&file->table_lock); 104 idr_for_each_entry(&file->object_idr, gobj, handle) { 105 WARN_ONCE(1, "And also active allocations!\n"); 106 drm_gem_object_unreference_unlocked(gobj); 107 } 108 idr_destroy(&file->object_idr); 109 spin_unlock(&file->table_lock); 110 } 111 112 mutex_unlock(&ddev->filelist_mutex); 113 } 114 115 /* 116 * Call from drm_gem_handle_create which appear in both new and open ioctl 117 * case. 118 */ 119 int amdgpu_gem_object_open(struct drm_gem_object *obj, 120 struct drm_file *file_priv) 121 { 122 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 123 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 124 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 125 struct amdgpu_vm *vm = &fpriv->vm; 126 struct amdgpu_bo_va *bo_va; 127 int r; 128 r = amdgpu_bo_reserve(abo, false); 129 if (r) 130 return r; 131 132 bo_va = amdgpu_vm_bo_find(vm, abo); 133 if (!bo_va) { 134 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 135 } else { 136 ++bo_va->ref_count; 137 } 138 amdgpu_bo_unreserve(abo); 139 return 0; 140 } 141 142 void amdgpu_gem_object_close(struct drm_gem_object *obj, 143 struct drm_file *file_priv) 144 { 145 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 146 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 147 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 148 struct amdgpu_vm *vm = &fpriv->vm; 149 150 struct amdgpu_bo_list_entry vm_pd; 151 struct list_head list, duplicates; 152 struct ttm_validate_buffer tv; 153 struct ww_acquire_ctx ticket; 154 struct amdgpu_bo_va *bo_va; 155 struct dma_fence *fence = NULL; 156 int r; 157 158 INIT_LIST_HEAD(&list); 159 INIT_LIST_HEAD(&duplicates); 160 161 tv.bo = &bo->tbo; 162 tv.shared = true; 163 list_add(&tv.head, &list); 164 165 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 166 167 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 168 if (r) { 169 dev_err(adev->dev, "leaking bo va because " 170 "we fail to reserve bo (%d)\n", r); 171 return; 172 } 173 bo_va = amdgpu_vm_bo_find(vm, bo); 174 if (bo_va) { 175 if (--bo_va->ref_count == 0) { 176 amdgpu_vm_bo_rmv(adev, bo_va); 177 178 r = amdgpu_vm_clear_freed(adev, vm, &fence); 179 if (unlikely(r)) { 180 dev_err(adev->dev, "failed to clear page " 181 "tables on GEM object close (%d)\n", r); 182 } 183 184 if (fence) { 185 amdgpu_bo_fence(bo, fence, true); 186 dma_fence_put(fence); 187 } 188 } 189 } 190 ttm_eu_backoff_reservation(&ticket, &list); 191 } 192 193 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) 194 { 195 if (r == -EDEADLK) { 196 r = amdgpu_gpu_reset(adev); 197 if (!r) 198 r = -EAGAIN; 199 } 200 return r; 201 } 202 203 /* 204 * GEM ioctls. 205 */ 206 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 207 struct drm_file *filp) 208 { 209 struct amdgpu_device *adev = dev->dev_private; 210 union drm_amdgpu_gem_create *args = data; 211 uint64_t size = args->in.bo_size; 212 struct drm_gem_object *gobj; 213 uint32_t handle; 214 bool kernel = false; 215 int r; 216 217 /* reject invalid gem flags */ 218 if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 219 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 220 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 221 AMDGPU_GEM_CREATE_VRAM_CLEARED| 222 AMDGPU_GEM_CREATE_SHADOW | 223 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) { 224 r = -EINVAL; 225 goto error_unlock; 226 } 227 /* reject invalid gem domains */ 228 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU | 229 AMDGPU_GEM_DOMAIN_GTT | 230 AMDGPU_GEM_DOMAIN_VRAM | 231 AMDGPU_GEM_DOMAIN_GDS | 232 AMDGPU_GEM_DOMAIN_GWS | 233 AMDGPU_GEM_DOMAIN_OA)) { 234 r = -EINVAL; 235 goto error_unlock; 236 } 237 238 /* create a gem object to contain this object in */ 239 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 240 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 241 kernel = true; 242 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 243 size = size << AMDGPU_GDS_SHIFT; 244 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 245 size = size << AMDGPU_GWS_SHIFT; 246 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 247 size = size << AMDGPU_OA_SHIFT; 248 else { 249 r = -EINVAL; 250 goto error_unlock; 251 } 252 } 253 size = roundup(size, PAGE_SIZE); 254 255 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 256 (u32)(0xffffffff & args->in.domains), 257 args->in.domain_flags, 258 kernel, &gobj); 259 if (r) 260 goto error_unlock; 261 262 r = drm_gem_handle_create(filp, gobj, &handle); 263 /* drop reference from allocate - handle holds it now */ 264 drm_gem_object_unreference_unlocked(gobj); 265 if (r) 266 goto error_unlock; 267 268 memset(args, 0, sizeof(*args)); 269 args->out.handle = handle; 270 return 0; 271 272 error_unlock: 273 r = amdgpu_gem_handle_lockup(adev, r); 274 return r; 275 } 276 277 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 278 struct drm_file *filp) 279 { 280 struct amdgpu_device *adev = dev->dev_private; 281 struct drm_amdgpu_gem_userptr *args = data; 282 struct drm_gem_object *gobj; 283 struct amdgpu_bo *bo; 284 uint32_t handle; 285 int r; 286 287 if (offset_in_page(args->addr | args->size)) 288 return -EINVAL; 289 290 /* reject unknown flag values */ 291 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 292 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 293 AMDGPU_GEM_USERPTR_REGISTER)) 294 return -EINVAL; 295 296 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 297 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 298 299 /* if we want to write to it we must install a MMU notifier */ 300 return -EACCES; 301 } 302 303 /* create a gem object to contain this object in */ 304 r = amdgpu_gem_object_create(adev, args->size, 0, 305 AMDGPU_GEM_DOMAIN_CPU, 0, 306 0, &gobj); 307 if (r) 308 goto handle_lockup; 309 310 bo = gem_to_amdgpu_bo(gobj); 311 bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT; 312 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 313 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 314 if (r) 315 goto release_object; 316 317 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 318 r = amdgpu_mn_register(bo, args->addr); 319 if (r) 320 goto release_object; 321 } 322 323 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 324 down_read(¤t->mm->mmap_sem); 325 326 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 327 bo->tbo.ttm->pages); 328 if (r) 329 goto unlock_mmap_sem; 330 331 r = amdgpu_bo_reserve(bo, true); 332 if (r) 333 goto free_pages; 334 335 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 336 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 337 amdgpu_bo_unreserve(bo); 338 if (r) 339 goto free_pages; 340 341 up_read(¤t->mm->mmap_sem); 342 } 343 344 r = drm_gem_handle_create(filp, gobj, &handle); 345 /* drop reference from allocate - handle holds it now */ 346 drm_gem_object_unreference_unlocked(gobj); 347 if (r) 348 goto handle_lockup; 349 350 args->handle = handle; 351 return 0; 352 353 free_pages: 354 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false); 355 356 unlock_mmap_sem: 357 up_read(¤t->mm->mmap_sem); 358 359 release_object: 360 drm_gem_object_unreference_unlocked(gobj); 361 362 handle_lockup: 363 r = amdgpu_gem_handle_lockup(adev, r); 364 365 return r; 366 } 367 368 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 369 struct drm_device *dev, 370 uint32_t handle, uint64_t *offset_p) 371 { 372 struct drm_gem_object *gobj; 373 struct amdgpu_bo *robj; 374 375 gobj = drm_gem_object_lookup(filp, handle); 376 if (gobj == NULL) { 377 return -ENOENT; 378 } 379 robj = gem_to_amdgpu_bo(gobj); 380 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 381 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 382 drm_gem_object_unreference_unlocked(gobj); 383 return -EPERM; 384 } 385 *offset_p = amdgpu_bo_mmap_offset(robj); 386 drm_gem_object_unreference_unlocked(gobj); 387 return 0; 388 } 389 390 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 391 struct drm_file *filp) 392 { 393 union drm_amdgpu_gem_mmap *args = data; 394 uint32_t handle = args->in.handle; 395 memset(args, 0, sizeof(*args)); 396 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 397 } 398 399 /** 400 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 401 * 402 * @timeout_ns: timeout in ns 403 * 404 * Calculate the timeout in jiffies from an absolute timeout in ns. 405 */ 406 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 407 { 408 unsigned long timeout_jiffies; 409 ktime_t timeout; 410 411 /* clamp timeout if it's to large */ 412 if (((int64_t)timeout_ns) < 0) 413 return MAX_SCHEDULE_TIMEOUT; 414 415 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 416 if (ktime_to_ns(timeout) < 0) 417 return 0; 418 419 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 420 /* clamp timeout to avoid unsigned-> signed overflow */ 421 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 422 return MAX_SCHEDULE_TIMEOUT - 1; 423 424 return timeout_jiffies; 425 } 426 427 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 428 struct drm_file *filp) 429 { 430 struct amdgpu_device *adev = dev->dev_private; 431 union drm_amdgpu_gem_wait_idle *args = data; 432 struct drm_gem_object *gobj; 433 struct amdgpu_bo *robj; 434 uint32_t handle = args->in.handle; 435 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 436 int r = 0; 437 long ret; 438 439 gobj = drm_gem_object_lookup(filp, handle); 440 if (gobj == NULL) { 441 return -ENOENT; 442 } 443 robj = gem_to_amdgpu_bo(gobj); 444 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 445 timeout); 446 447 /* ret == 0 means not signaled, 448 * ret > 0 means signaled 449 * ret < 0 means interrupted before timeout 450 */ 451 if (ret >= 0) { 452 memset(args, 0, sizeof(*args)); 453 args->out.status = (ret == 0); 454 } else 455 r = ret; 456 457 drm_gem_object_unreference_unlocked(gobj); 458 r = amdgpu_gem_handle_lockup(adev, r); 459 return r; 460 } 461 462 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 463 struct drm_file *filp) 464 { 465 struct drm_amdgpu_gem_metadata *args = data; 466 struct drm_gem_object *gobj; 467 struct amdgpu_bo *robj; 468 int r = -1; 469 470 DRM_DEBUG("%d \n", args->handle); 471 gobj = drm_gem_object_lookup(filp, args->handle); 472 if (gobj == NULL) 473 return -ENOENT; 474 robj = gem_to_amdgpu_bo(gobj); 475 476 r = amdgpu_bo_reserve(robj, false); 477 if (unlikely(r != 0)) 478 goto out; 479 480 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 481 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 482 r = amdgpu_bo_get_metadata(robj, args->data.data, 483 sizeof(args->data.data), 484 &args->data.data_size_bytes, 485 &args->data.flags); 486 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 487 if (args->data.data_size_bytes > sizeof(args->data.data)) { 488 r = -EINVAL; 489 goto unreserve; 490 } 491 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 492 if (!r) 493 r = amdgpu_bo_set_metadata(robj, args->data.data, 494 args->data.data_size_bytes, 495 args->data.flags); 496 } 497 498 unreserve: 499 amdgpu_bo_unreserve(robj); 500 out: 501 drm_gem_object_unreference_unlocked(gobj); 502 return r; 503 } 504 505 static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo) 506 { 507 /* if anything is swapped out don't swap it in here, 508 just abort and wait for the next CS */ 509 if (!amdgpu_bo_gpu_accessible(bo)) 510 return -ERESTARTSYS; 511 512 if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow)) 513 return -ERESTARTSYS; 514 515 return 0; 516 } 517 518 /** 519 * amdgpu_gem_va_update_vm -update the bo_va in its VM 520 * 521 * @adev: amdgpu_device pointer 522 * @vm: vm to update 523 * @bo_va: bo_va to update 524 * @list: validation list 525 * @operation: map, unmap or clear 526 * 527 * Update the bo_va directly after setting its address. Errors are not 528 * vital here, so they are not reported back to userspace. 529 */ 530 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 531 struct amdgpu_vm *vm, 532 struct amdgpu_bo_va *bo_va, 533 struct list_head *list, 534 uint32_t operation) 535 { 536 struct ttm_validate_buffer *entry; 537 int r = -ERESTARTSYS; 538 539 list_for_each_entry(entry, list, head) { 540 struct amdgpu_bo *bo = 541 container_of(entry->bo, struct amdgpu_bo, tbo); 542 if (amdgpu_gem_va_check(NULL, bo)) 543 goto error; 544 } 545 546 r = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_gem_va_check, 547 NULL); 548 if (r) 549 goto error; 550 551 r = amdgpu_vm_update_directories(adev, vm); 552 if (r) 553 goto error; 554 555 r = amdgpu_vm_clear_freed(adev, vm, NULL); 556 if (r) 557 goto error; 558 559 if (operation == AMDGPU_VA_OP_MAP || 560 operation == AMDGPU_VA_OP_REPLACE) 561 r = amdgpu_vm_bo_update(adev, bo_va, false); 562 563 error: 564 if (r && r != -ERESTARTSYS) 565 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 566 } 567 568 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 569 struct drm_file *filp) 570 { 571 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 572 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 573 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 574 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 575 AMDGPU_VM_PAGE_PRT; 576 577 struct drm_amdgpu_gem_va *args = data; 578 struct drm_gem_object *gobj; 579 struct amdgpu_device *adev = dev->dev_private; 580 struct amdgpu_fpriv *fpriv = filp->driver_priv; 581 struct amdgpu_bo *abo; 582 struct amdgpu_bo_va *bo_va; 583 struct amdgpu_bo_list_entry vm_pd; 584 struct ttm_validate_buffer tv; 585 struct ww_acquire_ctx ticket; 586 struct list_head list; 587 uint64_t va_flags; 588 int r = 0; 589 590 if (!adev->vm_manager.enabled) 591 return -ENOTTY; 592 593 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 594 dev_err(&dev->pdev->dev, 595 "va_address 0x%lX is in reserved area 0x%X\n", 596 (unsigned long)args->va_address, 597 AMDGPU_VA_RESERVED_SIZE); 598 return -EINVAL; 599 } 600 601 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 602 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 603 args->flags); 604 return -EINVAL; 605 } 606 607 switch (args->operation) { 608 case AMDGPU_VA_OP_MAP: 609 case AMDGPU_VA_OP_UNMAP: 610 case AMDGPU_VA_OP_CLEAR: 611 case AMDGPU_VA_OP_REPLACE: 612 break; 613 default: 614 dev_err(&dev->pdev->dev, "unsupported operation %d\n", 615 args->operation); 616 return -EINVAL; 617 } 618 619 INIT_LIST_HEAD(&list); 620 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 621 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 622 gobj = drm_gem_object_lookup(filp, args->handle); 623 if (gobj == NULL) 624 return -ENOENT; 625 abo = gem_to_amdgpu_bo(gobj); 626 tv.bo = &abo->tbo; 627 tv.shared = false; 628 list_add(&tv.head, &list); 629 } else { 630 gobj = NULL; 631 abo = NULL; 632 } 633 634 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 635 636 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); 637 if (r) 638 goto error_unref; 639 640 if (abo) { 641 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 642 if (!bo_va) { 643 r = -ENOENT; 644 goto error_backoff; 645 } 646 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 647 bo_va = fpriv->prt_va; 648 } else { 649 bo_va = NULL; 650 } 651 652 switch (args->operation) { 653 case AMDGPU_VA_OP_MAP: 654 r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, 655 args->map_size); 656 if (r) 657 goto error_backoff; 658 659 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); 660 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 661 args->offset_in_bo, args->map_size, 662 va_flags); 663 break; 664 case AMDGPU_VA_OP_UNMAP: 665 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 666 break; 667 668 case AMDGPU_VA_OP_CLEAR: 669 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 670 args->va_address, 671 args->map_size); 672 break; 673 case AMDGPU_VA_OP_REPLACE: 674 r = amdgpu_vm_alloc_pts(adev, bo_va->vm, args->va_address, 675 args->map_size); 676 if (r) 677 goto error_backoff; 678 679 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); 680 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 681 args->offset_in_bo, args->map_size, 682 va_flags); 683 break; 684 default: 685 break; 686 } 687 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 688 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, 689 args->operation); 690 691 error_backoff: 692 ttm_eu_backoff_reservation(&ticket, &list); 693 694 error_unref: 695 drm_gem_object_unreference_unlocked(gobj); 696 return r; 697 } 698 699 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 700 struct drm_file *filp) 701 { 702 struct drm_amdgpu_gem_op *args = data; 703 struct drm_gem_object *gobj; 704 struct amdgpu_bo *robj; 705 int r; 706 707 gobj = drm_gem_object_lookup(filp, args->handle); 708 if (gobj == NULL) { 709 return -ENOENT; 710 } 711 robj = gem_to_amdgpu_bo(gobj); 712 713 r = amdgpu_bo_reserve(robj, false); 714 if (unlikely(r)) 715 goto out; 716 717 switch (args->op) { 718 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 719 struct drm_amdgpu_gem_create_in info; 720 void __user *out = (void __user *)(long)args->value; 721 722 info.bo_size = robj->gem_base.size; 723 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 724 info.domains = robj->prefered_domains; 725 info.domain_flags = robj->flags; 726 amdgpu_bo_unreserve(robj); 727 if (copy_to_user(out, &info, sizeof(info))) 728 r = -EFAULT; 729 break; 730 } 731 case AMDGPU_GEM_OP_SET_PLACEMENT: 732 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 733 r = -EPERM; 734 amdgpu_bo_unreserve(robj); 735 break; 736 } 737 robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 738 AMDGPU_GEM_DOMAIN_GTT | 739 AMDGPU_GEM_DOMAIN_CPU); 740 robj->allowed_domains = robj->prefered_domains; 741 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 742 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 743 744 amdgpu_bo_unreserve(robj); 745 break; 746 default: 747 amdgpu_bo_unreserve(robj); 748 r = -EINVAL; 749 } 750 751 out: 752 drm_gem_object_unreference_unlocked(gobj); 753 return r; 754 } 755 756 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 757 struct drm_device *dev, 758 struct drm_mode_create_dumb *args) 759 { 760 struct amdgpu_device *adev = dev->dev_private; 761 struct drm_gem_object *gobj; 762 uint32_t handle; 763 int r; 764 765 args->pitch = amdgpu_align_pitch(adev, args->width, 766 DIV_ROUND_UP(args->bpp, 8), 0); 767 args->size = (u64)args->pitch * args->height; 768 args->size = ALIGN(args->size, PAGE_SIZE); 769 770 r = amdgpu_gem_object_create(adev, args->size, 0, 771 AMDGPU_GEM_DOMAIN_VRAM, 772 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 773 ttm_bo_type_device, 774 &gobj); 775 if (r) 776 return -ENOMEM; 777 778 r = drm_gem_handle_create(file_priv, gobj, &handle); 779 /* drop reference from allocate - handle holds it now */ 780 drm_gem_object_unreference_unlocked(gobj); 781 if (r) { 782 return r; 783 } 784 args->handle = handle; 785 return 0; 786 } 787 788 #if defined(CONFIG_DEBUG_FS) 789 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 790 { 791 struct drm_gem_object *gobj = ptr; 792 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 793 struct seq_file *m = data; 794 795 unsigned domain; 796 const char *placement; 797 unsigned pin_count; 798 799 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 800 switch (domain) { 801 case AMDGPU_GEM_DOMAIN_VRAM: 802 placement = "VRAM"; 803 break; 804 case AMDGPU_GEM_DOMAIN_GTT: 805 placement = " GTT"; 806 break; 807 case AMDGPU_GEM_DOMAIN_CPU: 808 default: 809 placement = " CPU"; 810 break; 811 } 812 seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx", 813 id, amdgpu_bo_size(bo), placement, 814 amdgpu_bo_gpu_offset(bo)); 815 816 pin_count = ACCESS_ONCE(bo->pin_count); 817 if (pin_count) 818 seq_printf(m, " pin count %d", pin_count); 819 seq_printf(m, "\n"); 820 821 return 0; 822 } 823 824 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 825 { 826 struct drm_info_node *node = (struct drm_info_node *)m->private; 827 struct drm_device *dev = node->minor->dev; 828 struct drm_file *file; 829 int r; 830 831 r = mutex_lock_interruptible(&dev->filelist_mutex); 832 if (r) 833 return r; 834 835 list_for_each_entry(file, &dev->filelist, lhead) { 836 struct task_struct *task; 837 838 /* 839 * Although we have a valid reference on file->pid, that does 840 * not guarantee that the task_struct who called get_pid() is 841 * still alive (e.g. get_pid(current) => fork() => exit()). 842 * Therefore, we need to protect this ->comm access using RCU. 843 */ 844 rcu_read_lock(); 845 task = pid_task(file->pid, PIDTYPE_PID); 846 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 847 task ? task->comm : "<unknown>"); 848 rcu_read_unlock(); 849 850 spin_lock(&file->table_lock); 851 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 852 spin_unlock(&file->table_lock); 853 } 854 855 mutex_unlock(&dev->filelist_mutex); 856 return 0; 857 } 858 859 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 860 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 861 }; 862 #endif 863 864 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) 865 { 866 #if defined(CONFIG_DEBUG_FS) 867 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 868 #endif 869 return 0; 870 } 871