1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_debugfs.h> 36 #include <drm/drm_gem_ttm_helper.h> 37 38 #include "amdgpu.h" 39 #include "amdgpu_display.h" 40 #include "amdgpu_dma_buf.h" 41 #include "amdgpu_xgmi.h" 42 43 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; 44 45 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 46 { 47 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 48 49 if (robj) { 50 amdgpu_mn_unregister(robj); 51 amdgpu_bo_unref(&robj); 52 } 53 } 54 55 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 56 int alignment, u32 initial_domain, 57 u64 flags, enum ttm_bo_type type, 58 struct dma_resv *resv, 59 struct drm_gem_object **obj) 60 { 61 struct amdgpu_bo *bo; 62 struct amdgpu_bo_param bp; 63 int r; 64 65 memset(&bp, 0, sizeof(bp)); 66 *obj = NULL; 67 68 bp.size = size; 69 bp.byte_align = alignment; 70 bp.type = type; 71 bp.resv = resv; 72 bp.preferred_domain = initial_domain; 73 bp.flags = flags; 74 bp.domain = initial_domain; 75 r = amdgpu_bo_create(adev, &bp, &bo); 76 if (r) 77 return r; 78 79 *obj = &bo->tbo.base; 80 (*obj)->funcs = &amdgpu_gem_object_funcs; 81 82 return 0; 83 } 84 85 void amdgpu_gem_force_release(struct amdgpu_device *adev) 86 { 87 struct drm_device *ddev = adev_to_drm(adev); 88 struct drm_file *file; 89 90 mutex_lock(&ddev->filelist_mutex); 91 92 list_for_each_entry(file, &ddev->filelist, lhead) { 93 struct drm_gem_object *gobj; 94 int handle; 95 96 WARN_ONCE(1, "Still active user space clients!\n"); 97 spin_lock(&file->table_lock); 98 idr_for_each_entry(&file->object_idr, gobj, handle) { 99 WARN_ONCE(1, "And also active allocations!\n"); 100 drm_gem_object_put(gobj); 101 } 102 idr_destroy(&file->object_idr); 103 spin_unlock(&file->table_lock); 104 } 105 106 mutex_unlock(&ddev->filelist_mutex); 107 } 108 109 /* 110 * Call from drm_gem_handle_create which appear in both new and open ioctl 111 * case. 112 */ 113 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 114 struct drm_file *file_priv) 115 { 116 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 117 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 118 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 119 struct amdgpu_vm *vm = &fpriv->vm; 120 struct amdgpu_bo_va *bo_va; 121 struct mm_struct *mm; 122 int r; 123 124 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 125 if (mm && mm != current->mm) 126 return -EPERM; 127 128 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 129 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 130 return -EPERM; 131 132 r = amdgpu_bo_reserve(abo, false); 133 if (r) 134 return r; 135 136 bo_va = amdgpu_vm_bo_find(vm, abo); 137 if (!bo_va) { 138 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 139 } else { 140 ++bo_va->ref_count; 141 } 142 amdgpu_bo_unreserve(abo); 143 return 0; 144 } 145 146 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 147 struct drm_file *file_priv) 148 { 149 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 150 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 151 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 152 struct amdgpu_vm *vm = &fpriv->vm; 153 154 struct amdgpu_bo_list_entry vm_pd; 155 struct list_head list, duplicates; 156 struct dma_fence *fence = NULL; 157 struct ttm_validate_buffer tv; 158 struct ww_acquire_ctx ticket; 159 struct amdgpu_bo_va *bo_va; 160 long r; 161 162 INIT_LIST_HEAD(&list); 163 INIT_LIST_HEAD(&duplicates); 164 165 tv.bo = &bo->tbo; 166 tv.num_shared = 2; 167 list_add(&tv.head, &list); 168 169 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 170 171 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 172 if (r) { 173 dev_err(adev->dev, "leaking bo va because " 174 "we fail to reserve bo (%ld)\n", r); 175 return; 176 } 177 bo_va = amdgpu_vm_bo_find(vm, bo); 178 if (!bo_va || --bo_va->ref_count) 179 goto out_unlock; 180 181 amdgpu_vm_bo_rmv(adev, bo_va); 182 if (!amdgpu_vm_ready(vm)) 183 goto out_unlock; 184 185 fence = dma_resv_get_excl(bo->tbo.base.resv); 186 if (fence) { 187 amdgpu_bo_fence(bo, fence, true); 188 fence = NULL; 189 } 190 191 r = amdgpu_vm_clear_freed(adev, vm, &fence); 192 if (r || !fence) 193 goto out_unlock; 194 195 amdgpu_bo_fence(bo, fence, true); 196 dma_fence_put(fence); 197 198 out_unlock: 199 if (unlikely(r < 0)) 200 dev_err(adev->dev, "failed to clear page " 201 "tables on GEM object close (%ld)\n", r); 202 ttm_eu_backoff_reservation(&ticket, &list); 203 } 204 205 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 206 .free = amdgpu_gem_object_free, 207 .open = amdgpu_gem_object_open, 208 .close = amdgpu_gem_object_close, 209 .export = amdgpu_gem_prime_export, 210 .vmap = drm_gem_ttm_vmap, 211 .vunmap = drm_gem_ttm_vunmap, 212 }; 213 214 /* 215 * GEM ioctls. 216 */ 217 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 218 struct drm_file *filp) 219 { 220 struct amdgpu_device *adev = drm_to_adev(dev); 221 struct amdgpu_fpriv *fpriv = filp->driver_priv; 222 struct amdgpu_vm *vm = &fpriv->vm; 223 union drm_amdgpu_gem_create *args = data; 224 uint64_t flags = args->in.domain_flags; 225 uint64_t size = args->in.bo_size; 226 struct dma_resv *resv = NULL; 227 struct drm_gem_object *gobj; 228 uint32_t handle, initial_domain; 229 int r; 230 231 /* reject invalid gem flags */ 232 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 233 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 234 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 235 AMDGPU_GEM_CREATE_VRAM_CLEARED | 236 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 237 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 238 AMDGPU_GEM_CREATE_ENCRYPTED)) 239 240 return -EINVAL; 241 242 /* reject invalid gem domains */ 243 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 244 return -EINVAL; 245 246 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 247 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 248 return -EINVAL; 249 } 250 251 /* create a gem object to contain this object in */ 252 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 253 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 254 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 255 /* if gds bo is created from user space, it must be 256 * passed to bo list 257 */ 258 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 259 return -EINVAL; 260 } 261 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 262 } 263 264 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 265 r = amdgpu_bo_reserve(vm->root.base.bo, false); 266 if (r) 267 return r; 268 269 resv = vm->root.base.bo->tbo.base.resv; 270 } 271 272 initial_domain = (u32)(0xffffffff & args->in.domains); 273 retry: 274 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 275 initial_domain, 276 flags, ttm_bo_type_device, resv, &gobj); 277 if (r) { 278 if (r != -ERESTARTSYS) { 279 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 280 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 281 goto retry; 282 } 283 284 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 285 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 286 goto retry; 287 } 288 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 289 size, initial_domain, args->in.alignment, r); 290 } 291 return r; 292 } 293 294 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 295 if (!r) { 296 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 297 298 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 299 } 300 amdgpu_bo_unreserve(vm->root.base.bo); 301 } 302 if (r) 303 return r; 304 305 r = drm_gem_handle_create(filp, gobj, &handle); 306 /* drop reference from allocate - handle holds it now */ 307 drm_gem_object_put(gobj); 308 if (r) 309 return r; 310 311 memset(args, 0, sizeof(*args)); 312 args->out.handle = handle; 313 return 0; 314 } 315 316 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 317 struct drm_file *filp) 318 { 319 struct ttm_operation_ctx ctx = { true, false }; 320 struct amdgpu_device *adev = drm_to_adev(dev); 321 struct drm_amdgpu_gem_userptr *args = data; 322 struct drm_gem_object *gobj; 323 struct amdgpu_bo *bo; 324 uint32_t handle; 325 int r; 326 327 args->addr = untagged_addr(args->addr); 328 329 if (offset_in_page(args->addr | args->size)) 330 return -EINVAL; 331 332 /* reject unknown flag values */ 333 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 334 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 335 AMDGPU_GEM_USERPTR_REGISTER)) 336 return -EINVAL; 337 338 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 339 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 340 341 /* if we want to write to it we must install a MMU notifier */ 342 return -EACCES; 343 } 344 345 /* create a gem object to contain this object in */ 346 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 347 0, ttm_bo_type_device, NULL, &gobj); 348 if (r) 349 return r; 350 351 bo = gem_to_amdgpu_bo(gobj); 352 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 353 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 354 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 355 if (r) 356 goto release_object; 357 358 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 359 r = amdgpu_mn_register(bo, args->addr); 360 if (r) 361 goto release_object; 362 } 363 364 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 365 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 366 if (r) 367 goto release_object; 368 369 r = amdgpu_bo_reserve(bo, true); 370 if (r) 371 goto user_pages_done; 372 373 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 374 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 375 amdgpu_bo_unreserve(bo); 376 if (r) 377 goto user_pages_done; 378 } 379 380 r = drm_gem_handle_create(filp, gobj, &handle); 381 if (r) 382 goto user_pages_done; 383 384 args->handle = handle; 385 386 user_pages_done: 387 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 388 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 389 390 release_object: 391 drm_gem_object_put(gobj); 392 393 return r; 394 } 395 396 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 397 struct drm_device *dev, 398 uint32_t handle, uint64_t *offset_p) 399 { 400 struct drm_gem_object *gobj; 401 struct amdgpu_bo *robj; 402 403 gobj = drm_gem_object_lookup(filp, handle); 404 if (gobj == NULL) { 405 return -ENOENT; 406 } 407 robj = gem_to_amdgpu_bo(gobj); 408 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 409 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 410 drm_gem_object_put(gobj); 411 return -EPERM; 412 } 413 *offset_p = amdgpu_bo_mmap_offset(robj); 414 drm_gem_object_put(gobj); 415 return 0; 416 } 417 418 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 419 struct drm_file *filp) 420 { 421 union drm_amdgpu_gem_mmap *args = data; 422 uint32_t handle = args->in.handle; 423 memset(args, 0, sizeof(*args)); 424 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 425 } 426 427 /** 428 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 429 * 430 * @timeout_ns: timeout in ns 431 * 432 * Calculate the timeout in jiffies from an absolute timeout in ns. 433 */ 434 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 435 { 436 unsigned long timeout_jiffies; 437 ktime_t timeout; 438 439 /* clamp timeout if it's to large */ 440 if (((int64_t)timeout_ns) < 0) 441 return MAX_SCHEDULE_TIMEOUT; 442 443 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 444 if (ktime_to_ns(timeout) < 0) 445 return 0; 446 447 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 448 /* clamp timeout to avoid unsigned-> signed overflow */ 449 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 450 return MAX_SCHEDULE_TIMEOUT - 1; 451 452 return timeout_jiffies; 453 } 454 455 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 456 struct drm_file *filp) 457 { 458 union drm_amdgpu_gem_wait_idle *args = data; 459 struct drm_gem_object *gobj; 460 struct amdgpu_bo *robj; 461 uint32_t handle = args->in.handle; 462 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 463 int r = 0; 464 long ret; 465 466 gobj = drm_gem_object_lookup(filp, handle); 467 if (gobj == NULL) { 468 return -ENOENT; 469 } 470 robj = gem_to_amdgpu_bo(gobj); 471 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 472 timeout); 473 474 /* ret == 0 means not signaled, 475 * ret > 0 means signaled 476 * ret < 0 means interrupted before timeout 477 */ 478 if (ret >= 0) { 479 memset(args, 0, sizeof(*args)); 480 args->out.status = (ret == 0); 481 } else 482 r = ret; 483 484 drm_gem_object_put(gobj); 485 return r; 486 } 487 488 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 489 struct drm_file *filp) 490 { 491 struct drm_amdgpu_gem_metadata *args = data; 492 struct drm_gem_object *gobj; 493 struct amdgpu_bo *robj; 494 int r = -1; 495 496 DRM_DEBUG("%d \n", args->handle); 497 gobj = drm_gem_object_lookup(filp, args->handle); 498 if (gobj == NULL) 499 return -ENOENT; 500 robj = gem_to_amdgpu_bo(gobj); 501 502 r = amdgpu_bo_reserve(robj, false); 503 if (unlikely(r != 0)) 504 goto out; 505 506 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 507 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 508 r = amdgpu_bo_get_metadata(robj, args->data.data, 509 sizeof(args->data.data), 510 &args->data.data_size_bytes, 511 &args->data.flags); 512 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 513 if (args->data.data_size_bytes > sizeof(args->data.data)) { 514 r = -EINVAL; 515 goto unreserve; 516 } 517 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 518 if (!r) 519 r = amdgpu_bo_set_metadata(robj, args->data.data, 520 args->data.data_size_bytes, 521 args->data.flags); 522 } 523 524 unreserve: 525 amdgpu_bo_unreserve(robj); 526 out: 527 drm_gem_object_put(gobj); 528 return r; 529 } 530 531 /** 532 * amdgpu_gem_va_update_vm -update the bo_va in its VM 533 * 534 * @adev: amdgpu_device pointer 535 * @vm: vm to update 536 * @bo_va: bo_va to update 537 * @operation: map, unmap or clear 538 * 539 * Update the bo_va directly after setting its address. Errors are not 540 * vital here, so they are not reported back to userspace. 541 */ 542 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 543 struct amdgpu_vm *vm, 544 struct amdgpu_bo_va *bo_va, 545 uint32_t operation) 546 { 547 int r; 548 549 if (!amdgpu_vm_ready(vm)) 550 return; 551 552 r = amdgpu_vm_clear_freed(adev, vm, NULL); 553 if (r) 554 goto error; 555 556 if (operation == AMDGPU_VA_OP_MAP || 557 operation == AMDGPU_VA_OP_REPLACE) { 558 r = amdgpu_vm_bo_update(adev, bo_va, false); 559 if (r) 560 goto error; 561 } 562 563 r = amdgpu_vm_update_pdes(adev, vm, false); 564 565 error: 566 if (r && r != -ERESTARTSYS) 567 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 568 } 569 570 /** 571 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 572 * 573 * @adev: amdgpu_device pointer 574 * @flags: GEM UAPI flags 575 * 576 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 577 */ 578 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 579 { 580 uint64_t pte_flag = 0; 581 582 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 583 pte_flag |= AMDGPU_PTE_EXECUTABLE; 584 if (flags & AMDGPU_VM_PAGE_READABLE) 585 pte_flag |= AMDGPU_PTE_READABLE; 586 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 587 pte_flag |= AMDGPU_PTE_WRITEABLE; 588 if (flags & AMDGPU_VM_PAGE_PRT) 589 pte_flag |= AMDGPU_PTE_PRT; 590 591 if (adev->gmc.gmc_funcs->map_mtype) 592 pte_flag |= amdgpu_gmc_map_mtype(adev, 593 flags & AMDGPU_VM_MTYPE_MASK); 594 595 return pte_flag; 596 } 597 598 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 599 struct drm_file *filp) 600 { 601 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 602 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 603 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 604 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 605 AMDGPU_VM_PAGE_PRT; 606 607 struct drm_amdgpu_gem_va *args = data; 608 struct drm_gem_object *gobj; 609 struct amdgpu_device *adev = drm_to_adev(dev); 610 struct amdgpu_fpriv *fpriv = filp->driver_priv; 611 struct amdgpu_bo *abo; 612 struct amdgpu_bo_va *bo_va; 613 struct amdgpu_bo_list_entry vm_pd; 614 struct ttm_validate_buffer tv; 615 struct ww_acquire_ctx ticket; 616 struct list_head list, duplicates; 617 uint64_t va_flags; 618 uint64_t vm_size; 619 int r = 0; 620 621 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 622 dev_dbg(dev->dev, 623 "va_address 0x%LX is in reserved area 0x%LX\n", 624 args->va_address, AMDGPU_VA_RESERVED_SIZE); 625 return -EINVAL; 626 } 627 628 if (args->va_address >= AMDGPU_GMC_HOLE_START && 629 args->va_address < AMDGPU_GMC_HOLE_END) { 630 dev_dbg(dev->dev, 631 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 632 args->va_address, AMDGPU_GMC_HOLE_START, 633 AMDGPU_GMC_HOLE_END); 634 return -EINVAL; 635 } 636 637 args->va_address &= AMDGPU_GMC_HOLE_MASK; 638 639 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 640 vm_size -= AMDGPU_VA_RESERVED_SIZE; 641 if (args->va_address + args->map_size > vm_size) { 642 dev_dbg(dev->dev, 643 "va_address 0x%llx is in top reserved area 0x%llx\n", 644 args->va_address + args->map_size, vm_size); 645 return -EINVAL; 646 } 647 648 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 649 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 650 args->flags); 651 return -EINVAL; 652 } 653 654 switch (args->operation) { 655 case AMDGPU_VA_OP_MAP: 656 case AMDGPU_VA_OP_UNMAP: 657 case AMDGPU_VA_OP_CLEAR: 658 case AMDGPU_VA_OP_REPLACE: 659 break; 660 default: 661 dev_dbg(dev->dev, "unsupported operation %d\n", 662 args->operation); 663 return -EINVAL; 664 } 665 666 INIT_LIST_HEAD(&list); 667 INIT_LIST_HEAD(&duplicates); 668 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 669 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 670 gobj = drm_gem_object_lookup(filp, args->handle); 671 if (gobj == NULL) 672 return -ENOENT; 673 abo = gem_to_amdgpu_bo(gobj); 674 tv.bo = &abo->tbo; 675 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 676 tv.num_shared = 1; 677 else 678 tv.num_shared = 0; 679 list_add(&tv.head, &list); 680 } else { 681 gobj = NULL; 682 abo = NULL; 683 } 684 685 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 686 687 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 688 if (r) 689 goto error_unref; 690 691 if (abo) { 692 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 693 if (!bo_va) { 694 r = -ENOENT; 695 goto error_backoff; 696 } 697 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 698 bo_va = fpriv->prt_va; 699 } else { 700 bo_va = NULL; 701 } 702 703 switch (args->operation) { 704 case AMDGPU_VA_OP_MAP: 705 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 706 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 707 args->offset_in_bo, args->map_size, 708 va_flags); 709 break; 710 case AMDGPU_VA_OP_UNMAP: 711 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 712 break; 713 714 case AMDGPU_VA_OP_CLEAR: 715 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 716 args->va_address, 717 args->map_size); 718 break; 719 case AMDGPU_VA_OP_REPLACE: 720 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 721 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 722 args->offset_in_bo, args->map_size, 723 va_flags); 724 break; 725 default: 726 break; 727 } 728 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 729 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 730 args->operation); 731 732 error_backoff: 733 ttm_eu_backoff_reservation(&ticket, &list); 734 735 error_unref: 736 drm_gem_object_put(gobj); 737 return r; 738 } 739 740 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 741 struct drm_file *filp) 742 { 743 struct amdgpu_device *adev = drm_to_adev(dev); 744 struct drm_amdgpu_gem_op *args = data; 745 struct drm_gem_object *gobj; 746 struct amdgpu_vm_bo_base *base; 747 struct amdgpu_bo *robj; 748 int r; 749 750 gobj = drm_gem_object_lookup(filp, args->handle); 751 if (gobj == NULL) { 752 return -ENOENT; 753 } 754 robj = gem_to_amdgpu_bo(gobj); 755 756 r = amdgpu_bo_reserve(robj, false); 757 if (unlikely(r)) 758 goto out; 759 760 switch (args->op) { 761 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 762 struct drm_amdgpu_gem_create_in info; 763 void __user *out = u64_to_user_ptr(args->value); 764 765 info.bo_size = robj->tbo.base.size; 766 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 767 info.domains = robj->preferred_domains; 768 info.domain_flags = robj->flags; 769 amdgpu_bo_unreserve(robj); 770 if (copy_to_user(out, &info, sizeof(info))) 771 r = -EFAULT; 772 break; 773 } 774 case AMDGPU_GEM_OP_SET_PLACEMENT: 775 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 776 r = -EINVAL; 777 amdgpu_bo_unreserve(robj); 778 break; 779 } 780 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 781 r = -EPERM; 782 amdgpu_bo_unreserve(robj); 783 break; 784 } 785 for (base = robj->vm_bo; base; base = base->next) 786 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 787 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 788 r = -EINVAL; 789 amdgpu_bo_unreserve(robj); 790 goto out; 791 } 792 793 794 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 795 AMDGPU_GEM_DOMAIN_GTT | 796 AMDGPU_GEM_DOMAIN_CPU); 797 robj->allowed_domains = robj->preferred_domains; 798 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 799 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 800 801 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 802 amdgpu_vm_bo_invalidate(adev, robj, true); 803 804 amdgpu_bo_unreserve(robj); 805 break; 806 default: 807 amdgpu_bo_unreserve(robj); 808 r = -EINVAL; 809 } 810 811 out: 812 drm_gem_object_put(gobj); 813 return r; 814 } 815 816 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 817 struct drm_device *dev, 818 struct drm_mode_create_dumb *args) 819 { 820 struct amdgpu_device *adev = drm_to_adev(dev); 821 struct drm_gem_object *gobj; 822 uint32_t handle; 823 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 824 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 825 u32 domain; 826 int r; 827 828 /* 829 * The buffer returned from this function should be cleared, but 830 * it can only be done if the ring is enabled or we'll fail to 831 * create the buffer. 832 */ 833 if (adev->mman.buffer_funcs_enabled) 834 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 835 836 args->pitch = amdgpu_align_pitch(adev, args->width, 837 DIV_ROUND_UP(args->bpp, 8), 0); 838 args->size = (u64)args->pitch * args->height; 839 args->size = ALIGN(args->size, PAGE_SIZE); 840 domain = amdgpu_bo_get_preferred_pin_domain(adev, 841 amdgpu_display_supported_domains(adev, flags)); 842 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 843 ttm_bo_type_device, NULL, &gobj); 844 if (r) 845 return -ENOMEM; 846 847 r = drm_gem_handle_create(file_priv, gobj, &handle); 848 /* drop reference from allocate - handle holds it now */ 849 drm_gem_object_put(gobj); 850 if (r) { 851 return r; 852 } 853 args->handle = handle; 854 return 0; 855 } 856 857 #if defined(CONFIG_DEBUG_FS) 858 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 859 { 860 struct drm_info_node *node = (struct drm_info_node *)m->private; 861 struct drm_device *dev = node->minor->dev; 862 struct drm_file *file; 863 int r; 864 865 r = mutex_lock_interruptible(&dev->filelist_mutex); 866 if (r) 867 return r; 868 869 list_for_each_entry(file, &dev->filelist, lhead) { 870 struct task_struct *task; 871 struct drm_gem_object *gobj; 872 int id; 873 874 /* 875 * Although we have a valid reference on file->pid, that does 876 * not guarantee that the task_struct who called get_pid() is 877 * still alive (e.g. get_pid(current) => fork() => exit()). 878 * Therefore, we need to protect this ->comm access using RCU. 879 */ 880 rcu_read_lock(); 881 task = pid_task(file->pid, PIDTYPE_PID); 882 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 883 task ? task->comm : "<unknown>"); 884 rcu_read_unlock(); 885 886 spin_lock(&file->table_lock); 887 idr_for_each_entry(&file->object_idr, gobj, id) { 888 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 889 890 amdgpu_bo_print_info(id, bo, m); 891 } 892 spin_unlock(&file->table_lock); 893 } 894 895 mutex_unlock(&dev->filelist_mutex); 896 return 0; 897 } 898 899 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 900 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 901 }; 902 #endif 903 904 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 905 { 906 #if defined(CONFIG_DEBUG_FS) 907 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 908 ARRAY_SIZE(amdgpu_debugfs_gem_list)); 909 #endif 910 return 0; 911 } 912