1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <drm/drmP.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 33 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 34 { 35 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 36 37 if (robj) { 38 if (robj->gem_base.import_attach) 39 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 40 amdgpu_mn_unregister(robj); 41 amdgpu_bo_unref(&robj); 42 } 43 } 44 45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 46 int alignment, u32 initial_domain, 47 u64 flags, bool kernel, 48 struct drm_gem_object **obj) 49 { 50 struct amdgpu_bo *robj; 51 unsigned long max_size; 52 int r; 53 54 *obj = NULL; 55 /* At least align on page size */ 56 if (alignment < PAGE_SIZE) { 57 alignment = PAGE_SIZE; 58 } 59 60 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { 61 /* Maximum bo size is the unpinned gtt size since we use the gtt to 62 * handle vram to system pool migrations. 63 */ 64 max_size = adev->mc.gtt_size - adev->gart_pin_size; 65 if (size > max_size) { 66 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", 67 size >> 20, max_size >> 20); 68 return -ENOMEM; 69 } 70 } 71 retry: 72 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, 73 flags, NULL, NULL, &robj); 74 if (r) { 75 if (r != -ERESTARTSYS) { 76 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 77 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 78 goto retry; 79 } 80 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 81 size, initial_domain, alignment, r); 82 } 83 return r; 84 } 85 *obj = &robj->gem_base; 86 robj->pid = task_pid_nr(current); 87 88 mutex_lock(&adev->gem.mutex); 89 list_add_tail(&robj->list, &adev->gem.objects); 90 mutex_unlock(&adev->gem.mutex); 91 92 return 0; 93 } 94 95 int amdgpu_gem_init(struct amdgpu_device *adev) 96 { 97 INIT_LIST_HEAD(&adev->gem.objects); 98 return 0; 99 } 100 101 void amdgpu_gem_fini(struct amdgpu_device *adev) 102 { 103 amdgpu_bo_force_delete(adev); 104 } 105 106 /* 107 * Call from drm_gem_handle_create which appear in both new and open ioctl 108 * case. 109 */ 110 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) 111 { 112 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); 113 struct amdgpu_device *adev = rbo->adev; 114 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 115 struct amdgpu_vm *vm = &fpriv->vm; 116 struct amdgpu_bo_va *bo_va; 117 int r; 118 119 r = amdgpu_bo_reserve(rbo, false); 120 if (r) { 121 return r; 122 } 123 124 bo_va = amdgpu_vm_bo_find(vm, rbo); 125 if (!bo_va) { 126 bo_va = amdgpu_vm_bo_add(adev, vm, rbo); 127 } else { 128 ++bo_va->ref_count; 129 } 130 amdgpu_bo_unreserve(rbo); 131 132 return 0; 133 } 134 135 void amdgpu_gem_object_close(struct drm_gem_object *obj, 136 struct drm_file *file_priv) 137 { 138 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); 139 struct amdgpu_device *adev = rbo->adev; 140 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 141 struct amdgpu_vm *vm = &fpriv->vm; 142 struct amdgpu_bo_va *bo_va; 143 int r; 144 145 r = amdgpu_bo_reserve(rbo, true); 146 if (r) { 147 dev_err(adev->dev, "leaking bo va because " 148 "we fail to reserve bo (%d)\n", r); 149 return; 150 } 151 bo_va = amdgpu_vm_bo_find(vm, rbo); 152 if (bo_va) { 153 if (--bo_va->ref_count == 0) { 154 amdgpu_vm_bo_rmv(adev, bo_va); 155 } 156 } 157 amdgpu_bo_unreserve(rbo); 158 } 159 160 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) 161 { 162 if (r == -EDEADLK) { 163 r = amdgpu_gpu_reset(adev); 164 if (!r) 165 r = -EAGAIN; 166 } 167 return r; 168 } 169 170 /* 171 * GEM ioctls. 172 */ 173 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 174 struct drm_file *filp) 175 { 176 struct amdgpu_device *adev = dev->dev_private; 177 union drm_amdgpu_gem_create *args = data; 178 uint64_t size = args->in.bo_size; 179 struct drm_gem_object *gobj; 180 uint32_t handle; 181 bool kernel = false; 182 int r; 183 184 down_read(&adev->exclusive_lock); 185 /* create a gem object to contain this object in */ 186 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 187 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 188 kernel = true; 189 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 190 size = size << AMDGPU_GDS_SHIFT; 191 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 192 size = size << AMDGPU_GWS_SHIFT; 193 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 194 size = size << AMDGPU_OA_SHIFT; 195 else { 196 r = -EINVAL; 197 goto error_unlock; 198 } 199 } 200 size = roundup(size, PAGE_SIZE); 201 202 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 203 (u32)(0xffffffff & args->in.domains), 204 args->in.domain_flags, 205 kernel, &gobj); 206 if (r) 207 goto error_unlock; 208 209 r = drm_gem_handle_create(filp, gobj, &handle); 210 /* drop reference from allocate - handle holds it now */ 211 drm_gem_object_unreference_unlocked(gobj); 212 if (r) 213 goto error_unlock; 214 215 memset(args, 0, sizeof(*args)); 216 args->out.handle = handle; 217 up_read(&adev->exclusive_lock); 218 return 0; 219 220 error_unlock: 221 up_read(&adev->exclusive_lock); 222 r = amdgpu_gem_handle_lockup(adev, r); 223 return r; 224 } 225 226 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 227 struct drm_file *filp) 228 { 229 struct amdgpu_device *adev = dev->dev_private; 230 struct drm_amdgpu_gem_userptr *args = data; 231 struct drm_gem_object *gobj; 232 struct amdgpu_bo *bo; 233 uint32_t handle; 234 int r; 235 236 if (offset_in_page(args->addr | args->size)) 237 return -EINVAL; 238 239 /* reject unknown flag values */ 240 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 241 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 242 AMDGPU_GEM_USERPTR_REGISTER)) 243 return -EINVAL; 244 245 if (!(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || 246 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 247 248 /* if we want to write to it we must require anonymous 249 memory and install a MMU notifier */ 250 return -EACCES; 251 } 252 253 down_read(&adev->exclusive_lock); 254 255 /* create a gem object to contain this object in */ 256 r = amdgpu_gem_object_create(adev, args->size, 0, 257 AMDGPU_GEM_DOMAIN_CPU, 0, 258 0, &gobj); 259 if (r) 260 goto handle_lockup; 261 262 bo = gem_to_amdgpu_bo(gobj); 263 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 264 if (r) 265 goto release_object; 266 267 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 268 r = amdgpu_mn_register(bo, args->addr); 269 if (r) 270 goto release_object; 271 } 272 273 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 274 down_read(¤t->mm->mmap_sem); 275 r = amdgpu_bo_reserve(bo, true); 276 if (r) { 277 up_read(¤t->mm->mmap_sem); 278 goto release_object; 279 } 280 281 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 282 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 283 amdgpu_bo_unreserve(bo); 284 up_read(¤t->mm->mmap_sem); 285 if (r) 286 goto release_object; 287 } 288 289 r = drm_gem_handle_create(filp, gobj, &handle); 290 /* drop reference from allocate - handle holds it now */ 291 drm_gem_object_unreference_unlocked(gobj); 292 if (r) 293 goto handle_lockup; 294 295 args->handle = handle; 296 up_read(&adev->exclusive_lock); 297 return 0; 298 299 release_object: 300 drm_gem_object_unreference_unlocked(gobj); 301 302 handle_lockup: 303 up_read(&adev->exclusive_lock); 304 r = amdgpu_gem_handle_lockup(adev, r); 305 306 return r; 307 } 308 309 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 310 struct drm_device *dev, 311 uint32_t handle, uint64_t *offset_p) 312 { 313 struct drm_gem_object *gobj; 314 struct amdgpu_bo *robj; 315 316 gobj = drm_gem_object_lookup(dev, filp, handle); 317 if (gobj == NULL) { 318 return -ENOENT; 319 } 320 robj = gem_to_amdgpu_bo(gobj); 321 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) || 322 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 323 drm_gem_object_unreference_unlocked(gobj); 324 return -EPERM; 325 } 326 *offset_p = amdgpu_bo_mmap_offset(robj); 327 drm_gem_object_unreference_unlocked(gobj); 328 return 0; 329 } 330 331 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 332 struct drm_file *filp) 333 { 334 union drm_amdgpu_gem_mmap *args = data; 335 uint32_t handle = args->in.handle; 336 memset(args, 0, sizeof(*args)); 337 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 338 } 339 340 /** 341 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 342 * 343 * @timeout_ns: timeout in ns 344 * 345 * Calculate the timeout in jiffies from an absolute timeout in ns. 346 */ 347 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 348 { 349 unsigned long timeout_jiffies; 350 ktime_t timeout; 351 352 /* clamp timeout if it's to large */ 353 if (((int64_t)timeout_ns) < 0) 354 return MAX_SCHEDULE_TIMEOUT; 355 356 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 357 if (ktime_to_ns(timeout) < 0) 358 return 0; 359 360 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 361 /* clamp timeout to avoid unsigned-> signed overflow */ 362 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 363 return MAX_SCHEDULE_TIMEOUT - 1; 364 365 return timeout_jiffies; 366 } 367 368 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 369 struct drm_file *filp) 370 { 371 struct amdgpu_device *adev = dev->dev_private; 372 union drm_amdgpu_gem_wait_idle *args = data; 373 struct drm_gem_object *gobj; 374 struct amdgpu_bo *robj; 375 uint32_t handle = args->in.handle; 376 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 377 int r = 0; 378 long ret; 379 380 gobj = drm_gem_object_lookup(dev, filp, handle); 381 if (gobj == NULL) { 382 return -ENOENT; 383 } 384 robj = gem_to_amdgpu_bo(gobj); 385 if (timeout == 0) 386 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); 387 else 388 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); 389 390 /* ret == 0 means not signaled, 391 * ret > 0 means signaled 392 * ret < 0 means interrupted before timeout 393 */ 394 if (ret >= 0) { 395 memset(args, 0, sizeof(*args)); 396 args->out.status = (ret == 0); 397 } else 398 r = ret; 399 400 drm_gem_object_unreference_unlocked(gobj); 401 r = amdgpu_gem_handle_lockup(adev, r); 402 return r; 403 } 404 405 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 406 struct drm_file *filp) 407 { 408 struct drm_amdgpu_gem_metadata *args = data; 409 struct drm_gem_object *gobj; 410 struct amdgpu_bo *robj; 411 int r = -1; 412 413 DRM_DEBUG("%d \n", args->handle); 414 gobj = drm_gem_object_lookup(dev, filp, args->handle); 415 if (gobj == NULL) 416 return -ENOENT; 417 robj = gem_to_amdgpu_bo(gobj); 418 419 r = amdgpu_bo_reserve(robj, false); 420 if (unlikely(r != 0)) 421 goto out; 422 423 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 424 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 425 r = amdgpu_bo_get_metadata(robj, args->data.data, 426 sizeof(args->data.data), 427 &args->data.data_size_bytes, 428 &args->data.flags); 429 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 430 if (args->data.data_size_bytes > sizeof(args->data.data)) { 431 r = -EINVAL; 432 goto unreserve; 433 } 434 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 435 if (!r) 436 r = amdgpu_bo_set_metadata(robj, args->data.data, 437 args->data.data_size_bytes, 438 args->data.flags); 439 } 440 441 unreserve: 442 amdgpu_bo_unreserve(robj); 443 out: 444 drm_gem_object_unreference_unlocked(gobj); 445 return r; 446 } 447 448 /** 449 * amdgpu_gem_va_update_vm -update the bo_va in its VM 450 * 451 * @adev: amdgpu_device pointer 452 * @bo_va: bo_va to update 453 * 454 * Update the bo_va directly after setting it's address. Errors are not 455 * vital here, so they are not reported back to userspace. 456 */ 457 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 458 struct amdgpu_bo_va *bo_va, uint32_t operation) 459 { 460 struct ttm_validate_buffer tv, *entry; 461 struct amdgpu_bo_list_entry *vm_bos; 462 struct ww_acquire_ctx ticket; 463 struct list_head list, duplicates; 464 unsigned domain; 465 int r; 466 467 INIT_LIST_HEAD(&list); 468 INIT_LIST_HEAD(&duplicates); 469 470 tv.bo = &bo_va->bo->tbo; 471 tv.shared = true; 472 list_add(&tv.head, &list); 473 474 vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list); 475 if (!vm_bos) 476 return; 477 478 /* Provide duplicates to avoid -EALREADY */ 479 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 480 if (r) 481 goto error_free; 482 483 list_for_each_entry(entry, &list, head) { 484 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); 485 /* if anything is swapped out don't swap it in here, 486 just abort and wait for the next CS */ 487 if (domain == AMDGPU_GEM_DOMAIN_CPU) 488 goto error_unreserve; 489 } 490 491 mutex_lock(&bo_va->vm->mutex); 492 r = amdgpu_vm_clear_freed(adev, bo_va->vm); 493 if (r) 494 goto error_unlock; 495 496 497 if (operation == AMDGPU_VA_OP_MAP) 498 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); 499 500 error_unlock: 501 mutex_unlock(&bo_va->vm->mutex); 502 503 error_unreserve: 504 ttm_eu_backoff_reservation(&ticket, &list); 505 506 error_free: 507 drm_free_large(vm_bos); 508 509 if (r && r != -ERESTARTSYS) 510 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 511 } 512 513 514 515 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 516 struct drm_file *filp) 517 { 518 struct drm_amdgpu_gem_va *args = data; 519 struct drm_gem_object *gobj; 520 struct amdgpu_device *adev = dev->dev_private; 521 struct amdgpu_fpriv *fpriv = filp->driver_priv; 522 struct amdgpu_bo *rbo; 523 struct amdgpu_bo_va *bo_va; 524 uint32_t invalid_flags, va_flags = 0; 525 int r = 0; 526 527 if (!adev->vm_manager.enabled) 528 return -ENOTTY; 529 530 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 531 dev_err(&dev->pdev->dev, 532 "va_address 0x%lX is in reserved area 0x%X\n", 533 (unsigned long)args->va_address, 534 AMDGPU_VA_RESERVED_SIZE); 535 return -EINVAL; 536 } 537 538 invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE | 539 AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); 540 if ((args->flags & invalid_flags)) { 541 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", 542 args->flags, invalid_flags); 543 return -EINVAL; 544 } 545 546 switch (args->operation) { 547 case AMDGPU_VA_OP_MAP: 548 case AMDGPU_VA_OP_UNMAP: 549 break; 550 default: 551 dev_err(&dev->pdev->dev, "unsupported operation %d\n", 552 args->operation); 553 return -EINVAL; 554 } 555 556 gobj = drm_gem_object_lookup(dev, filp, args->handle); 557 if (gobj == NULL) 558 return -ENOENT; 559 560 rbo = gem_to_amdgpu_bo(gobj); 561 r = amdgpu_bo_reserve(rbo, false); 562 if (r) { 563 drm_gem_object_unreference_unlocked(gobj); 564 return r; 565 } 566 567 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 568 if (!bo_va) { 569 amdgpu_bo_unreserve(rbo); 570 return -ENOENT; 571 } 572 573 switch (args->operation) { 574 case AMDGPU_VA_OP_MAP: 575 if (args->flags & AMDGPU_VM_PAGE_READABLE) 576 va_flags |= AMDGPU_PTE_READABLE; 577 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) 578 va_flags |= AMDGPU_PTE_WRITEABLE; 579 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) 580 va_flags |= AMDGPU_PTE_EXECUTABLE; 581 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 582 args->offset_in_bo, args->map_size, 583 va_flags); 584 break; 585 case AMDGPU_VA_OP_UNMAP: 586 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 587 break; 588 default: 589 break; 590 } 591 592 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 593 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 594 595 drm_gem_object_unreference_unlocked(gobj); 596 return r; 597 } 598 599 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 600 struct drm_file *filp) 601 { 602 struct drm_amdgpu_gem_op *args = data; 603 struct drm_gem_object *gobj; 604 struct amdgpu_bo *robj; 605 int r; 606 607 gobj = drm_gem_object_lookup(dev, filp, args->handle); 608 if (gobj == NULL) { 609 return -ENOENT; 610 } 611 robj = gem_to_amdgpu_bo(gobj); 612 613 r = amdgpu_bo_reserve(robj, false); 614 if (unlikely(r)) 615 goto out; 616 617 switch (args->op) { 618 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 619 struct drm_amdgpu_gem_create_in info; 620 void __user *out = (void __user *)(long)args->value; 621 622 info.bo_size = robj->gem_base.size; 623 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 624 info.domains = robj->initial_domain; 625 info.domain_flags = robj->flags; 626 amdgpu_bo_unreserve(robj); 627 if (copy_to_user(out, &info, sizeof(info))) 628 r = -EFAULT; 629 break; 630 } 631 case AMDGPU_GEM_OP_SET_PLACEMENT: 632 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { 633 r = -EPERM; 634 amdgpu_bo_unreserve(robj); 635 break; 636 } 637 robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 638 AMDGPU_GEM_DOMAIN_GTT | 639 AMDGPU_GEM_DOMAIN_CPU); 640 amdgpu_bo_unreserve(robj); 641 break; 642 default: 643 amdgpu_bo_unreserve(robj); 644 r = -EINVAL; 645 } 646 647 out: 648 drm_gem_object_unreference_unlocked(gobj); 649 return r; 650 } 651 652 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 653 struct drm_device *dev, 654 struct drm_mode_create_dumb *args) 655 { 656 struct amdgpu_device *adev = dev->dev_private; 657 struct drm_gem_object *gobj; 658 uint32_t handle; 659 int r; 660 661 args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); 662 args->size = (u64)args->pitch * args->height; 663 args->size = ALIGN(args->size, PAGE_SIZE); 664 665 r = amdgpu_gem_object_create(adev, args->size, 0, 666 AMDGPU_GEM_DOMAIN_VRAM, 667 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 668 ttm_bo_type_device, 669 &gobj); 670 if (r) 671 return -ENOMEM; 672 673 r = drm_gem_handle_create(file_priv, gobj, &handle); 674 /* drop reference from allocate - handle holds it now */ 675 drm_gem_object_unreference_unlocked(gobj); 676 if (r) { 677 return r; 678 } 679 args->handle = handle; 680 return 0; 681 } 682 683 #if defined(CONFIG_DEBUG_FS) 684 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 685 { 686 struct drm_info_node *node = (struct drm_info_node *)m->private; 687 struct drm_device *dev = node->minor->dev; 688 struct amdgpu_device *adev = dev->dev_private; 689 struct amdgpu_bo *rbo; 690 unsigned i = 0; 691 692 mutex_lock(&adev->gem.mutex); 693 list_for_each_entry(rbo, &adev->gem.objects, list) { 694 unsigned domain; 695 const char *placement; 696 697 domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type); 698 switch (domain) { 699 case AMDGPU_GEM_DOMAIN_VRAM: 700 placement = "VRAM"; 701 break; 702 case AMDGPU_GEM_DOMAIN_GTT: 703 placement = " GTT"; 704 break; 705 case AMDGPU_GEM_DOMAIN_CPU: 706 default: 707 placement = " CPU"; 708 break; 709 } 710 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", 711 i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20, 712 placement, (unsigned long)rbo->pid); 713 i++; 714 } 715 mutex_unlock(&adev->gem.mutex); 716 return 0; 717 } 718 719 static struct drm_info_list amdgpu_debugfs_gem_list[] = { 720 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 721 }; 722 #endif 723 724 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) 725 { 726 #if defined(CONFIG_DEBUG_FS) 727 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 728 #endif 729 return 0; 730 } 731