1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_gem_ttm_helper.h> 37 38 #include "amdgpu.h" 39 #include "amdgpu_display.h" 40 #include "amdgpu_dma_buf.h" 41 #include "amdgpu_xgmi.h" 42 43 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; 44 45 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) 46 { 47 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 48 struct drm_device *ddev = bo->base.dev; 49 vm_fault_t ret; 50 int idx; 51 52 ret = ttm_bo_vm_reserve(bo, vmf); 53 if (ret) 54 return ret; 55 56 if (drm_dev_enter(ddev, &idx)) { 57 ret = amdgpu_bo_fault_reserve_notify(bo); 58 if (ret) { 59 drm_dev_exit(idx); 60 goto unlock; 61 } 62 63 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 64 TTM_BO_VM_NUM_PREFAULT, 1); 65 drm_dev_exit(idx); 66 } else { 67 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); 68 } 69 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 70 return ret; 71 72 unlock: 73 dma_resv_unlock(bo->base.resv); 74 return ret; 75 } 76 77 static const struct vm_operations_struct amdgpu_gem_vm_ops = { 78 .fault = amdgpu_gem_fault, 79 .open = ttm_bo_vm_open, 80 .close = ttm_bo_vm_close, 81 .access = ttm_bo_vm_access 82 }; 83 84 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 85 { 86 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 87 88 if (robj) { 89 amdgpu_mn_unregister(robj); 90 amdgpu_bo_unref(&robj); 91 } 92 } 93 94 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 95 int alignment, u32 initial_domain, 96 u64 flags, enum ttm_bo_type type, 97 struct dma_resv *resv, 98 struct drm_gem_object **obj) 99 { 100 struct amdgpu_bo *bo; 101 struct amdgpu_bo_user *ubo; 102 struct amdgpu_bo_param bp; 103 int r; 104 105 memset(&bp, 0, sizeof(bp)); 106 *obj = NULL; 107 108 bp.size = size; 109 bp.byte_align = alignment; 110 bp.type = type; 111 bp.resv = resv; 112 bp.preferred_domain = initial_domain; 113 bp.flags = flags; 114 bp.domain = initial_domain; 115 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 116 117 r = amdgpu_bo_create_user(adev, &bp, &ubo); 118 if (r) 119 return r; 120 121 bo = &ubo->bo; 122 *obj = &bo->tbo.base; 123 (*obj)->funcs = &amdgpu_gem_object_funcs; 124 125 return 0; 126 } 127 128 void amdgpu_gem_force_release(struct amdgpu_device *adev) 129 { 130 struct drm_device *ddev = adev_to_drm(adev); 131 struct drm_file *file; 132 133 mutex_lock(&ddev->filelist_mutex); 134 135 list_for_each_entry(file, &ddev->filelist, lhead) { 136 struct drm_gem_object *gobj; 137 int handle; 138 139 WARN_ONCE(1, "Still active user space clients!\n"); 140 spin_lock(&file->table_lock); 141 idr_for_each_entry(&file->object_idr, gobj, handle) { 142 WARN_ONCE(1, "And also active allocations!\n"); 143 drm_gem_object_put(gobj); 144 } 145 idr_destroy(&file->object_idr); 146 spin_unlock(&file->table_lock); 147 } 148 149 mutex_unlock(&ddev->filelist_mutex); 150 } 151 152 /* 153 * Call from drm_gem_handle_create which appear in both new and open ioctl 154 * case. 155 */ 156 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 157 struct drm_file *file_priv) 158 { 159 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 160 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 161 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 162 struct amdgpu_vm *vm = &fpriv->vm; 163 struct amdgpu_bo_va *bo_va; 164 struct mm_struct *mm; 165 int r; 166 167 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 168 if (mm && mm != current->mm) 169 return -EPERM; 170 171 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 172 abo->tbo.base.resv != vm->root.bo->tbo.base.resv) 173 return -EPERM; 174 175 r = amdgpu_bo_reserve(abo, false); 176 if (r) 177 return r; 178 179 bo_va = amdgpu_vm_bo_find(vm, abo); 180 if (!bo_va) { 181 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 182 } else { 183 ++bo_va->ref_count; 184 } 185 amdgpu_bo_unreserve(abo); 186 return 0; 187 } 188 189 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 190 struct drm_file *file_priv) 191 { 192 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 193 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 194 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 195 struct amdgpu_vm *vm = &fpriv->vm; 196 197 struct amdgpu_bo_list_entry vm_pd; 198 struct list_head list, duplicates; 199 struct dma_fence *fence = NULL; 200 struct ttm_validate_buffer tv; 201 struct ww_acquire_ctx ticket; 202 struct amdgpu_bo_va *bo_va; 203 long r; 204 205 INIT_LIST_HEAD(&list); 206 INIT_LIST_HEAD(&duplicates); 207 208 tv.bo = &bo->tbo; 209 tv.num_shared = 2; 210 list_add(&tv.head, &list); 211 212 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 213 214 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 215 if (r) { 216 dev_err(adev->dev, "leaking bo va because " 217 "we fail to reserve bo (%ld)\n", r); 218 return; 219 } 220 bo_va = amdgpu_vm_bo_find(vm, bo); 221 if (!bo_va || --bo_va->ref_count) 222 goto out_unlock; 223 224 amdgpu_vm_bo_rmv(adev, bo_va); 225 if (!amdgpu_vm_ready(vm)) 226 goto out_unlock; 227 228 fence = dma_resv_excl_fence(bo->tbo.base.resv); 229 if (fence) { 230 amdgpu_bo_fence(bo, fence, true); 231 fence = NULL; 232 } 233 234 r = amdgpu_vm_clear_freed(adev, vm, &fence); 235 if (r || !fence) 236 goto out_unlock; 237 238 amdgpu_bo_fence(bo, fence, true); 239 dma_fence_put(fence); 240 241 out_unlock: 242 if (unlikely(r < 0)) 243 dev_err(adev->dev, "failed to clear page " 244 "tables on GEM object close (%ld)\n", r); 245 ttm_eu_backoff_reservation(&ticket, &list); 246 } 247 248 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) 249 { 250 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 251 252 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 253 return -EPERM; 254 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 255 return -EPERM; 256 257 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings 258 * for debugger access to invisible VRAM. Should have used MAP_SHARED 259 * instead. Clearing VM_MAYWRITE prevents the mapping from ever 260 * becoming writable and makes is_cow_mapping(vm_flags) false. 261 */ 262 if (is_cow_mapping(vma->vm_flags) && 263 !(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC))) 264 vma->vm_flags &= ~VM_MAYWRITE; 265 266 return drm_gem_ttm_mmap(obj, vma); 267 } 268 269 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 270 .free = amdgpu_gem_object_free, 271 .open = amdgpu_gem_object_open, 272 .close = amdgpu_gem_object_close, 273 .export = amdgpu_gem_prime_export, 274 .vmap = drm_gem_ttm_vmap, 275 .vunmap = drm_gem_ttm_vunmap, 276 .mmap = amdgpu_gem_object_mmap, 277 .vm_ops = &amdgpu_gem_vm_ops, 278 }; 279 280 /* 281 * GEM ioctls. 282 */ 283 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 284 struct drm_file *filp) 285 { 286 struct amdgpu_device *adev = drm_to_adev(dev); 287 struct amdgpu_fpriv *fpriv = filp->driver_priv; 288 struct amdgpu_vm *vm = &fpriv->vm; 289 union drm_amdgpu_gem_create *args = data; 290 uint64_t flags = args->in.domain_flags; 291 uint64_t size = args->in.bo_size; 292 struct dma_resv *resv = NULL; 293 struct drm_gem_object *gobj; 294 uint32_t handle, initial_domain; 295 int r; 296 297 /* reject invalid gem flags */ 298 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 299 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 300 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 301 AMDGPU_GEM_CREATE_VRAM_CLEARED | 302 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 303 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 304 AMDGPU_GEM_CREATE_ENCRYPTED)) 305 306 return -EINVAL; 307 308 /* reject invalid gem domains */ 309 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 310 return -EINVAL; 311 312 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 313 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 314 return -EINVAL; 315 } 316 317 /* create a gem object to contain this object in */ 318 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 319 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 320 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 321 /* if gds bo is created from user space, it must be 322 * passed to bo list 323 */ 324 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 325 return -EINVAL; 326 } 327 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 328 } 329 330 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 331 r = amdgpu_bo_reserve(vm->root.bo, false); 332 if (r) 333 return r; 334 335 resv = vm->root.bo->tbo.base.resv; 336 } 337 338 initial_domain = (u32)(0xffffffff & args->in.domains); 339 retry: 340 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 341 initial_domain, 342 flags, ttm_bo_type_device, resv, &gobj); 343 if (r && r != -ERESTARTSYS) { 344 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 345 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 346 goto retry; 347 } 348 349 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 350 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 351 goto retry; 352 } 353 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 354 size, initial_domain, args->in.alignment, r); 355 } 356 357 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 358 if (!r) { 359 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 360 361 abo->parent = amdgpu_bo_ref(vm->root.bo); 362 } 363 amdgpu_bo_unreserve(vm->root.bo); 364 } 365 if (r) 366 return r; 367 368 r = drm_gem_handle_create(filp, gobj, &handle); 369 /* drop reference from allocate - handle holds it now */ 370 drm_gem_object_put(gobj); 371 if (r) 372 return r; 373 374 memset(args, 0, sizeof(*args)); 375 args->out.handle = handle; 376 return 0; 377 } 378 379 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 380 struct drm_file *filp) 381 { 382 struct ttm_operation_ctx ctx = { true, false }; 383 struct amdgpu_device *adev = drm_to_adev(dev); 384 struct drm_amdgpu_gem_userptr *args = data; 385 struct drm_gem_object *gobj; 386 struct amdgpu_bo *bo; 387 uint32_t handle; 388 int r; 389 390 args->addr = untagged_addr(args->addr); 391 392 if (offset_in_page(args->addr | args->size)) 393 return -EINVAL; 394 395 /* reject unknown flag values */ 396 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 397 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 398 AMDGPU_GEM_USERPTR_REGISTER)) 399 return -EINVAL; 400 401 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 402 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 403 404 /* if we want to write to it we must install a MMU notifier */ 405 return -EACCES; 406 } 407 408 /* create a gem object to contain this object in */ 409 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 410 0, ttm_bo_type_device, NULL, &gobj); 411 if (r) 412 return r; 413 414 bo = gem_to_amdgpu_bo(gobj); 415 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 416 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 417 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 418 if (r) 419 goto release_object; 420 421 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 422 r = amdgpu_mn_register(bo, args->addr); 423 if (r) 424 goto release_object; 425 } 426 427 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 428 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 429 if (r) 430 goto release_object; 431 432 r = amdgpu_bo_reserve(bo, true); 433 if (r) 434 goto user_pages_done; 435 436 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 437 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 438 amdgpu_bo_unreserve(bo); 439 if (r) 440 goto user_pages_done; 441 } 442 443 r = drm_gem_handle_create(filp, gobj, &handle); 444 if (r) 445 goto user_pages_done; 446 447 args->handle = handle; 448 449 user_pages_done: 450 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 451 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 452 453 release_object: 454 drm_gem_object_put(gobj); 455 456 return r; 457 } 458 459 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 460 struct drm_device *dev, 461 uint32_t handle, uint64_t *offset_p) 462 { 463 struct drm_gem_object *gobj; 464 struct amdgpu_bo *robj; 465 466 gobj = drm_gem_object_lookup(filp, handle); 467 if (gobj == NULL) { 468 return -ENOENT; 469 } 470 robj = gem_to_amdgpu_bo(gobj); 471 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 472 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 473 drm_gem_object_put(gobj); 474 return -EPERM; 475 } 476 *offset_p = amdgpu_bo_mmap_offset(robj); 477 drm_gem_object_put(gobj); 478 return 0; 479 } 480 481 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 482 struct drm_file *filp) 483 { 484 union drm_amdgpu_gem_mmap *args = data; 485 uint32_t handle = args->in.handle; 486 memset(args, 0, sizeof(*args)); 487 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 488 } 489 490 /** 491 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 492 * 493 * @timeout_ns: timeout in ns 494 * 495 * Calculate the timeout in jiffies from an absolute timeout in ns. 496 */ 497 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 498 { 499 unsigned long timeout_jiffies; 500 ktime_t timeout; 501 502 /* clamp timeout if it's to large */ 503 if (((int64_t)timeout_ns) < 0) 504 return MAX_SCHEDULE_TIMEOUT; 505 506 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 507 if (ktime_to_ns(timeout) < 0) 508 return 0; 509 510 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 511 /* clamp timeout to avoid unsigned-> signed overflow */ 512 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 513 return MAX_SCHEDULE_TIMEOUT - 1; 514 515 return timeout_jiffies; 516 } 517 518 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 519 struct drm_file *filp) 520 { 521 union drm_amdgpu_gem_wait_idle *args = data; 522 struct drm_gem_object *gobj; 523 struct amdgpu_bo *robj; 524 uint32_t handle = args->in.handle; 525 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 526 int r = 0; 527 long ret; 528 529 gobj = drm_gem_object_lookup(filp, handle); 530 if (gobj == NULL) { 531 return -ENOENT; 532 } 533 robj = gem_to_amdgpu_bo(gobj); 534 ret = dma_resv_wait_timeout(robj->tbo.base.resv, true, true, timeout); 535 536 /* ret == 0 means not signaled, 537 * ret > 0 means signaled 538 * ret < 0 means interrupted before timeout 539 */ 540 if (ret >= 0) { 541 memset(args, 0, sizeof(*args)); 542 args->out.status = (ret == 0); 543 } else 544 r = ret; 545 546 drm_gem_object_put(gobj); 547 return r; 548 } 549 550 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 551 struct drm_file *filp) 552 { 553 struct drm_amdgpu_gem_metadata *args = data; 554 struct drm_gem_object *gobj; 555 struct amdgpu_bo *robj; 556 int r = -1; 557 558 DRM_DEBUG("%d \n", args->handle); 559 gobj = drm_gem_object_lookup(filp, args->handle); 560 if (gobj == NULL) 561 return -ENOENT; 562 robj = gem_to_amdgpu_bo(gobj); 563 564 r = amdgpu_bo_reserve(robj, false); 565 if (unlikely(r != 0)) 566 goto out; 567 568 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 569 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 570 r = amdgpu_bo_get_metadata(robj, args->data.data, 571 sizeof(args->data.data), 572 &args->data.data_size_bytes, 573 &args->data.flags); 574 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 575 if (args->data.data_size_bytes > sizeof(args->data.data)) { 576 r = -EINVAL; 577 goto unreserve; 578 } 579 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 580 if (!r) 581 r = amdgpu_bo_set_metadata(robj, args->data.data, 582 args->data.data_size_bytes, 583 args->data.flags); 584 } 585 586 unreserve: 587 amdgpu_bo_unreserve(robj); 588 out: 589 drm_gem_object_put(gobj); 590 return r; 591 } 592 593 /** 594 * amdgpu_gem_va_update_vm -update the bo_va in its VM 595 * 596 * @adev: amdgpu_device pointer 597 * @vm: vm to update 598 * @bo_va: bo_va to update 599 * @operation: map, unmap or clear 600 * 601 * Update the bo_va directly after setting its address. Errors are not 602 * vital here, so they are not reported back to userspace. 603 */ 604 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 605 struct amdgpu_vm *vm, 606 struct amdgpu_bo_va *bo_va, 607 uint32_t operation) 608 { 609 int r; 610 611 if (!amdgpu_vm_ready(vm)) 612 return; 613 614 r = amdgpu_vm_clear_freed(adev, vm, NULL); 615 if (r) 616 goto error; 617 618 if (operation == AMDGPU_VA_OP_MAP || 619 operation == AMDGPU_VA_OP_REPLACE) { 620 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL); 621 if (r) 622 goto error; 623 } 624 625 r = amdgpu_vm_update_pdes(adev, vm, false); 626 627 error: 628 if (r && r != -ERESTARTSYS) 629 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 630 } 631 632 /** 633 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 634 * 635 * @adev: amdgpu_device pointer 636 * @flags: GEM UAPI flags 637 * 638 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 639 */ 640 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 641 { 642 uint64_t pte_flag = 0; 643 644 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 645 pte_flag |= AMDGPU_PTE_EXECUTABLE; 646 if (flags & AMDGPU_VM_PAGE_READABLE) 647 pte_flag |= AMDGPU_PTE_READABLE; 648 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 649 pte_flag |= AMDGPU_PTE_WRITEABLE; 650 if (flags & AMDGPU_VM_PAGE_PRT) 651 pte_flag |= AMDGPU_PTE_PRT; 652 653 if (adev->gmc.gmc_funcs->map_mtype) 654 pte_flag |= amdgpu_gmc_map_mtype(adev, 655 flags & AMDGPU_VM_MTYPE_MASK); 656 657 return pte_flag; 658 } 659 660 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 661 struct drm_file *filp) 662 { 663 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 664 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 665 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 666 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 667 AMDGPU_VM_PAGE_PRT; 668 669 struct drm_amdgpu_gem_va *args = data; 670 struct drm_gem_object *gobj; 671 struct amdgpu_device *adev = drm_to_adev(dev); 672 struct amdgpu_fpriv *fpriv = filp->driver_priv; 673 struct amdgpu_bo *abo; 674 struct amdgpu_bo_va *bo_va; 675 struct amdgpu_bo_list_entry vm_pd; 676 struct ttm_validate_buffer tv; 677 struct ww_acquire_ctx ticket; 678 struct list_head list, duplicates; 679 uint64_t va_flags; 680 uint64_t vm_size; 681 int r = 0; 682 683 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 684 dev_dbg(dev->dev, 685 "va_address 0x%LX is in reserved area 0x%LX\n", 686 args->va_address, AMDGPU_VA_RESERVED_SIZE); 687 return -EINVAL; 688 } 689 690 if (args->va_address >= AMDGPU_GMC_HOLE_START && 691 args->va_address < AMDGPU_GMC_HOLE_END) { 692 dev_dbg(dev->dev, 693 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 694 args->va_address, AMDGPU_GMC_HOLE_START, 695 AMDGPU_GMC_HOLE_END); 696 return -EINVAL; 697 } 698 699 args->va_address &= AMDGPU_GMC_HOLE_MASK; 700 701 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 702 vm_size -= AMDGPU_VA_RESERVED_SIZE; 703 if (args->va_address + args->map_size > vm_size) { 704 dev_dbg(dev->dev, 705 "va_address 0x%llx is in top reserved area 0x%llx\n", 706 args->va_address + args->map_size, vm_size); 707 return -EINVAL; 708 } 709 710 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 711 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 712 args->flags); 713 return -EINVAL; 714 } 715 716 switch (args->operation) { 717 case AMDGPU_VA_OP_MAP: 718 case AMDGPU_VA_OP_UNMAP: 719 case AMDGPU_VA_OP_CLEAR: 720 case AMDGPU_VA_OP_REPLACE: 721 break; 722 default: 723 dev_dbg(dev->dev, "unsupported operation %d\n", 724 args->operation); 725 return -EINVAL; 726 } 727 728 INIT_LIST_HEAD(&list); 729 INIT_LIST_HEAD(&duplicates); 730 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 731 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 732 gobj = drm_gem_object_lookup(filp, args->handle); 733 if (gobj == NULL) 734 return -ENOENT; 735 abo = gem_to_amdgpu_bo(gobj); 736 tv.bo = &abo->tbo; 737 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 738 tv.num_shared = 1; 739 else 740 tv.num_shared = 0; 741 list_add(&tv.head, &list); 742 } else { 743 gobj = NULL; 744 abo = NULL; 745 } 746 747 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 748 749 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 750 if (r) 751 goto error_unref; 752 753 if (abo) { 754 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 755 if (!bo_va) { 756 r = -ENOENT; 757 goto error_backoff; 758 } 759 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 760 bo_va = fpriv->prt_va; 761 } else { 762 bo_va = NULL; 763 } 764 765 switch (args->operation) { 766 case AMDGPU_VA_OP_MAP: 767 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 768 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 769 args->offset_in_bo, args->map_size, 770 va_flags); 771 break; 772 case AMDGPU_VA_OP_UNMAP: 773 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 774 break; 775 776 case AMDGPU_VA_OP_CLEAR: 777 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 778 args->va_address, 779 args->map_size); 780 break; 781 case AMDGPU_VA_OP_REPLACE: 782 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 783 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 784 args->offset_in_bo, args->map_size, 785 va_flags); 786 break; 787 default: 788 break; 789 } 790 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 791 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 792 args->operation); 793 794 error_backoff: 795 ttm_eu_backoff_reservation(&ticket, &list); 796 797 error_unref: 798 drm_gem_object_put(gobj); 799 return r; 800 } 801 802 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 803 struct drm_file *filp) 804 { 805 struct amdgpu_device *adev = drm_to_adev(dev); 806 struct drm_amdgpu_gem_op *args = data; 807 struct drm_gem_object *gobj; 808 struct amdgpu_vm_bo_base *base; 809 struct amdgpu_bo *robj; 810 int r; 811 812 gobj = drm_gem_object_lookup(filp, args->handle); 813 if (gobj == NULL) { 814 return -ENOENT; 815 } 816 robj = gem_to_amdgpu_bo(gobj); 817 818 r = amdgpu_bo_reserve(robj, false); 819 if (unlikely(r)) 820 goto out; 821 822 switch (args->op) { 823 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 824 struct drm_amdgpu_gem_create_in info; 825 void __user *out = u64_to_user_ptr(args->value); 826 827 info.bo_size = robj->tbo.base.size; 828 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; 829 info.domains = robj->preferred_domains; 830 info.domain_flags = robj->flags; 831 amdgpu_bo_unreserve(robj); 832 if (copy_to_user(out, &info, sizeof(info))) 833 r = -EFAULT; 834 break; 835 } 836 case AMDGPU_GEM_OP_SET_PLACEMENT: 837 if (robj->tbo.base.import_attach && 838 args->value & AMDGPU_GEM_DOMAIN_VRAM) { 839 r = -EINVAL; 840 amdgpu_bo_unreserve(robj); 841 break; 842 } 843 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 844 r = -EPERM; 845 amdgpu_bo_unreserve(robj); 846 break; 847 } 848 for (base = robj->vm_bo; base; base = base->next) 849 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 850 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { 851 r = -EINVAL; 852 amdgpu_bo_unreserve(robj); 853 goto out; 854 } 855 856 857 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 858 AMDGPU_GEM_DOMAIN_GTT | 859 AMDGPU_GEM_DOMAIN_CPU); 860 robj->allowed_domains = robj->preferred_domains; 861 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 862 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 863 864 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 865 amdgpu_vm_bo_invalidate(adev, robj, true); 866 867 amdgpu_bo_unreserve(robj); 868 break; 869 default: 870 amdgpu_bo_unreserve(robj); 871 r = -EINVAL; 872 } 873 874 out: 875 drm_gem_object_put(gobj); 876 return r; 877 } 878 879 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 880 struct drm_device *dev, 881 struct drm_mode_create_dumb *args) 882 { 883 struct amdgpu_device *adev = drm_to_adev(dev); 884 struct drm_gem_object *gobj; 885 uint32_t handle; 886 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 887 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 888 u32 domain; 889 int r; 890 891 /* 892 * The buffer returned from this function should be cleared, but 893 * it can only be done if the ring is enabled or we'll fail to 894 * create the buffer. 895 */ 896 if (adev->mman.buffer_funcs_enabled) 897 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 898 899 args->pitch = amdgpu_align_pitch(adev, args->width, 900 DIV_ROUND_UP(args->bpp, 8), 0); 901 args->size = (u64)args->pitch * args->height; 902 args->size = ALIGN(args->size, PAGE_SIZE); 903 domain = amdgpu_bo_get_preferred_domain(adev, 904 amdgpu_display_supported_domains(adev, flags)); 905 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 906 ttm_bo_type_device, NULL, &gobj); 907 if (r) 908 return -ENOMEM; 909 910 r = drm_gem_handle_create(file_priv, gobj, &handle); 911 /* drop reference from allocate - handle holds it now */ 912 drm_gem_object_put(gobj); 913 if (r) { 914 return r; 915 } 916 args->handle = handle; 917 return 0; 918 } 919 920 #if defined(CONFIG_DEBUG_FS) 921 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) 922 { 923 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 924 struct drm_device *dev = adev_to_drm(adev); 925 struct drm_file *file; 926 int r; 927 928 r = mutex_lock_interruptible(&dev->filelist_mutex); 929 if (r) 930 return r; 931 932 list_for_each_entry(file, &dev->filelist, lhead) { 933 struct task_struct *task; 934 struct drm_gem_object *gobj; 935 int id; 936 937 /* 938 * Although we have a valid reference on file->pid, that does 939 * not guarantee that the task_struct who called get_pid() is 940 * still alive (e.g. get_pid(current) => fork() => exit()). 941 * Therefore, we need to protect this ->comm access using RCU. 942 */ 943 rcu_read_lock(); 944 task = pid_task(file->pid, PIDTYPE_PID); 945 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 946 task ? task->comm : "<unknown>"); 947 rcu_read_unlock(); 948 949 spin_lock(&file->table_lock); 950 idr_for_each_entry(&file->object_idr, gobj, id) { 951 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 952 953 amdgpu_bo_print_info(id, bo, m); 954 } 955 spin_unlock(&file->table_lock); 956 } 957 958 mutex_unlock(&dev->filelist_mutex); 959 return 0; 960 } 961 962 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); 963 964 #endif 965 966 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 967 { 968 #if defined(CONFIG_DEBUG_FS) 969 struct drm_minor *minor = adev_to_drm(adev)->primary; 970 struct dentry *root = minor->debugfs_root; 971 972 debugfs_create_file("amdgpu_gem_info", 0444, root, adev, 973 &amdgpu_debugfs_gem_info_fops); 974 #endif 975 } 976