1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 34 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 35 { 36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 37 38 if (robj) { 39 if (robj->gem_base.import_attach) 40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 41 amdgpu_mn_unregister(robj); 42 amdgpu_bo_unref(&robj); 43 } 44 } 45 46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 47 int alignment, u32 initial_domain, 48 u64 flags, bool kernel, 49 struct reservation_object *resv, 50 struct drm_gem_object **obj) 51 { 52 struct amdgpu_bo *bo; 53 int r; 54 55 *obj = NULL; 56 /* At least align on page size */ 57 if (alignment < PAGE_SIZE) { 58 alignment = PAGE_SIZE; 59 } 60 61 retry: 62 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, 63 flags, NULL, resv, 0, &bo); 64 if (r) { 65 if (r != -ERESTARTSYS) { 66 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 67 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 68 goto retry; 69 } 70 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 71 size, initial_domain, alignment, r); 72 } 73 return r; 74 } 75 *obj = &bo->gem_base; 76 77 return 0; 78 } 79 80 void amdgpu_gem_force_release(struct amdgpu_device *adev) 81 { 82 struct drm_device *ddev = adev->ddev; 83 struct drm_file *file; 84 85 mutex_lock(&ddev->filelist_mutex); 86 87 list_for_each_entry(file, &ddev->filelist, lhead) { 88 struct drm_gem_object *gobj; 89 int handle; 90 91 WARN_ONCE(1, "Still active user space clients!\n"); 92 spin_lock(&file->table_lock); 93 idr_for_each_entry(&file->object_idr, gobj, handle) { 94 WARN_ONCE(1, "And also active allocations!\n"); 95 drm_gem_object_put_unlocked(gobj); 96 } 97 idr_destroy(&file->object_idr); 98 spin_unlock(&file->table_lock); 99 } 100 101 mutex_unlock(&ddev->filelist_mutex); 102 } 103 104 /* 105 * Call from drm_gem_handle_create which appear in both new and open ioctl 106 * case. 107 */ 108 int amdgpu_gem_object_open(struct drm_gem_object *obj, 109 struct drm_file *file_priv) 110 { 111 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 112 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 113 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 114 struct amdgpu_vm *vm = &fpriv->vm; 115 struct amdgpu_bo_va *bo_va; 116 struct mm_struct *mm; 117 int r; 118 119 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 120 if (mm && mm != current->mm) 121 return -EPERM; 122 123 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 124 abo->tbo.resv != vm->root.base.bo->tbo.resv) 125 return -EPERM; 126 127 r = amdgpu_bo_reserve(abo, false); 128 if (r) 129 return r; 130 131 bo_va = amdgpu_vm_bo_find(vm, abo); 132 if (!bo_va) { 133 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 134 } else { 135 ++bo_va->ref_count; 136 } 137 amdgpu_bo_unreserve(abo); 138 return 0; 139 } 140 141 void amdgpu_gem_object_close(struct drm_gem_object *obj, 142 struct drm_file *file_priv) 143 { 144 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 145 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 146 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 147 struct amdgpu_vm *vm = &fpriv->vm; 148 149 struct amdgpu_bo_list_entry vm_pd; 150 struct list_head list, duplicates; 151 struct ttm_validate_buffer tv; 152 struct ww_acquire_ctx ticket; 153 struct amdgpu_bo_va *bo_va; 154 int r; 155 156 INIT_LIST_HEAD(&list); 157 INIT_LIST_HEAD(&duplicates); 158 159 tv.bo = &bo->tbo; 160 tv.shared = true; 161 list_add(&tv.head, &list); 162 163 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 164 165 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 166 if (r) { 167 dev_err(adev->dev, "leaking bo va because " 168 "we fail to reserve bo (%d)\n", r); 169 return; 170 } 171 bo_va = amdgpu_vm_bo_find(vm, bo); 172 if (bo_va && --bo_va->ref_count == 0) { 173 amdgpu_vm_bo_rmv(adev, bo_va); 174 175 if (amdgpu_vm_ready(vm)) { 176 struct dma_fence *fence = NULL; 177 178 r = amdgpu_vm_clear_freed(adev, vm, &fence); 179 if (unlikely(r)) { 180 dev_err(adev->dev, "failed to clear page " 181 "tables on GEM object close (%d)\n", r); 182 } 183 184 if (fence) { 185 amdgpu_bo_fence(bo, fence, true); 186 dma_fence_put(fence); 187 } 188 } 189 } 190 ttm_eu_backoff_reservation(&ticket, &list); 191 } 192 193 /* 194 * GEM ioctls. 195 */ 196 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 197 struct drm_file *filp) 198 { 199 struct amdgpu_device *adev = dev->dev_private; 200 struct amdgpu_fpriv *fpriv = filp->driver_priv; 201 struct amdgpu_vm *vm = &fpriv->vm; 202 union drm_amdgpu_gem_create *args = data; 203 uint64_t flags = args->in.domain_flags; 204 uint64_t size = args->in.bo_size; 205 struct reservation_object *resv = NULL; 206 struct drm_gem_object *gobj; 207 uint32_t handle; 208 int r; 209 210 /* reject invalid gem flags */ 211 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 212 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 213 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 214 AMDGPU_GEM_CREATE_VRAM_CLEARED | 215 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)) 216 return -EINVAL; 217 218 /* reject invalid gem domains */ 219 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU | 220 AMDGPU_GEM_DOMAIN_GTT | 221 AMDGPU_GEM_DOMAIN_VRAM | 222 AMDGPU_GEM_DOMAIN_GDS | 223 AMDGPU_GEM_DOMAIN_GWS | 224 AMDGPU_GEM_DOMAIN_OA)) 225 return -EINVAL; 226 227 /* create a gem object to contain this object in */ 228 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 229 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 230 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 231 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 232 size = size << AMDGPU_GDS_SHIFT; 233 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 234 size = size << AMDGPU_GWS_SHIFT; 235 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 236 size = size << AMDGPU_OA_SHIFT; 237 else 238 return -EINVAL; 239 } 240 size = roundup(size, PAGE_SIZE); 241 242 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 243 r = amdgpu_bo_reserve(vm->root.base.bo, false); 244 if (r) 245 return r; 246 247 resv = vm->root.base.bo->tbo.resv; 248 } 249 250 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 251 (u32)(0xffffffff & args->in.domains), 252 flags, false, resv, &gobj); 253 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 254 if (!r) { 255 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 256 257 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 258 } 259 amdgpu_bo_unreserve(vm->root.base.bo); 260 } 261 if (r) 262 return r; 263 264 r = drm_gem_handle_create(filp, gobj, &handle); 265 /* drop reference from allocate - handle holds it now */ 266 drm_gem_object_put_unlocked(gobj); 267 if (r) 268 return r; 269 270 memset(args, 0, sizeof(*args)); 271 args->out.handle = handle; 272 return 0; 273 } 274 275 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 276 struct drm_file *filp) 277 { 278 struct amdgpu_device *adev = dev->dev_private; 279 struct drm_amdgpu_gem_userptr *args = data; 280 struct drm_gem_object *gobj; 281 struct amdgpu_bo *bo; 282 uint32_t handle; 283 int r; 284 285 if (offset_in_page(args->addr | args->size)) 286 return -EINVAL; 287 288 /* reject unknown flag values */ 289 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 290 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 291 AMDGPU_GEM_USERPTR_REGISTER)) 292 return -EINVAL; 293 294 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 295 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 296 297 /* if we want to write to it we must install a MMU notifier */ 298 return -EACCES; 299 } 300 301 /* create a gem object to contain this object in */ 302 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 303 0, 0, NULL, &gobj); 304 if (r) 305 return r; 306 307 bo = gem_to_amdgpu_bo(gobj); 308 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 309 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 310 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 311 if (r) 312 goto release_object; 313 314 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 315 r = amdgpu_mn_register(bo, args->addr); 316 if (r) 317 goto release_object; 318 } 319 320 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 321 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 322 bo->tbo.ttm->pages); 323 if (r) 324 goto unlock_mmap_sem; 325 326 r = amdgpu_bo_reserve(bo, true); 327 if (r) 328 goto free_pages; 329 330 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 331 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 332 amdgpu_bo_unreserve(bo); 333 if (r) 334 goto free_pages; 335 } 336 337 r = drm_gem_handle_create(filp, gobj, &handle); 338 /* drop reference from allocate - handle holds it now */ 339 drm_gem_object_put_unlocked(gobj); 340 if (r) 341 return r; 342 343 args->handle = handle; 344 return 0; 345 346 free_pages: 347 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false); 348 349 unlock_mmap_sem: 350 up_read(¤t->mm->mmap_sem); 351 352 release_object: 353 drm_gem_object_put_unlocked(gobj); 354 355 return r; 356 } 357 358 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 359 struct drm_device *dev, 360 uint32_t handle, uint64_t *offset_p) 361 { 362 struct drm_gem_object *gobj; 363 struct amdgpu_bo *robj; 364 365 gobj = drm_gem_object_lookup(filp, handle); 366 if (gobj == NULL) { 367 return -ENOENT; 368 } 369 robj = gem_to_amdgpu_bo(gobj); 370 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 371 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 372 drm_gem_object_put_unlocked(gobj); 373 return -EPERM; 374 } 375 *offset_p = amdgpu_bo_mmap_offset(robj); 376 drm_gem_object_put_unlocked(gobj); 377 return 0; 378 } 379 380 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 381 struct drm_file *filp) 382 { 383 union drm_amdgpu_gem_mmap *args = data; 384 uint32_t handle = args->in.handle; 385 memset(args, 0, sizeof(*args)); 386 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 387 } 388 389 /** 390 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 391 * 392 * @timeout_ns: timeout in ns 393 * 394 * Calculate the timeout in jiffies from an absolute timeout in ns. 395 */ 396 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 397 { 398 unsigned long timeout_jiffies; 399 ktime_t timeout; 400 401 /* clamp timeout if it's to large */ 402 if (((int64_t)timeout_ns) < 0) 403 return MAX_SCHEDULE_TIMEOUT; 404 405 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 406 if (ktime_to_ns(timeout) < 0) 407 return 0; 408 409 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 410 /* clamp timeout to avoid unsigned-> signed overflow */ 411 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 412 return MAX_SCHEDULE_TIMEOUT - 1; 413 414 return timeout_jiffies; 415 } 416 417 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 418 struct drm_file *filp) 419 { 420 union drm_amdgpu_gem_wait_idle *args = data; 421 struct drm_gem_object *gobj; 422 struct amdgpu_bo *robj; 423 uint32_t handle = args->in.handle; 424 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 425 int r = 0; 426 long ret; 427 428 gobj = drm_gem_object_lookup(filp, handle); 429 if (gobj == NULL) { 430 return -ENOENT; 431 } 432 robj = gem_to_amdgpu_bo(gobj); 433 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 434 timeout); 435 436 /* ret == 0 means not signaled, 437 * ret > 0 means signaled 438 * ret < 0 means interrupted before timeout 439 */ 440 if (ret >= 0) { 441 memset(args, 0, sizeof(*args)); 442 args->out.status = (ret == 0); 443 } else 444 r = ret; 445 446 drm_gem_object_put_unlocked(gobj); 447 return r; 448 } 449 450 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 451 struct drm_file *filp) 452 { 453 struct drm_amdgpu_gem_metadata *args = data; 454 struct drm_gem_object *gobj; 455 struct amdgpu_bo *robj; 456 int r = -1; 457 458 DRM_DEBUG("%d \n", args->handle); 459 gobj = drm_gem_object_lookup(filp, args->handle); 460 if (gobj == NULL) 461 return -ENOENT; 462 robj = gem_to_amdgpu_bo(gobj); 463 464 r = amdgpu_bo_reserve(robj, false); 465 if (unlikely(r != 0)) 466 goto out; 467 468 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 469 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 470 r = amdgpu_bo_get_metadata(robj, args->data.data, 471 sizeof(args->data.data), 472 &args->data.data_size_bytes, 473 &args->data.flags); 474 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 475 if (args->data.data_size_bytes > sizeof(args->data.data)) { 476 r = -EINVAL; 477 goto unreserve; 478 } 479 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 480 if (!r) 481 r = amdgpu_bo_set_metadata(robj, args->data.data, 482 args->data.data_size_bytes, 483 args->data.flags); 484 } 485 486 unreserve: 487 amdgpu_bo_unreserve(robj); 488 out: 489 drm_gem_object_put_unlocked(gobj); 490 return r; 491 } 492 493 /** 494 * amdgpu_gem_va_update_vm -update the bo_va in its VM 495 * 496 * @adev: amdgpu_device pointer 497 * @vm: vm to update 498 * @bo_va: bo_va to update 499 * @list: validation list 500 * @operation: map, unmap or clear 501 * 502 * Update the bo_va directly after setting its address. Errors are not 503 * vital here, so they are not reported back to userspace. 504 */ 505 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 506 struct amdgpu_vm *vm, 507 struct amdgpu_bo_va *bo_va, 508 struct list_head *list, 509 uint32_t operation) 510 { 511 int r; 512 513 if (!amdgpu_vm_ready(vm)) 514 return; 515 516 r = amdgpu_vm_update_directories(adev, vm); 517 if (r) 518 goto error; 519 520 r = amdgpu_vm_clear_freed(adev, vm, NULL); 521 if (r) 522 goto error; 523 524 if (operation == AMDGPU_VA_OP_MAP || 525 operation == AMDGPU_VA_OP_REPLACE) 526 r = amdgpu_vm_bo_update(adev, bo_va, false); 527 528 error: 529 if (r && r != -ERESTARTSYS) 530 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 531 } 532 533 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 534 struct drm_file *filp) 535 { 536 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 537 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 538 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 539 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 540 AMDGPU_VM_PAGE_PRT; 541 542 struct drm_amdgpu_gem_va *args = data; 543 struct drm_gem_object *gobj; 544 struct amdgpu_device *adev = dev->dev_private; 545 struct amdgpu_fpriv *fpriv = filp->driver_priv; 546 struct amdgpu_bo *abo; 547 struct amdgpu_bo_va *bo_va; 548 struct amdgpu_bo_list_entry vm_pd; 549 struct ttm_validate_buffer tv; 550 struct ww_acquire_ctx ticket; 551 struct list_head list, duplicates; 552 uint64_t va_flags; 553 int r = 0; 554 555 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 556 dev_err(&dev->pdev->dev, 557 "va_address 0x%lX is in reserved area 0x%X\n", 558 (unsigned long)args->va_address, 559 AMDGPU_VA_RESERVED_SIZE); 560 return -EINVAL; 561 } 562 563 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 564 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 565 args->flags); 566 return -EINVAL; 567 } 568 569 switch (args->operation) { 570 case AMDGPU_VA_OP_MAP: 571 case AMDGPU_VA_OP_UNMAP: 572 case AMDGPU_VA_OP_CLEAR: 573 case AMDGPU_VA_OP_REPLACE: 574 break; 575 default: 576 dev_err(&dev->pdev->dev, "unsupported operation %d\n", 577 args->operation); 578 return -EINVAL; 579 } 580 if ((args->operation == AMDGPU_VA_OP_MAP) || 581 (args->operation == AMDGPU_VA_OP_REPLACE)) { 582 if (amdgpu_kms_vram_lost(adev, fpriv)) 583 return -ENODEV; 584 } 585 586 INIT_LIST_HEAD(&list); 587 INIT_LIST_HEAD(&duplicates); 588 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 589 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 590 gobj = drm_gem_object_lookup(filp, args->handle); 591 if (gobj == NULL) 592 return -ENOENT; 593 abo = gem_to_amdgpu_bo(gobj); 594 tv.bo = &abo->tbo; 595 tv.shared = false; 596 list_add(&tv.head, &list); 597 } else { 598 gobj = NULL; 599 abo = NULL; 600 } 601 602 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 603 604 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 605 if (r) 606 goto error_unref; 607 608 if (abo) { 609 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 610 if (!bo_va) { 611 r = -ENOENT; 612 goto error_backoff; 613 } 614 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 615 bo_va = fpriv->prt_va; 616 } else { 617 bo_va = NULL; 618 } 619 620 switch (args->operation) { 621 case AMDGPU_VA_OP_MAP: 622 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 623 args->map_size); 624 if (r) 625 goto error_backoff; 626 627 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); 628 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 629 args->offset_in_bo, args->map_size, 630 va_flags); 631 break; 632 case AMDGPU_VA_OP_UNMAP: 633 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 634 break; 635 636 case AMDGPU_VA_OP_CLEAR: 637 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 638 args->va_address, 639 args->map_size); 640 break; 641 case AMDGPU_VA_OP_REPLACE: 642 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 643 args->map_size); 644 if (r) 645 goto error_backoff; 646 647 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); 648 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 649 args->offset_in_bo, args->map_size, 650 va_flags); 651 break; 652 default: 653 break; 654 } 655 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 656 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, 657 args->operation); 658 659 error_backoff: 660 ttm_eu_backoff_reservation(&ticket, &list); 661 662 error_unref: 663 drm_gem_object_put_unlocked(gobj); 664 return r; 665 } 666 667 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 668 struct drm_file *filp) 669 { 670 struct amdgpu_device *adev = dev->dev_private; 671 struct drm_amdgpu_gem_op *args = data; 672 struct drm_gem_object *gobj; 673 struct amdgpu_bo *robj; 674 int r; 675 676 gobj = drm_gem_object_lookup(filp, args->handle); 677 if (gobj == NULL) { 678 return -ENOENT; 679 } 680 robj = gem_to_amdgpu_bo(gobj); 681 682 r = amdgpu_bo_reserve(robj, false); 683 if (unlikely(r)) 684 goto out; 685 686 switch (args->op) { 687 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 688 struct drm_amdgpu_gem_create_in info; 689 void __user *out = u64_to_user_ptr(args->value); 690 691 info.bo_size = robj->gem_base.size; 692 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 693 info.domains = robj->preferred_domains; 694 info.domain_flags = robj->flags; 695 amdgpu_bo_unreserve(robj); 696 if (copy_to_user(out, &info, sizeof(info))) 697 r = -EFAULT; 698 break; 699 } 700 case AMDGPU_GEM_OP_SET_PLACEMENT: 701 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 702 r = -EINVAL; 703 amdgpu_bo_unreserve(robj); 704 break; 705 } 706 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 707 r = -EPERM; 708 amdgpu_bo_unreserve(robj); 709 break; 710 } 711 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 712 AMDGPU_GEM_DOMAIN_GTT | 713 AMDGPU_GEM_DOMAIN_CPU); 714 robj->allowed_domains = robj->preferred_domains; 715 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 716 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 717 718 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 719 amdgpu_vm_bo_invalidate(adev, robj, true); 720 721 amdgpu_bo_unreserve(robj); 722 break; 723 default: 724 amdgpu_bo_unreserve(robj); 725 r = -EINVAL; 726 } 727 728 out: 729 drm_gem_object_put_unlocked(gobj); 730 return r; 731 } 732 733 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 734 struct drm_device *dev, 735 struct drm_mode_create_dumb *args) 736 { 737 struct amdgpu_device *adev = dev->dev_private; 738 struct drm_gem_object *gobj; 739 uint32_t handle; 740 int r; 741 742 args->pitch = amdgpu_align_pitch(adev, args->width, 743 DIV_ROUND_UP(args->bpp, 8), 0); 744 args->size = (u64)args->pitch * args->height; 745 args->size = ALIGN(args->size, PAGE_SIZE); 746 747 r = amdgpu_gem_object_create(adev, args->size, 0, 748 AMDGPU_GEM_DOMAIN_VRAM, 749 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 750 false, NULL, &gobj); 751 if (r) 752 return -ENOMEM; 753 754 r = drm_gem_handle_create(file_priv, gobj, &handle); 755 /* drop reference from allocate - handle holds it now */ 756 drm_gem_object_put_unlocked(gobj); 757 if (r) { 758 return r; 759 } 760 args->handle = handle; 761 return 0; 762 } 763 764 #if defined(CONFIG_DEBUG_FS) 765 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 766 { 767 struct drm_gem_object *gobj = ptr; 768 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 769 struct seq_file *m = data; 770 771 unsigned domain; 772 const char *placement; 773 unsigned pin_count; 774 uint64_t offset; 775 776 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 777 switch (domain) { 778 case AMDGPU_GEM_DOMAIN_VRAM: 779 placement = "VRAM"; 780 break; 781 case AMDGPU_GEM_DOMAIN_GTT: 782 placement = " GTT"; 783 break; 784 case AMDGPU_GEM_DOMAIN_CPU: 785 default: 786 placement = " CPU"; 787 break; 788 } 789 seq_printf(m, "\t0x%08x: %12ld byte %s", 790 id, amdgpu_bo_size(bo), placement); 791 792 offset = ACCESS_ONCE(bo->tbo.mem.start); 793 if (offset != AMDGPU_BO_INVALID_OFFSET) 794 seq_printf(m, " @ 0x%010Lx", offset); 795 796 pin_count = ACCESS_ONCE(bo->pin_count); 797 if (pin_count) 798 seq_printf(m, " pin count %d", pin_count); 799 seq_printf(m, "\n"); 800 801 return 0; 802 } 803 804 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 805 { 806 struct drm_info_node *node = (struct drm_info_node *)m->private; 807 struct drm_device *dev = node->minor->dev; 808 struct drm_file *file; 809 int r; 810 811 r = mutex_lock_interruptible(&dev->filelist_mutex); 812 if (r) 813 return r; 814 815 list_for_each_entry(file, &dev->filelist, lhead) { 816 struct task_struct *task; 817 818 /* 819 * Although we have a valid reference on file->pid, that does 820 * not guarantee that the task_struct who called get_pid() is 821 * still alive (e.g. get_pid(current) => fork() => exit()). 822 * Therefore, we need to protect this ->comm access using RCU. 823 */ 824 rcu_read_lock(); 825 task = pid_task(file->pid, PIDTYPE_PID); 826 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 827 task ? task->comm : "<unknown>"); 828 rcu_read_unlock(); 829 830 spin_lock(&file->table_lock); 831 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 832 spin_unlock(&file->table_lock); 833 } 834 835 mutex_unlock(&dev->filelist_mutex); 836 return 0; 837 } 838 839 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 840 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 841 }; 842 #endif 843 844 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) 845 { 846 #if defined(CONFIG_DEBUG_FS) 847 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 848 #endif 849 return 0; 850 } 851