1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 34 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 35 { 36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 37 38 if (robj) { 39 amdgpu_mn_unregister(robj); 40 amdgpu_bo_unref(&robj); 41 } 42 } 43 44 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 45 int alignment, u32 initial_domain, 46 u64 flags, enum ttm_bo_type type, 47 struct reservation_object *resv, 48 struct drm_gem_object **obj) 49 { 50 struct amdgpu_bo *bo; 51 struct amdgpu_bo_param bp; 52 int r; 53 54 memset(&bp, 0, sizeof(bp)); 55 *obj = NULL; 56 /* At least align on page size */ 57 if (alignment < PAGE_SIZE) { 58 alignment = PAGE_SIZE; 59 } 60 61 bp.size = size; 62 bp.byte_align = alignment; 63 bp.type = type; 64 bp.resv = resv; 65 bp.preferred_domain = initial_domain; 66 retry: 67 bp.flags = flags; 68 bp.domain = initial_domain; 69 r = amdgpu_bo_create(adev, &bp, &bo); 70 if (r) { 71 if (r != -ERESTARTSYS) { 72 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 73 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 74 goto retry; 75 } 76 77 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 78 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 79 goto retry; 80 } 81 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 82 size, initial_domain, alignment, r); 83 } 84 return r; 85 } 86 *obj = &bo->gem_base; 87 88 return 0; 89 } 90 91 void amdgpu_gem_force_release(struct amdgpu_device *adev) 92 { 93 struct drm_device *ddev = adev->ddev; 94 struct drm_file *file; 95 96 mutex_lock(&ddev->filelist_mutex); 97 98 list_for_each_entry(file, &ddev->filelist, lhead) { 99 struct drm_gem_object *gobj; 100 int handle; 101 102 WARN_ONCE(1, "Still active user space clients!\n"); 103 spin_lock(&file->table_lock); 104 idr_for_each_entry(&file->object_idr, gobj, handle) { 105 WARN_ONCE(1, "And also active allocations!\n"); 106 drm_gem_object_put_unlocked(gobj); 107 } 108 idr_destroy(&file->object_idr); 109 spin_unlock(&file->table_lock); 110 } 111 112 mutex_unlock(&ddev->filelist_mutex); 113 } 114 115 /* 116 * Call from drm_gem_handle_create which appear in both new and open ioctl 117 * case. 118 */ 119 int amdgpu_gem_object_open(struct drm_gem_object *obj, 120 struct drm_file *file_priv) 121 { 122 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 123 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 124 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 125 struct amdgpu_vm *vm = &fpriv->vm; 126 struct amdgpu_bo_va *bo_va; 127 struct mm_struct *mm; 128 int r; 129 130 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 131 if (mm && mm != current->mm) 132 return -EPERM; 133 134 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 135 abo->tbo.resv != vm->root.base.bo->tbo.resv) 136 return -EPERM; 137 138 r = amdgpu_bo_reserve(abo, false); 139 if (r) 140 return r; 141 142 bo_va = amdgpu_vm_bo_find(vm, abo); 143 if (!bo_va) { 144 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 145 } else { 146 ++bo_va->ref_count; 147 } 148 amdgpu_bo_unreserve(abo); 149 return 0; 150 } 151 152 void amdgpu_gem_object_close(struct drm_gem_object *obj, 153 struct drm_file *file_priv) 154 { 155 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 156 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 157 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 158 struct amdgpu_vm *vm = &fpriv->vm; 159 160 struct amdgpu_bo_list_entry vm_pd; 161 struct list_head list, duplicates; 162 struct ttm_validate_buffer tv; 163 struct ww_acquire_ctx ticket; 164 struct amdgpu_bo_va *bo_va; 165 int r; 166 167 INIT_LIST_HEAD(&list); 168 INIT_LIST_HEAD(&duplicates); 169 170 tv.bo = &bo->tbo; 171 tv.shared = true; 172 list_add(&tv.head, &list); 173 174 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 175 176 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 177 if (r) { 178 dev_err(adev->dev, "leaking bo va because " 179 "we fail to reserve bo (%d)\n", r); 180 return; 181 } 182 bo_va = amdgpu_vm_bo_find(vm, bo); 183 if (bo_va && --bo_va->ref_count == 0) { 184 amdgpu_vm_bo_rmv(adev, bo_va); 185 186 if (amdgpu_vm_ready(vm)) { 187 struct dma_fence *fence = NULL; 188 189 r = amdgpu_vm_clear_freed(adev, vm, &fence); 190 if (unlikely(r)) { 191 dev_err(adev->dev, "failed to clear page " 192 "tables on GEM object close (%d)\n", r); 193 } 194 195 if (fence) { 196 amdgpu_bo_fence(bo, fence, true); 197 dma_fence_put(fence); 198 } 199 } 200 } 201 ttm_eu_backoff_reservation(&ticket, &list); 202 } 203 204 /* 205 * GEM ioctls. 206 */ 207 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 208 struct drm_file *filp) 209 { 210 struct amdgpu_device *adev = dev->dev_private; 211 struct amdgpu_fpriv *fpriv = filp->driver_priv; 212 struct amdgpu_vm *vm = &fpriv->vm; 213 union drm_amdgpu_gem_create *args = data; 214 uint64_t flags = args->in.domain_flags; 215 uint64_t size = args->in.bo_size; 216 struct reservation_object *resv = NULL; 217 struct drm_gem_object *gobj; 218 uint32_t handle; 219 int r; 220 221 /* reject invalid gem flags */ 222 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 223 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 224 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 225 AMDGPU_GEM_CREATE_VRAM_CLEARED | 226 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 227 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 228 229 return -EINVAL; 230 231 /* reject invalid gem domains */ 232 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 233 return -EINVAL; 234 235 /* create a gem object to contain this object in */ 236 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 237 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 238 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 239 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 240 size = size << AMDGPU_GDS_SHIFT; 241 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 242 size = size << AMDGPU_GWS_SHIFT; 243 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 244 size = size << AMDGPU_OA_SHIFT; 245 else 246 return -EINVAL; 247 } 248 size = roundup(size, PAGE_SIZE); 249 250 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 251 r = amdgpu_bo_reserve(vm->root.base.bo, false); 252 if (r) 253 return r; 254 255 resv = vm->root.base.bo->tbo.resv; 256 } 257 258 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 259 (u32)(0xffffffff & args->in.domains), 260 flags, false, resv, &gobj); 261 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 262 if (!r) { 263 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 264 265 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 266 } 267 amdgpu_bo_unreserve(vm->root.base.bo); 268 } 269 if (r) 270 return r; 271 272 r = drm_gem_handle_create(filp, gobj, &handle); 273 /* drop reference from allocate - handle holds it now */ 274 drm_gem_object_put_unlocked(gobj); 275 if (r) 276 return r; 277 278 memset(args, 0, sizeof(*args)); 279 args->out.handle = handle; 280 return 0; 281 } 282 283 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 284 struct drm_file *filp) 285 { 286 struct ttm_operation_ctx ctx = { true, false }; 287 struct amdgpu_device *adev = dev->dev_private; 288 struct drm_amdgpu_gem_userptr *args = data; 289 struct drm_gem_object *gobj; 290 struct amdgpu_bo *bo; 291 uint32_t handle; 292 int r; 293 294 if (offset_in_page(args->addr | args->size)) 295 return -EINVAL; 296 297 /* reject unknown flag values */ 298 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 299 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 300 AMDGPU_GEM_USERPTR_REGISTER)) 301 return -EINVAL; 302 303 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 304 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 305 306 /* if we want to write to it we must install a MMU notifier */ 307 return -EACCES; 308 } 309 310 /* create a gem object to contain this object in */ 311 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 312 0, 0, NULL, &gobj); 313 if (r) 314 return r; 315 316 bo = gem_to_amdgpu_bo(gobj); 317 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 318 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 319 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 320 if (r) 321 goto release_object; 322 323 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 324 r = amdgpu_mn_register(bo, args->addr); 325 if (r) 326 goto release_object; 327 } 328 329 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 330 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 331 bo->tbo.ttm->pages); 332 if (r) 333 goto release_object; 334 335 r = amdgpu_bo_reserve(bo, true); 336 if (r) 337 goto free_pages; 338 339 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 340 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 341 amdgpu_bo_unreserve(bo); 342 if (r) 343 goto free_pages; 344 } 345 346 r = drm_gem_handle_create(filp, gobj, &handle); 347 /* drop reference from allocate - handle holds it now */ 348 drm_gem_object_put_unlocked(gobj); 349 if (r) 350 return r; 351 352 args->handle = handle; 353 return 0; 354 355 free_pages: 356 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); 357 358 release_object: 359 drm_gem_object_put_unlocked(gobj); 360 361 return r; 362 } 363 364 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 365 struct drm_device *dev, 366 uint32_t handle, uint64_t *offset_p) 367 { 368 struct drm_gem_object *gobj; 369 struct amdgpu_bo *robj; 370 371 gobj = drm_gem_object_lookup(filp, handle); 372 if (gobj == NULL) { 373 return -ENOENT; 374 } 375 robj = gem_to_amdgpu_bo(gobj); 376 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 377 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 378 drm_gem_object_put_unlocked(gobj); 379 return -EPERM; 380 } 381 *offset_p = amdgpu_bo_mmap_offset(robj); 382 drm_gem_object_put_unlocked(gobj); 383 return 0; 384 } 385 386 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 387 struct drm_file *filp) 388 { 389 union drm_amdgpu_gem_mmap *args = data; 390 uint32_t handle = args->in.handle; 391 memset(args, 0, sizeof(*args)); 392 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 393 } 394 395 /** 396 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 397 * 398 * @timeout_ns: timeout in ns 399 * 400 * Calculate the timeout in jiffies from an absolute timeout in ns. 401 */ 402 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 403 { 404 unsigned long timeout_jiffies; 405 ktime_t timeout; 406 407 /* clamp timeout if it's to large */ 408 if (((int64_t)timeout_ns) < 0) 409 return MAX_SCHEDULE_TIMEOUT; 410 411 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 412 if (ktime_to_ns(timeout) < 0) 413 return 0; 414 415 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 416 /* clamp timeout to avoid unsigned-> signed overflow */ 417 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 418 return MAX_SCHEDULE_TIMEOUT - 1; 419 420 return timeout_jiffies; 421 } 422 423 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 424 struct drm_file *filp) 425 { 426 union drm_amdgpu_gem_wait_idle *args = data; 427 struct drm_gem_object *gobj; 428 struct amdgpu_bo *robj; 429 uint32_t handle = args->in.handle; 430 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 431 int r = 0; 432 long ret; 433 434 gobj = drm_gem_object_lookup(filp, handle); 435 if (gobj == NULL) { 436 return -ENOENT; 437 } 438 robj = gem_to_amdgpu_bo(gobj); 439 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 440 timeout); 441 442 /* ret == 0 means not signaled, 443 * ret > 0 means signaled 444 * ret < 0 means interrupted before timeout 445 */ 446 if (ret >= 0) { 447 memset(args, 0, sizeof(*args)); 448 args->out.status = (ret == 0); 449 } else 450 r = ret; 451 452 drm_gem_object_put_unlocked(gobj); 453 return r; 454 } 455 456 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 457 struct drm_file *filp) 458 { 459 struct drm_amdgpu_gem_metadata *args = data; 460 struct drm_gem_object *gobj; 461 struct amdgpu_bo *robj; 462 int r = -1; 463 464 DRM_DEBUG("%d \n", args->handle); 465 gobj = drm_gem_object_lookup(filp, args->handle); 466 if (gobj == NULL) 467 return -ENOENT; 468 robj = gem_to_amdgpu_bo(gobj); 469 470 r = amdgpu_bo_reserve(robj, false); 471 if (unlikely(r != 0)) 472 goto out; 473 474 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 475 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 476 r = amdgpu_bo_get_metadata(robj, args->data.data, 477 sizeof(args->data.data), 478 &args->data.data_size_bytes, 479 &args->data.flags); 480 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 481 if (args->data.data_size_bytes > sizeof(args->data.data)) { 482 r = -EINVAL; 483 goto unreserve; 484 } 485 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 486 if (!r) 487 r = amdgpu_bo_set_metadata(robj, args->data.data, 488 args->data.data_size_bytes, 489 args->data.flags); 490 } 491 492 unreserve: 493 amdgpu_bo_unreserve(robj); 494 out: 495 drm_gem_object_put_unlocked(gobj); 496 return r; 497 } 498 499 /** 500 * amdgpu_gem_va_update_vm -update the bo_va in its VM 501 * 502 * @adev: amdgpu_device pointer 503 * @vm: vm to update 504 * @bo_va: bo_va to update 505 * @list: validation list 506 * @operation: map, unmap or clear 507 * 508 * Update the bo_va directly after setting its address. Errors are not 509 * vital here, so they are not reported back to userspace. 510 */ 511 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 512 struct amdgpu_vm *vm, 513 struct amdgpu_bo_va *bo_va, 514 struct list_head *list, 515 uint32_t operation) 516 { 517 int r; 518 519 if (!amdgpu_vm_ready(vm)) 520 return; 521 522 r = amdgpu_vm_clear_freed(adev, vm, NULL); 523 if (r) 524 goto error; 525 526 if (operation == AMDGPU_VA_OP_MAP || 527 operation == AMDGPU_VA_OP_REPLACE) { 528 r = amdgpu_vm_bo_update(adev, bo_va, false); 529 if (r) 530 goto error; 531 } 532 533 r = amdgpu_vm_update_directories(adev, vm); 534 535 error: 536 if (r && r != -ERESTARTSYS) 537 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 538 } 539 540 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 541 struct drm_file *filp) 542 { 543 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 544 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 545 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 546 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 547 AMDGPU_VM_PAGE_PRT; 548 549 struct drm_amdgpu_gem_va *args = data; 550 struct drm_gem_object *gobj; 551 struct amdgpu_device *adev = dev->dev_private; 552 struct amdgpu_fpriv *fpriv = filp->driver_priv; 553 struct amdgpu_bo *abo; 554 struct amdgpu_bo_va *bo_va; 555 struct amdgpu_bo_list_entry vm_pd; 556 struct ttm_validate_buffer tv; 557 struct ww_acquire_ctx ticket; 558 struct list_head list, duplicates; 559 uint64_t va_flags; 560 int r = 0; 561 562 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 563 dev_dbg(&dev->pdev->dev, 564 "va_address 0x%LX is in reserved area 0x%LX\n", 565 args->va_address, AMDGPU_VA_RESERVED_SIZE); 566 return -EINVAL; 567 } 568 569 if (args->va_address >= AMDGPU_VA_HOLE_START && 570 args->va_address < AMDGPU_VA_HOLE_END) { 571 dev_dbg(&dev->pdev->dev, 572 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 573 args->va_address, AMDGPU_VA_HOLE_START, 574 AMDGPU_VA_HOLE_END); 575 return -EINVAL; 576 } 577 578 args->va_address &= AMDGPU_VA_HOLE_MASK; 579 580 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 581 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 582 args->flags); 583 return -EINVAL; 584 } 585 586 switch (args->operation) { 587 case AMDGPU_VA_OP_MAP: 588 case AMDGPU_VA_OP_UNMAP: 589 case AMDGPU_VA_OP_CLEAR: 590 case AMDGPU_VA_OP_REPLACE: 591 break; 592 default: 593 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 594 args->operation); 595 return -EINVAL; 596 } 597 598 INIT_LIST_HEAD(&list); 599 INIT_LIST_HEAD(&duplicates); 600 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 601 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 602 gobj = drm_gem_object_lookup(filp, args->handle); 603 if (gobj == NULL) 604 return -ENOENT; 605 abo = gem_to_amdgpu_bo(gobj); 606 tv.bo = &abo->tbo; 607 tv.shared = false; 608 list_add(&tv.head, &list); 609 } else { 610 gobj = NULL; 611 abo = NULL; 612 } 613 614 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 615 616 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 617 if (r) 618 goto error_unref; 619 620 if (abo) { 621 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 622 if (!bo_va) { 623 r = -ENOENT; 624 goto error_backoff; 625 } 626 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 627 bo_va = fpriv->prt_va; 628 } else { 629 bo_va = NULL; 630 } 631 632 switch (args->operation) { 633 case AMDGPU_VA_OP_MAP: 634 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 635 args->map_size); 636 if (r) 637 goto error_backoff; 638 639 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 640 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 641 args->offset_in_bo, args->map_size, 642 va_flags); 643 break; 644 case AMDGPU_VA_OP_UNMAP: 645 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 646 break; 647 648 case AMDGPU_VA_OP_CLEAR: 649 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 650 args->va_address, 651 args->map_size); 652 break; 653 case AMDGPU_VA_OP_REPLACE: 654 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 655 args->map_size); 656 if (r) 657 goto error_backoff; 658 659 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 660 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 661 args->offset_in_bo, args->map_size, 662 va_flags); 663 break; 664 default: 665 break; 666 } 667 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 668 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list, 669 args->operation); 670 671 error_backoff: 672 ttm_eu_backoff_reservation(&ticket, &list); 673 674 error_unref: 675 drm_gem_object_put_unlocked(gobj); 676 return r; 677 } 678 679 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 680 struct drm_file *filp) 681 { 682 struct amdgpu_device *adev = dev->dev_private; 683 struct drm_amdgpu_gem_op *args = data; 684 struct drm_gem_object *gobj; 685 struct amdgpu_bo *robj; 686 int r; 687 688 gobj = drm_gem_object_lookup(filp, args->handle); 689 if (gobj == NULL) { 690 return -ENOENT; 691 } 692 robj = gem_to_amdgpu_bo(gobj); 693 694 r = amdgpu_bo_reserve(robj, false); 695 if (unlikely(r)) 696 goto out; 697 698 switch (args->op) { 699 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 700 struct drm_amdgpu_gem_create_in info; 701 void __user *out = u64_to_user_ptr(args->value); 702 703 info.bo_size = robj->gem_base.size; 704 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 705 info.domains = robj->preferred_domains; 706 info.domain_flags = robj->flags; 707 amdgpu_bo_unreserve(robj); 708 if (copy_to_user(out, &info, sizeof(info))) 709 r = -EFAULT; 710 break; 711 } 712 case AMDGPU_GEM_OP_SET_PLACEMENT: 713 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 714 r = -EINVAL; 715 amdgpu_bo_unreserve(robj); 716 break; 717 } 718 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 719 r = -EPERM; 720 amdgpu_bo_unreserve(robj); 721 break; 722 } 723 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 724 AMDGPU_GEM_DOMAIN_GTT | 725 AMDGPU_GEM_DOMAIN_CPU); 726 robj->allowed_domains = robj->preferred_domains; 727 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 728 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 729 730 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 731 amdgpu_vm_bo_invalidate(adev, robj, true); 732 733 amdgpu_bo_unreserve(robj); 734 break; 735 default: 736 amdgpu_bo_unreserve(robj); 737 r = -EINVAL; 738 } 739 740 out: 741 drm_gem_object_put_unlocked(gobj); 742 return r; 743 } 744 745 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 746 struct drm_device *dev, 747 struct drm_mode_create_dumb *args) 748 { 749 struct amdgpu_device *adev = dev->dev_private; 750 struct drm_gem_object *gobj; 751 uint32_t handle; 752 int r; 753 754 args->pitch = amdgpu_align_pitch(adev, args->width, 755 DIV_ROUND_UP(args->bpp, 8), 0); 756 args->size = (u64)args->pitch * args->height; 757 args->size = ALIGN(args->size, PAGE_SIZE); 758 759 r = amdgpu_gem_object_create(adev, args->size, 0, 760 AMDGPU_GEM_DOMAIN_VRAM, 761 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 762 false, NULL, &gobj); 763 if (r) 764 return -ENOMEM; 765 766 r = drm_gem_handle_create(file_priv, gobj, &handle); 767 /* drop reference from allocate - handle holds it now */ 768 drm_gem_object_put_unlocked(gobj); 769 if (r) { 770 return r; 771 } 772 args->handle = handle; 773 return 0; 774 } 775 776 #if defined(CONFIG_DEBUG_FS) 777 778 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 779 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 780 seq_printf((m), " " #flag); \ 781 } 782 783 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 784 { 785 struct drm_gem_object *gobj = ptr; 786 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 787 struct seq_file *m = data; 788 789 struct dma_buf_attachment *attachment; 790 struct dma_buf *dma_buf; 791 unsigned domain; 792 const char *placement; 793 unsigned pin_count; 794 795 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 796 switch (domain) { 797 case AMDGPU_GEM_DOMAIN_VRAM: 798 placement = "VRAM"; 799 break; 800 case AMDGPU_GEM_DOMAIN_GTT: 801 placement = " GTT"; 802 break; 803 case AMDGPU_GEM_DOMAIN_CPU: 804 default: 805 placement = " CPU"; 806 break; 807 } 808 seq_printf(m, "\t0x%08x: %12ld byte %s", 809 id, amdgpu_bo_size(bo), placement); 810 811 pin_count = READ_ONCE(bo->pin_count); 812 if (pin_count) 813 seq_printf(m, " pin count %d", pin_count); 814 815 dma_buf = READ_ONCE(bo->gem_base.dma_buf); 816 attachment = READ_ONCE(bo->gem_base.import_attach); 817 818 if (attachment) 819 seq_printf(m, " imported from %p", dma_buf); 820 else if (dma_buf) 821 seq_printf(m, " exported as %p", dma_buf); 822 823 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 824 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 825 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 826 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 827 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 828 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 829 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 830 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 831 832 seq_printf(m, "\n"); 833 834 return 0; 835 } 836 837 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 838 { 839 struct drm_info_node *node = (struct drm_info_node *)m->private; 840 struct drm_device *dev = node->minor->dev; 841 struct drm_file *file; 842 int r; 843 844 r = mutex_lock_interruptible(&dev->filelist_mutex); 845 if (r) 846 return r; 847 848 list_for_each_entry(file, &dev->filelist, lhead) { 849 struct task_struct *task; 850 851 /* 852 * Although we have a valid reference on file->pid, that does 853 * not guarantee that the task_struct who called get_pid() is 854 * still alive (e.g. get_pid(current) => fork() => exit()). 855 * Therefore, we need to protect this ->comm access using RCU. 856 */ 857 rcu_read_lock(); 858 task = pid_task(file->pid, PIDTYPE_PID); 859 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 860 task ? task->comm : "<unknown>"); 861 rcu_read_unlock(); 862 863 spin_lock(&file->table_lock); 864 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 865 spin_unlock(&file->table_lock); 866 } 867 868 mutex_unlock(&dev->filelist_mutex); 869 return 0; 870 } 871 872 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 873 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 874 }; 875 #endif 876 877 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 878 { 879 #if defined(CONFIG_DEBUG_FS) 880 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 881 #endif 882 return 0; 883 } 884