1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_gem_ttm_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_display.h" 39 #include "amdgpu_dma_buf.h" 40 #include "amdgpu_xgmi.h" 41 42 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; 43 44 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 45 { 46 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 47 48 if (robj) { 49 amdgpu_mn_unregister(robj); 50 amdgpu_bo_unref(&robj); 51 } 52 } 53 54 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 55 int alignment, u32 initial_domain, 56 u64 flags, enum ttm_bo_type type, 57 struct dma_resv *resv, 58 struct drm_gem_object **obj) 59 { 60 struct amdgpu_bo *bo; 61 struct amdgpu_bo_param bp; 62 int r; 63 64 memset(&bp, 0, sizeof(bp)); 65 *obj = NULL; 66 67 bp.size = size; 68 bp.byte_align = alignment; 69 bp.type = type; 70 bp.resv = resv; 71 bp.preferred_domain = initial_domain; 72 bp.flags = flags; 73 bp.domain = initial_domain; 74 r = amdgpu_bo_create(adev, &bp, &bo); 75 if (r) 76 return r; 77 78 *obj = &bo->tbo.base; 79 (*obj)->funcs = &amdgpu_gem_object_funcs; 80 81 return 0; 82 } 83 84 void amdgpu_gem_force_release(struct amdgpu_device *adev) 85 { 86 struct drm_device *ddev = adev_to_drm(adev); 87 struct drm_file *file; 88 89 mutex_lock(&ddev->filelist_mutex); 90 91 list_for_each_entry(file, &ddev->filelist, lhead) { 92 struct drm_gem_object *gobj; 93 int handle; 94 95 WARN_ONCE(1, "Still active user space clients!\n"); 96 spin_lock(&file->table_lock); 97 idr_for_each_entry(&file->object_idr, gobj, handle) { 98 WARN_ONCE(1, "And also active allocations!\n"); 99 drm_gem_object_put(gobj); 100 } 101 idr_destroy(&file->object_idr); 102 spin_unlock(&file->table_lock); 103 } 104 105 mutex_unlock(&ddev->filelist_mutex); 106 } 107 108 /* 109 * Call from drm_gem_handle_create which appear in both new and open ioctl 110 * case. 111 */ 112 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 113 struct drm_file *file_priv) 114 { 115 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 116 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 117 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 118 struct amdgpu_vm *vm = &fpriv->vm; 119 struct amdgpu_bo_va *bo_va; 120 struct mm_struct *mm; 121 int r; 122 123 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 124 if (mm && mm != current->mm) 125 return -EPERM; 126 127 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 128 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 129 return -EPERM; 130 131 r = amdgpu_bo_reserve(abo, false); 132 if (r) 133 return r; 134 135 bo_va = amdgpu_vm_bo_find(vm, abo); 136 if (!bo_va) { 137 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 138 } else { 139 ++bo_va->ref_count; 140 } 141 amdgpu_bo_unreserve(abo); 142 return 0; 143 } 144 145 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 146 struct drm_file *file_priv) 147 { 148 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 149 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 150 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 151 struct amdgpu_vm *vm = &fpriv->vm; 152 153 struct amdgpu_bo_list_entry vm_pd; 154 struct list_head list, duplicates; 155 struct dma_fence *fence = NULL; 156 struct ttm_validate_buffer tv; 157 struct ww_acquire_ctx ticket; 158 struct amdgpu_bo_va *bo_va; 159 long r; 160 161 INIT_LIST_HEAD(&list); 162 INIT_LIST_HEAD(&duplicates); 163 164 tv.bo = &bo->tbo; 165 tv.num_shared = 2; 166 list_add(&tv.head, &list); 167 168 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 169 170 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 171 if (r) { 172 dev_err(adev->dev, "leaking bo va because " 173 "we fail to reserve bo (%ld)\n", r); 174 return; 175 } 176 bo_va = amdgpu_vm_bo_find(vm, bo); 177 if (!bo_va || --bo_va->ref_count) 178 goto out_unlock; 179 180 amdgpu_vm_bo_rmv(adev, bo_va); 181 if (!amdgpu_vm_ready(vm)) 182 goto out_unlock; 183 184 fence = dma_resv_get_excl(bo->tbo.base.resv); 185 if (fence) { 186 amdgpu_bo_fence(bo, fence, true); 187 fence = NULL; 188 } 189 190 r = amdgpu_vm_clear_freed(adev, vm, &fence); 191 if (r || !fence) 192 goto out_unlock; 193 194 amdgpu_bo_fence(bo, fence, true); 195 dma_fence_put(fence); 196 197 out_unlock: 198 if (unlikely(r < 0)) 199 dev_err(adev->dev, "failed to clear page " 200 "tables on GEM object close (%ld)\n", r); 201 ttm_eu_backoff_reservation(&ticket, &list); 202 } 203 204 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 205 .free = amdgpu_gem_object_free, 206 .open = amdgpu_gem_object_open, 207 .close = amdgpu_gem_object_close, 208 .export = amdgpu_gem_prime_export, 209 .vmap = drm_gem_ttm_vmap, 210 .vunmap = drm_gem_ttm_vunmap, 211 }; 212 213 /* 214 * GEM ioctls. 215 */ 216 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 217 struct drm_file *filp) 218 { 219 struct amdgpu_device *adev = drm_to_adev(dev); 220 struct amdgpu_fpriv *fpriv = filp->driver_priv; 221 struct amdgpu_vm *vm = &fpriv->vm; 222 union drm_amdgpu_gem_create *args = data; 223 uint64_t flags = args->in.domain_flags; 224 uint64_t size = args->in.bo_size; 225 struct dma_resv *resv = NULL; 226 struct drm_gem_object *gobj; 227 uint32_t handle, initial_domain; 228 int r; 229 230 /* reject invalid gem flags */ 231 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 232 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 233 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 234 AMDGPU_GEM_CREATE_VRAM_CLEARED | 235 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 236 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 237 AMDGPU_GEM_CREATE_ENCRYPTED)) 238 239 return -EINVAL; 240 241 /* reject invalid gem domains */ 242 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 243 return -EINVAL; 244 245 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 246 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 247 return -EINVAL; 248 } 249 250 /* create a gem object to contain this object in */ 251 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 252 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 253 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 254 /* if gds bo is created from user space, it must be 255 * passed to bo list 256 */ 257 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 258 return -EINVAL; 259 } 260 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 261 } 262 263 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 264 r = amdgpu_bo_reserve(vm->root.base.bo, false); 265 if (r) 266 return r; 267 268 resv = vm->root.base.bo->tbo.base.resv; 269 } 270 271 initial_domain = (u32)(0xffffffff & args->in.domains); 272 retry: 273 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 274 initial_domain, 275 flags, ttm_bo_type_device, resv, &gobj); 276 if (r) { 277 if (r != -ERESTARTSYS) { 278 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 279 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 280 goto retry; 281 } 282 283 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 284 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 285 goto retry; 286 } 287 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 288 size, initial_domain, args->in.alignment, r); 289 } 290 return r; 291 } 292 293 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 294 if (!r) { 295 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 296 297 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 298 } 299 amdgpu_bo_unreserve(vm->root.base.bo); 300 } 301 if (r) 302 return r; 303 304 r = drm_gem_handle_create(filp, gobj, &handle); 305 /* drop reference from allocate - handle holds it now */ 306 drm_gem_object_put(gobj); 307 if (r) 308 return r; 309 310 memset(args, 0, sizeof(*args)); 311 args->out.handle = handle; 312 return 0; 313 } 314 315 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 316 struct drm_file *filp) 317 { 318 struct ttm_operation_ctx ctx = { true, false }; 319 struct amdgpu_device *adev = drm_to_adev(dev); 320 struct drm_amdgpu_gem_userptr *args = data; 321 struct drm_gem_object *gobj; 322 struct amdgpu_bo *bo; 323 uint32_t handle; 324 int r; 325 326 args->addr = untagged_addr(args->addr); 327 328 if (offset_in_page(args->addr | args->size)) 329 return -EINVAL; 330 331 /* reject unknown flag values */ 332 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 333 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 334 AMDGPU_GEM_USERPTR_REGISTER)) 335 return -EINVAL; 336 337 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 338 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 339 340 /* if we want to write to it we must install a MMU notifier */ 341 return -EACCES; 342 } 343 344 /* create a gem object to contain this object in */ 345 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 346 0, ttm_bo_type_device, NULL, &gobj); 347 if (r) 348 return r; 349 350 bo = gem_to_amdgpu_bo(gobj); 351 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 352 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 353 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 354 if (r) 355 goto release_object; 356 357 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 358 r = amdgpu_mn_register(bo, args->addr); 359 if (r) 360 goto release_object; 361 } 362 363 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 364 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 365 if (r) 366 goto release_object; 367 368 r = amdgpu_bo_reserve(bo, true); 369 if (r) 370 goto user_pages_done; 371 372 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 373 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 374 amdgpu_bo_unreserve(bo); 375 if (r) 376 goto user_pages_done; 377 } 378 379 r = drm_gem_handle_create(filp, gobj, &handle); 380 if (r) 381 goto user_pages_done; 382 383 args->handle = handle; 384 385 user_pages_done: 386 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 387 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 388 389 release_object: 390 drm_gem_object_put(gobj); 391 392 return r; 393 } 394 395 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 396 struct drm_device *dev, 397 uint32_t handle, uint64_t *offset_p) 398 { 399 struct drm_gem_object *gobj; 400 struct amdgpu_bo *robj; 401 402 gobj = drm_gem_object_lookup(filp, handle); 403 if (gobj == NULL) { 404 return -ENOENT; 405 } 406 robj = gem_to_amdgpu_bo(gobj); 407 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 408 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 409 drm_gem_object_put(gobj); 410 return -EPERM; 411 } 412 *offset_p = amdgpu_bo_mmap_offset(robj); 413 drm_gem_object_put(gobj); 414 return 0; 415 } 416 417 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 418 struct drm_file *filp) 419 { 420 union drm_amdgpu_gem_mmap *args = data; 421 uint32_t handle = args->in.handle; 422 memset(args, 0, sizeof(*args)); 423 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 424 } 425 426 /** 427 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 428 * 429 * @timeout_ns: timeout in ns 430 * 431 * Calculate the timeout in jiffies from an absolute timeout in ns. 432 */ 433 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 434 { 435 unsigned long timeout_jiffies; 436 ktime_t timeout; 437 438 /* clamp timeout if it's to large */ 439 if (((int64_t)timeout_ns) < 0) 440 return MAX_SCHEDULE_TIMEOUT; 441 442 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 443 if (ktime_to_ns(timeout) < 0) 444 return 0; 445 446 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 447 /* clamp timeout to avoid unsigned-> signed overflow */ 448 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 449 return MAX_SCHEDULE_TIMEOUT - 1; 450 451 return timeout_jiffies; 452 } 453 454 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 455 struct drm_file *filp) 456 { 457 union drm_amdgpu_gem_wait_idle *args = data; 458 struct drm_gem_object *gobj; 459 struct amdgpu_bo *robj; 460 uint32_t handle = args->in.handle; 461 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 462 int r = 0; 463 long ret; 464 465 gobj = drm_gem_object_lookup(filp, handle); 466 if (gobj == NULL) { 467 return -ENOENT; 468 } 469 robj = gem_to_amdgpu_bo(gobj); 470 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 471 timeout); 472 473 /* ret == 0 means not signaled, 474 * ret > 0 means signaled 475 * ret < 0 means interrupted before timeout 476 */ 477 if (ret >= 0) { 478 memset(args, 0, sizeof(*args)); 479 args->out.status = (ret == 0); 480 } else 481 r = ret; 482 483 drm_gem_object_put(gobj); 484 return r; 485 } 486 487 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 488 struct drm_file *filp) 489 { 490 struct drm_amdgpu_gem_metadata *args = data; 491 struct drm_gem_object *gobj; 492 struct amdgpu_bo *robj; 493 int r = -1; 494 495 DRM_DEBUG("%d \n", args->handle); 496 gobj = drm_gem_object_lookup(filp, args->handle); 497 if (gobj == NULL) 498 return -ENOENT; 499 robj = gem_to_amdgpu_bo(gobj); 500 501 r = amdgpu_bo_reserve(robj, false); 502 if (unlikely(r != 0)) 503 goto out; 504 505 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 506 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 507 r = amdgpu_bo_get_metadata(robj, args->data.data, 508 sizeof(args->data.data), 509 &args->data.data_size_bytes, 510 &args->data.flags); 511 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 512 if (args->data.data_size_bytes > sizeof(args->data.data)) { 513 r = -EINVAL; 514 goto unreserve; 515 } 516 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 517 if (!r) 518 r = amdgpu_bo_set_metadata(robj, args->data.data, 519 args->data.data_size_bytes, 520 args->data.flags); 521 } 522 523 unreserve: 524 amdgpu_bo_unreserve(robj); 525 out: 526 drm_gem_object_put(gobj); 527 return r; 528 } 529 530 /** 531 * amdgpu_gem_va_update_vm -update the bo_va in its VM 532 * 533 * @adev: amdgpu_device pointer 534 * @vm: vm to update 535 * @bo_va: bo_va to update 536 * @operation: map, unmap or clear 537 * 538 * Update the bo_va directly after setting its address. Errors are not 539 * vital here, so they are not reported back to userspace. 540 */ 541 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 542 struct amdgpu_vm *vm, 543 struct amdgpu_bo_va *bo_va, 544 uint32_t operation) 545 { 546 int r; 547 548 if (!amdgpu_vm_ready(vm)) 549 return; 550 551 r = amdgpu_vm_clear_freed(adev, vm, NULL); 552 if (r) 553 goto error; 554 555 if (operation == AMDGPU_VA_OP_MAP || 556 operation == AMDGPU_VA_OP_REPLACE) { 557 r = amdgpu_vm_bo_update(adev, bo_va, false); 558 if (r) 559 goto error; 560 } 561 562 r = amdgpu_vm_update_pdes(adev, vm, false); 563 564 error: 565 if (r && r != -ERESTARTSYS) 566 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 567 } 568 569 /** 570 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 571 * 572 * @adev: amdgpu_device pointer 573 * @flags: GEM UAPI flags 574 * 575 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 576 */ 577 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 578 { 579 uint64_t pte_flag = 0; 580 581 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 582 pte_flag |= AMDGPU_PTE_EXECUTABLE; 583 if (flags & AMDGPU_VM_PAGE_READABLE) 584 pte_flag |= AMDGPU_PTE_READABLE; 585 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 586 pte_flag |= AMDGPU_PTE_WRITEABLE; 587 if (flags & AMDGPU_VM_PAGE_PRT) 588 pte_flag |= AMDGPU_PTE_PRT; 589 590 if (adev->gmc.gmc_funcs->map_mtype) 591 pte_flag |= amdgpu_gmc_map_mtype(adev, 592 flags & AMDGPU_VM_MTYPE_MASK); 593 594 return pte_flag; 595 } 596 597 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 598 struct drm_file *filp) 599 { 600 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 601 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 602 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 603 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 604 AMDGPU_VM_PAGE_PRT; 605 606 struct drm_amdgpu_gem_va *args = data; 607 struct drm_gem_object *gobj; 608 struct amdgpu_device *adev = drm_to_adev(dev); 609 struct amdgpu_fpriv *fpriv = filp->driver_priv; 610 struct amdgpu_bo *abo; 611 struct amdgpu_bo_va *bo_va; 612 struct amdgpu_bo_list_entry vm_pd; 613 struct ttm_validate_buffer tv; 614 struct ww_acquire_ctx ticket; 615 struct list_head list, duplicates; 616 uint64_t va_flags; 617 uint64_t vm_size; 618 int r = 0; 619 620 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 621 dev_dbg(dev->dev, 622 "va_address 0x%LX is in reserved area 0x%LX\n", 623 args->va_address, AMDGPU_VA_RESERVED_SIZE); 624 return -EINVAL; 625 } 626 627 if (args->va_address >= AMDGPU_GMC_HOLE_START && 628 args->va_address < AMDGPU_GMC_HOLE_END) { 629 dev_dbg(dev->dev, 630 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 631 args->va_address, AMDGPU_GMC_HOLE_START, 632 AMDGPU_GMC_HOLE_END); 633 return -EINVAL; 634 } 635 636 args->va_address &= AMDGPU_GMC_HOLE_MASK; 637 638 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 639 vm_size -= AMDGPU_VA_RESERVED_SIZE; 640 if (args->va_address + args->map_size > vm_size) { 641 dev_dbg(dev->dev, 642 "va_address 0x%llx is in top reserved area 0x%llx\n", 643 args->va_address + args->map_size, vm_size); 644 return -EINVAL; 645 } 646 647 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 648 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 649 args->flags); 650 return -EINVAL; 651 } 652 653 switch (args->operation) { 654 case AMDGPU_VA_OP_MAP: 655 case AMDGPU_VA_OP_UNMAP: 656 case AMDGPU_VA_OP_CLEAR: 657 case AMDGPU_VA_OP_REPLACE: 658 break; 659 default: 660 dev_dbg(dev->dev, "unsupported operation %d\n", 661 args->operation); 662 return -EINVAL; 663 } 664 665 INIT_LIST_HEAD(&list); 666 INIT_LIST_HEAD(&duplicates); 667 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 668 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 669 gobj = drm_gem_object_lookup(filp, args->handle); 670 if (gobj == NULL) 671 return -ENOENT; 672 abo = gem_to_amdgpu_bo(gobj); 673 tv.bo = &abo->tbo; 674 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 675 tv.num_shared = 1; 676 else 677 tv.num_shared = 0; 678 list_add(&tv.head, &list); 679 } else { 680 gobj = NULL; 681 abo = NULL; 682 } 683 684 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 685 686 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 687 if (r) 688 goto error_unref; 689 690 if (abo) { 691 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 692 if (!bo_va) { 693 r = -ENOENT; 694 goto error_backoff; 695 } 696 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 697 bo_va = fpriv->prt_va; 698 } else { 699 bo_va = NULL; 700 } 701 702 switch (args->operation) { 703 case AMDGPU_VA_OP_MAP: 704 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 705 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 706 args->offset_in_bo, args->map_size, 707 va_flags); 708 break; 709 case AMDGPU_VA_OP_UNMAP: 710 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 711 break; 712 713 case AMDGPU_VA_OP_CLEAR: 714 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 715 args->va_address, 716 args->map_size); 717 break; 718 case AMDGPU_VA_OP_REPLACE: 719 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 720 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 721 args->offset_in_bo, args->map_size, 722 va_flags); 723 break; 724 default: 725 break; 726 } 727 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 728 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 729 args->operation); 730 731 error_backoff: 732 ttm_eu_backoff_reservation(&ticket, &list); 733 734 error_unref: 735 drm_gem_object_put(gobj); 736 return r; 737 } 738 739 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 740 struct drm_file *filp) 741 { 742 struct amdgpu_device *adev = drm_to_adev(dev); 743 struct drm_amdgpu_gem_op *args = data; 744 struct drm_gem_object *gobj; 745 struct amdgpu_vm_bo_base *base; 746 struct amdgpu_bo *robj; 747 int r; 748 749 gobj = drm_gem_object_lookup(filp, args->handle); 750 if (gobj == NULL) { 751 return -ENOENT; 752 } 753 robj = gem_to_amdgpu_bo(gobj); 754 755 r = amdgpu_bo_reserve(robj, false); 756 if (unlikely(r)) 757 goto out; 758 759 switch (args->op) { 760 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 761 struct drm_amdgpu_gem_create_in info; 762 void __user *out = u64_to_user_ptr(args->value); 763 764 info.bo_size = robj->tbo.base.size; 765 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 766 info.domains = robj->preferred_domains; 767 info.domain_flags = robj->flags; 768 amdgpu_bo_unreserve(robj); 769 if (copy_to_user(out, &info, sizeof(info))) 770 r = -EFAULT; 771 break; 772 } 773 case AMDGPU_GEM_OP_SET_PLACEMENT: 774 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 775 r = -EINVAL; 776 amdgpu_bo_unreserve(robj); 777 break; 778 } 779 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 780 r = -EPERM; 781 amdgpu_bo_unreserve(robj); 782 break; 783 } 784 for (base = robj->vm_bo; base; base = base->next) 785 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 786 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 787 r = -EINVAL; 788 amdgpu_bo_unreserve(robj); 789 goto out; 790 } 791 792 793 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 794 AMDGPU_GEM_DOMAIN_GTT | 795 AMDGPU_GEM_DOMAIN_CPU); 796 robj->allowed_domains = robj->preferred_domains; 797 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 798 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 799 800 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 801 amdgpu_vm_bo_invalidate(adev, robj, true); 802 803 amdgpu_bo_unreserve(robj); 804 break; 805 default: 806 amdgpu_bo_unreserve(robj); 807 r = -EINVAL; 808 } 809 810 out: 811 drm_gem_object_put(gobj); 812 return r; 813 } 814 815 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 816 struct drm_device *dev, 817 struct drm_mode_create_dumb *args) 818 { 819 struct amdgpu_device *adev = drm_to_adev(dev); 820 struct drm_gem_object *gobj; 821 uint32_t handle; 822 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 823 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 824 u32 domain; 825 int r; 826 827 /* 828 * The buffer returned from this function should be cleared, but 829 * it can only be done if the ring is enabled or we'll fail to 830 * create the buffer. 831 */ 832 if (adev->mman.buffer_funcs_enabled) 833 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 834 835 args->pitch = amdgpu_align_pitch(adev, args->width, 836 DIV_ROUND_UP(args->bpp, 8), 0); 837 args->size = (u64)args->pitch * args->height; 838 args->size = ALIGN(args->size, PAGE_SIZE); 839 domain = amdgpu_bo_get_preferred_pin_domain(adev, 840 amdgpu_display_supported_domains(adev, flags)); 841 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 842 ttm_bo_type_device, NULL, &gobj); 843 if (r) 844 return -ENOMEM; 845 846 r = drm_gem_handle_create(file_priv, gobj, &handle); 847 /* drop reference from allocate - handle holds it now */ 848 drm_gem_object_put(gobj); 849 if (r) { 850 return r; 851 } 852 args->handle = handle; 853 return 0; 854 } 855 856 #if defined(CONFIG_DEBUG_FS) 857 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) 858 { 859 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 860 struct drm_device *dev = adev_to_drm(adev); 861 struct drm_file *file; 862 int r; 863 864 r = mutex_lock_interruptible(&dev->filelist_mutex); 865 if (r) 866 return r; 867 868 list_for_each_entry(file, &dev->filelist, lhead) { 869 struct task_struct *task; 870 struct drm_gem_object *gobj; 871 int id; 872 873 /* 874 * Although we have a valid reference on file->pid, that does 875 * not guarantee that the task_struct who called get_pid() is 876 * still alive (e.g. get_pid(current) => fork() => exit()). 877 * Therefore, we need to protect this ->comm access using RCU. 878 */ 879 rcu_read_lock(); 880 task = pid_task(file->pid, PIDTYPE_PID); 881 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 882 task ? task->comm : "<unknown>"); 883 rcu_read_unlock(); 884 885 spin_lock(&file->table_lock); 886 idr_for_each_entry(&file->object_idr, gobj, id) { 887 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 888 889 amdgpu_bo_print_info(id, bo, m); 890 } 891 spin_unlock(&file->table_lock); 892 } 893 894 mutex_unlock(&dev->filelist_mutex); 895 return 0; 896 } 897 898 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); 899 900 #endif 901 902 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 903 { 904 #if defined(CONFIG_DEBUG_FS) 905 struct drm_minor *minor = adev_to_drm(adev)->primary; 906 struct dentry *root = minor->debugfs_root; 907 908 debugfs_create_file("amdgpu_gem_info", 0444, root, adev, 909 &amdgpu_debugfs_gem_info_fops); 910 #endif 911 } 912