1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/pagemap.h> 30 #include <drm/drmP.h> 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "amdgpu_display.h" 34 35 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 36 { 37 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 38 39 if (robj) { 40 amdgpu_mn_unregister(robj); 41 amdgpu_bo_unref(&robj); 42 } 43 } 44 45 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 46 int alignment, u32 initial_domain, 47 u64 flags, enum ttm_bo_type type, 48 struct reservation_object *resv, 49 struct drm_gem_object **obj) 50 { 51 struct amdgpu_bo *bo; 52 struct amdgpu_bo_param bp; 53 int r; 54 55 memset(&bp, 0, sizeof(bp)); 56 *obj = NULL; 57 /* At least align on page size */ 58 if (alignment < PAGE_SIZE) { 59 alignment = PAGE_SIZE; 60 } 61 62 bp.size = size; 63 bp.byte_align = alignment; 64 bp.type = type; 65 bp.resv = resv; 66 bp.preferred_domain = initial_domain; 67 retry: 68 bp.flags = flags; 69 bp.domain = initial_domain; 70 r = amdgpu_bo_create(adev, &bp, &bo); 71 if (r) { 72 if (r != -ERESTARTSYS) { 73 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 74 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 75 goto retry; 76 } 77 78 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 79 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 80 goto retry; 81 } 82 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 83 size, initial_domain, alignment, r); 84 } 85 return r; 86 } 87 *obj = &bo->gem_base; 88 89 return 0; 90 } 91 92 void amdgpu_gem_force_release(struct amdgpu_device *adev) 93 { 94 struct drm_device *ddev = adev->ddev; 95 struct drm_file *file; 96 97 mutex_lock(&ddev->filelist_mutex); 98 99 list_for_each_entry(file, &ddev->filelist, lhead) { 100 struct drm_gem_object *gobj; 101 int handle; 102 103 WARN_ONCE(1, "Still active user space clients!\n"); 104 spin_lock(&file->table_lock); 105 idr_for_each_entry(&file->object_idr, gobj, handle) { 106 WARN_ONCE(1, "And also active allocations!\n"); 107 drm_gem_object_put_unlocked(gobj); 108 } 109 idr_destroy(&file->object_idr); 110 spin_unlock(&file->table_lock); 111 } 112 113 mutex_unlock(&ddev->filelist_mutex); 114 } 115 116 /* 117 * Call from drm_gem_handle_create which appear in both new and open ioctl 118 * case. 119 */ 120 int amdgpu_gem_object_open(struct drm_gem_object *obj, 121 struct drm_file *file_priv) 122 { 123 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 124 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 125 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 126 struct amdgpu_vm *vm = &fpriv->vm; 127 struct amdgpu_bo_va *bo_va; 128 struct mm_struct *mm; 129 int r; 130 131 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 132 if (mm && mm != current->mm) 133 return -EPERM; 134 135 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 136 abo->tbo.resv != vm->root.base.bo->tbo.resv) 137 return -EPERM; 138 139 r = amdgpu_bo_reserve(abo, false); 140 if (r) 141 return r; 142 143 bo_va = amdgpu_vm_bo_find(vm, abo); 144 if (!bo_va) { 145 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 146 } else { 147 ++bo_va->ref_count; 148 } 149 amdgpu_bo_unreserve(abo); 150 return 0; 151 } 152 153 void amdgpu_gem_object_close(struct drm_gem_object *obj, 154 struct drm_file *file_priv) 155 { 156 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 157 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 158 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 159 struct amdgpu_vm *vm = &fpriv->vm; 160 161 struct amdgpu_bo_list_entry vm_pd; 162 struct list_head list, duplicates; 163 struct ttm_validate_buffer tv; 164 struct ww_acquire_ctx ticket; 165 struct amdgpu_bo_va *bo_va; 166 int r; 167 168 INIT_LIST_HEAD(&list); 169 INIT_LIST_HEAD(&duplicates); 170 171 tv.bo = &bo->tbo; 172 tv.num_shared = 1; 173 list_add(&tv.head, &list); 174 175 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 176 177 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 178 if (r) { 179 dev_err(adev->dev, "leaking bo va because " 180 "we fail to reserve bo (%d)\n", r); 181 return; 182 } 183 bo_va = amdgpu_vm_bo_find(vm, bo); 184 if (bo_va && --bo_va->ref_count == 0) { 185 amdgpu_vm_bo_rmv(adev, bo_va); 186 187 if (amdgpu_vm_ready(vm)) { 188 struct dma_fence *fence = NULL; 189 190 r = amdgpu_vm_clear_freed(adev, vm, &fence); 191 if (unlikely(r)) { 192 dev_err(adev->dev, "failed to clear page " 193 "tables on GEM object close (%d)\n", r); 194 } 195 196 if (fence) { 197 amdgpu_bo_fence(bo, fence, true); 198 dma_fence_put(fence); 199 } 200 } 201 } 202 ttm_eu_backoff_reservation(&ticket, &list); 203 } 204 205 /* 206 * GEM ioctls. 207 */ 208 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 209 struct drm_file *filp) 210 { 211 struct amdgpu_device *adev = dev->dev_private; 212 struct amdgpu_fpriv *fpriv = filp->driver_priv; 213 struct amdgpu_vm *vm = &fpriv->vm; 214 union drm_amdgpu_gem_create *args = data; 215 uint64_t flags = args->in.domain_flags; 216 uint64_t size = args->in.bo_size; 217 struct reservation_object *resv = NULL; 218 struct drm_gem_object *gobj; 219 uint32_t handle; 220 int r; 221 222 /* reject invalid gem flags */ 223 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 224 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 225 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 226 AMDGPU_GEM_CREATE_VRAM_CLEARED | 227 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 228 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 229 230 return -EINVAL; 231 232 /* reject invalid gem domains */ 233 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 234 return -EINVAL; 235 236 /* create a gem object to contain this object in */ 237 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 238 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 239 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 240 /* if gds bo is created from user space, it must be 241 * passed to bo list 242 */ 243 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 244 return -EINVAL; 245 } 246 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 247 /* GDS allocations must be DW aligned */ 248 if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS) 249 size = ALIGN(size, 4); 250 } 251 252 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 253 r = amdgpu_bo_reserve(vm->root.base.bo, false); 254 if (r) 255 return r; 256 257 resv = vm->root.base.bo->tbo.resv; 258 } 259 260 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 261 (u32)(0xffffffff & args->in.domains), 262 flags, ttm_bo_type_device, resv, &gobj); 263 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 264 if (!r) { 265 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 266 267 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 268 } 269 amdgpu_bo_unreserve(vm->root.base.bo); 270 } 271 if (r) 272 return r; 273 274 r = drm_gem_handle_create(filp, gobj, &handle); 275 /* drop reference from allocate - handle holds it now */ 276 drm_gem_object_put_unlocked(gobj); 277 if (r) 278 return r; 279 280 memset(args, 0, sizeof(*args)); 281 args->out.handle = handle; 282 return 0; 283 } 284 285 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 286 struct drm_file *filp) 287 { 288 struct ttm_operation_ctx ctx = { true, false }; 289 struct amdgpu_device *adev = dev->dev_private; 290 struct drm_amdgpu_gem_userptr *args = data; 291 struct drm_gem_object *gobj; 292 struct amdgpu_bo *bo; 293 uint32_t handle; 294 int r; 295 296 if (offset_in_page(args->addr | args->size)) 297 return -EINVAL; 298 299 /* reject unknown flag values */ 300 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 301 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 302 AMDGPU_GEM_USERPTR_REGISTER)) 303 return -EINVAL; 304 305 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 306 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 307 308 /* if we want to write to it we must install a MMU notifier */ 309 return -EACCES; 310 } 311 312 /* create a gem object to contain this object in */ 313 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 314 0, ttm_bo_type_device, NULL, &gobj); 315 if (r) 316 return r; 317 318 bo = gem_to_amdgpu_bo(gobj); 319 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 320 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 321 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 322 if (r) 323 goto release_object; 324 325 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 326 r = amdgpu_mn_register(bo, args->addr); 327 if (r) 328 goto release_object; 329 } 330 331 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 332 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 333 bo->tbo.ttm->pages); 334 if (r) 335 goto release_object; 336 337 r = amdgpu_bo_reserve(bo, true); 338 if (r) 339 goto free_pages; 340 341 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 342 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 343 amdgpu_bo_unreserve(bo); 344 if (r) 345 goto free_pages; 346 } 347 348 r = drm_gem_handle_create(filp, gobj, &handle); 349 /* drop reference from allocate - handle holds it now */ 350 drm_gem_object_put_unlocked(gobj); 351 if (r) 352 return r; 353 354 args->handle = handle; 355 return 0; 356 357 free_pages: 358 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); 359 360 release_object: 361 drm_gem_object_put_unlocked(gobj); 362 363 return r; 364 } 365 366 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 367 struct drm_device *dev, 368 uint32_t handle, uint64_t *offset_p) 369 { 370 struct drm_gem_object *gobj; 371 struct amdgpu_bo *robj; 372 373 gobj = drm_gem_object_lookup(filp, handle); 374 if (gobj == NULL) { 375 return -ENOENT; 376 } 377 robj = gem_to_amdgpu_bo(gobj); 378 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 379 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 380 drm_gem_object_put_unlocked(gobj); 381 return -EPERM; 382 } 383 *offset_p = amdgpu_bo_mmap_offset(robj); 384 drm_gem_object_put_unlocked(gobj); 385 return 0; 386 } 387 388 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 389 struct drm_file *filp) 390 { 391 union drm_amdgpu_gem_mmap *args = data; 392 uint32_t handle = args->in.handle; 393 memset(args, 0, sizeof(*args)); 394 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 395 } 396 397 /** 398 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 399 * 400 * @timeout_ns: timeout in ns 401 * 402 * Calculate the timeout in jiffies from an absolute timeout in ns. 403 */ 404 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 405 { 406 unsigned long timeout_jiffies; 407 ktime_t timeout; 408 409 /* clamp timeout if it's to large */ 410 if (((int64_t)timeout_ns) < 0) 411 return MAX_SCHEDULE_TIMEOUT; 412 413 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 414 if (ktime_to_ns(timeout) < 0) 415 return 0; 416 417 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 418 /* clamp timeout to avoid unsigned-> signed overflow */ 419 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 420 return MAX_SCHEDULE_TIMEOUT - 1; 421 422 return timeout_jiffies; 423 } 424 425 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 426 struct drm_file *filp) 427 { 428 union drm_amdgpu_gem_wait_idle *args = data; 429 struct drm_gem_object *gobj; 430 struct amdgpu_bo *robj; 431 uint32_t handle = args->in.handle; 432 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 433 int r = 0; 434 long ret; 435 436 gobj = drm_gem_object_lookup(filp, handle); 437 if (gobj == NULL) { 438 return -ENOENT; 439 } 440 robj = gem_to_amdgpu_bo(gobj); 441 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 442 timeout); 443 444 /* ret == 0 means not signaled, 445 * ret > 0 means signaled 446 * ret < 0 means interrupted before timeout 447 */ 448 if (ret >= 0) { 449 memset(args, 0, sizeof(*args)); 450 args->out.status = (ret == 0); 451 } else 452 r = ret; 453 454 drm_gem_object_put_unlocked(gobj); 455 return r; 456 } 457 458 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 459 struct drm_file *filp) 460 { 461 struct drm_amdgpu_gem_metadata *args = data; 462 struct drm_gem_object *gobj; 463 struct amdgpu_bo *robj; 464 int r = -1; 465 466 DRM_DEBUG("%d \n", args->handle); 467 gobj = drm_gem_object_lookup(filp, args->handle); 468 if (gobj == NULL) 469 return -ENOENT; 470 robj = gem_to_amdgpu_bo(gobj); 471 472 r = amdgpu_bo_reserve(robj, false); 473 if (unlikely(r != 0)) 474 goto out; 475 476 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 477 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 478 r = amdgpu_bo_get_metadata(robj, args->data.data, 479 sizeof(args->data.data), 480 &args->data.data_size_bytes, 481 &args->data.flags); 482 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 483 if (args->data.data_size_bytes > sizeof(args->data.data)) { 484 r = -EINVAL; 485 goto unreserve; 486 } 487 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 488 if (!r) 489 r = amdgpu_bo_set_metadata(robj, args->data.data, 490 args->data.data_size_bytes, 491 args->data.flags); 492 } 493 494 unreserve: 495 amdgpu_bo_unreserve(robj); 496 out: 497 drm_gem_object_put_unlocked(gobj); 498 return r; 499 } 500 501 /** 502 * amdgpu_gem_va_update_vm -update the bo_va in its VM 503 * 504 * @adev: amdgpu_device pointer 505 * @vm: vm to update 506 * @bo_va: bo_va to update 507 * @operation: map, unmap or clear 508 * 509 * Update the bo_va directly after setting its address. Errors are not 510 * vital here, so they are not reported back to userspace. 511 */ 512 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 513 struct amdgpu_vm *vm, 514 struct amdgpu_bo_va *bo_va, 515 uint32_t operation) 516 { 517 int r; 518 519 if (!amdgpu_vm_ready(vm)) 520 return; 521 522 r = amdgpu_vm_clear_freed(adev, vm, NULL); 523 if (r) 524 goto error; 525 526 if (operation == AMDGPU_VA_OP_MAP || 527 operation == AMDGPU_VA_OP_REPLACE) { 528 r = amdgpu_vm_bo_update(adev, bo_va, false); 529 if (r) 530 goto error; 531 } 532 533 r = amdgpu_vm_update_directories(adev, vm); 534 535 error: 536 if (r && r != -ERESTARTSYS) 537 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 538 } 539 540 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 541 struct drm_file *filp) 542 { 543 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 544 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 545 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 546 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 547 AMDGPU_VM_PAGE_PRT; 548 549 struct drm_amdgpu_gem_va *args = data; 550 struct drm_gem_object *gobj; 551 struct amdgpu_device *adev = dev->dev_private; 552 struct amdgpu_fpriv *fpriv = filp->driver_priv; 553 struct amdgpu_bo *abo; 554 struct amdgpu_bo_va *bo_va; 555 struct amdgpu_bo_list_entry vm_pd; 556 struct ttm_validate_buffer tv; 557 struct ww_acquire_ctx ticket; 558 struct list_head list, duplicates; 559 uint64_t va_flags; 560 int r = 0; 561 562 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 563 dev_dbg(&dev->pdev->dev, 564 "va_address 0x%LX is in reserved area 0x%LX\n", 565 args->va_address, AMDGPU_VA_RESERVED_SIZE); 566 return -EINVAL; 567 } 568 569 if (args->va_address >= AMDGPU_GMC_HOLE_START && 570 args->va_address < AMDGPU_GMC_HOLE_END) { 571 dev_dbg(&dev->pdev->dev, 572 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 573 args->va_address, AMDGPU_GMC_HOLE_START, 574 AMDGPU_GMC_HOLE_END); 575 return -EINVAL; 576 } 577 578 args->va_address &= AMDGPU_GMC_HOLE_MASK; 579 580 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 581 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 582 args->flags); 583 return -EINVAL; 584 } 585 586 switch (args->operation) { 587 case AMDGPU_VA_OP_MAP: 588 case AMDGPU_VA_OP_UNMAP: 589 case AMDGPU_VA_OP_CLEAR: 590 case AMDGPU_VA_OP_REPLACE: 591 break; 592 default: 593 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 594 args->operation); 595 return -EINVAL; 596 } 597 598 INIT_LIST_HEAD(&list); 599 INIT_LIST_HEAD(&duplicates); 600 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 601 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 602 gobj = drm_gem_object_lookup(filp, args->handle); 603 if (gobj == NULL) 604 return -ENOENT; 605 abo = gem_to_amdgpu_bo(gobj); 606 tv.bo = &abo->tbo; 607 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 608 tv.num_shared = 1; 609 else 610 tv.num_shared = 0; 611 list_add(&tv.head, &list); 612 } else { 613 gobj = NULL; 614 abo = NULL; 615 } 616 617 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 618 619 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 620 if (r) 621 goto error_unref; 622 623 if (abo) { 624 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 625 if (!bo_va) { 626 r = -ENOENT; 627 goto error_backoff; 628 } 629 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 630 bo_va = fpriv->prt_va; 631 } else { 632 bo_va = NULL; 633 } 634 635 switch (args->operation) { 636 case AMDGPU_VA_OP_MAP: 637 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 638 args->map_size); 639 if (r) 640 goto error_backoff; 641 642 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 643 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 644 args->offset_in_bo, args->map_size, 645 va_flags); 646 break; 647 case AMDGPU_VA_OP_UNMAP: 648 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 649 break; 650 651 case AMDGPU_VA_OP_CLEAR: 652 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 653 args->va_address, 654 args->map_size); 655 break; 656 case AMDGPU_VA_OP_REPLACE: 657 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, 658 args->map_size); 659 if (r) 660 goto error_backoff; 661 662 va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); 663 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 664 args->offset_in_bo, args->map_size, 665 va_flags); 666 break; 667 default: 668 break; 669 } 670 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 671 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 672 args->operation); 673 674 error_backoff: 675 ttm_eu_backoff_reservation(&ticket, &list); 676 677 error_unref: 678 drm_gem_object_put_unlocked(gobj); 679 return r; 680 } 681 682 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 683 struct drm_file *filp) 684 { 685 struct amdgpu_device *adev = dev->dev_private; 686 struct drm_amdgpu_gem_op *args = data; 687 struct drm_gem_object *gobj; 688 struct amdgpu_bo *robj; 689 int r; 690 691 gobj = drm_gem_object_lookup(filp, args->handle); 692 if (gobj == NULL) { 693 return -ENOENT; 694 } 695 robj = gem_to_amdgpu_bo(gobj); 696 697 r = amdgpu_bo_reserve(robj, false); 698 if (unlikely(r)) 699 goto out; 700 701 switch (args->op) { 702 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 703 struct drm_amdgpu_gem_create_in info; 704 void __user *out = u64_to_user_ptr(args->value); 705 706 info.bo_size = robj->gem_base.size; 707 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 708 info.domains = robj->preferred_domains; 709 info.domain_flags = robj->flags; 710 amdgpu_bo_unreserve(robj); 711 if (copy_to_user(out, &info, sizeof(info))) 712 r = -EFAULT; 713 break; 714 } 715 case AMDGPU_GEM_OP_SET_PLACEMENT: 716 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 717 r = -EINVAL; 718 amdgpu_bo_unreserve(robj); 719 break; 720 } 721 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 722 r = -EPERM; 723 amdgpu_bo_unreserve(robj); 724 break; 725 } 726 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 727 AMDGPU_GEM_DOMAIN_GTT | 728 AMDGPU_GEM_DOMAIN_CPU); 729 robj->allowed_domains = robj->preferred_domains; 730 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 731 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 732 733 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 734 amdgpu_vm_bo_invalidate(adev, robj, true); 735 736 amdgpu_bo_unreserve(robj); 737 break; 738 default: 739 amdgpu_bo_unreserve(robj); 740 r = -EINVAL; 741 } 742 743 out: 744 drm_gem_object_put_unlocked(gobj); 745 return r; 746 } 747 748 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 749 struct drm_device *dev, 750 struct drm_mode_create_dumb *args) 751 { 752 struct amdgpu_device *adev = dev->dev_private; 753 struct drm_gem_object *gobj; 754 uint32_t handle; 755 u32 domain; 756 int r; 757 758 args->pitch = amdgpu_align_pitch(adev, args->width, 759 DIV_ROUND_UP(args->bpp, 8), 0); 760 args->size = (u64)args->pitch * args->height; 761 args->size = ALIGN(args->size, PAGE_SIZE); 762 domain = amdgpu_bo_get_preferred_pin_domain(adev, 763 amdgpu_display_supported_domains(adev)); 764 r = amdgpu_gem_object_create(adev, args->size, 0, domain, 765 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 766 ttm_bo_type_device, NULL, &gobj); 767 if (r) 768 return -ENOMEM; 769 770 r = drm_gem_handle_create(file_priv, gobj, &handle); 771 /* drop reference from allocate - handle holds it now */ 772 drm_gem_object_put_unlocked(gobj); 773 if (r) { 774 return r; 775 } 776 args->handle = handle; 777 return 0; 778 } 779 780 #if defined(CONFIG_DEBUG_FS) 781 782 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 783 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 784 seq_printf((m), " " #flag); \ 785 } 786 787 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 788 { 789 struct drm_gem_object *gobj = ptr; 790 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 791 struct seq_file *m = data; 792 793 struct dma_buf_attachment *attachment; 794 struct dma_buf *dma_buf; 795 unsigned domain; 796 const char *placement; 797 unsigned pin_count; 798 799 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 800 switch (domain) { 801 case AMDGPU_GEM_DOMAIN_VRAM: 802 placement = "VRAM"; 803 break; 804 case AMDGPU_GEM_DOMAIN_GTT: 805 placement = " GTT"; 806 break; 807 case AMDGPU_GEM_DOMAIN_CPU: 808 default: 809 placement = " CPU"; 810 break; 811 } 812 seq_printf(m, "\t0x%08x: %12ld byte %s", 813 id, amdgpu_bo_size(bo), placement); 814 815 pin_count = READ_ONCE(bo->pin_count); 816 if (pin_count) 817 seq_printf(m, " pin count %d", pin_count); 818 819 dma_buf = READ_ONCE(bo->gem_base.dma_buf); 820 attachment = READ_ONCE(bo->gem_base.import_attach); 821 822 if (attachment) 823 seq_printf(m, " imported from %p", dma_buf); 824 else if (dma_buf) 825 seq_printf(m, " exported as %p", dma_buf); 826 827 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 828 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 829 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 830 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 831 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 832 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 833 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 834 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 835 836 seq_printf(m, "\n"); 837 838 return 0; 839 } 840 841 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 842 { 843 struct drm_info_node *node = (struct drm_info_node *)m->private; 844 struct drm_device *dev = node->minor->dev; 845 struct drm_file *file; 846 int r; 847 848 r = mutex_lock_interruptible(&dev->filelist_mutex); 849 if (r) 850 return r; 851 852 list_for_each_entry(file, &dev->filelist, lhead) { 853 struct task_struct *task; 854 855 /* 856 * Although we have a valid reference on file->pid, that does 857 * not guarantee that the task_struct who called get_pid() is 858 * still alive (e.g. get_pid(current) => fork() => exit()). 859 * Therefore, we need to protect this ->comm access using RCU. 860 */ 861 rcu_read_lock(); 862 task = pid_task(file->pid, PIDTYPE_PID); 863 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 864 task ? task->comm : "<unknown>"); 865 rcu_read_unlock(); 866 867 spin_lock(&file->table_lock); 868 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 869 spin_unlock(&file->table_lock); 870 } 871 872 mutex_unlock(&dev->filelist_mutex); 873 return 0; 874 } 875 876 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 877 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 878 }; 879 #endif 880 881 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 882 { 883 #if defined(CONFIG_DEBUG_FS) 884 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 885 #endif 886 return 0; 887 } 888