1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_debugfs.h> 36 #include <drm/drm_gem_ttm_helper.h> 37 38 #include "amdgpu.h" 39 #include "amdgpu_display.h" 40 #include "amdgpu_dma_buf.h" 41 #include "amdgpu_xgmi.h" 42 43 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; 44 45 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 46 { 47 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 48 49 if (robj) { 50 amdgpu_mn_unregister(robj); 51 amdgpu_bo_unref(&robj); 52 } 53 } 54 55 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 56 int alignment, u32 initial_domain, 57 u64 flags, enum ttm_bo_type type, 58 struct dma_resv *resv, 59 struct drm_gem_object **obj) 60 { 61 struct amdgpu_bo *bo; 62 struct amdgpu_bo_param bp; 63 int r; 64 65 memset(&bp, 0, sizeof(bp)); 66 *obj = NULL; 67 68 bp.size = size; 69 bp.byte_align = alignment; 70 bp.type = type; 71 bp.resv = resv; 72 bp.preferred_domain = initial_domain; 73 retry: 74 bp.flags = flags; 75 bp.domain = initial_domain; 76 r = amdgpu_bo_create(adev, &bp, &bo); 77 if (r) { 78 if (r != -ERESTARTSYS) { 79 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 80 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 81 goto retry; 82 } 83 84 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 85 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 86 goto retry; 87 } 88 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 89 size, initial_domain, alignment, r); 90 } 91 return r; 92 } 93 *obj = &bo->tbo.base; 94 (*obj)->funcs = &amdgpu_gem_object_funcs; 95 96 return 0; 97 } 98 99 void amdgpu_gem_force_release(struct amdgpu_device *adev) 100 { 101 struct drm_device *ddev = adev_to_drm(adev); 102 struct drm_file *file; 103 104 mutex_lock(&ddev->filelist_mutex); 105 106 list_for_each_entry(file, &ddev->filelist, lhead) { 107 struct drm_gem_object *gobj; 108 int handle; 109 110 WARN_ONCE(1, "Still active user space clients!\n"); 111 spin_lock(&file->table_lock); 112 idr_for_each_entry(&file->object_idr, gobj, handle) { 113 WARN_ONCE(1, "And also active allocations!\n"); 114 drm_gem_object_put(gobj); 115 } 116 idr_destroy(&file->object_idr); 117 spin_unlock(&file->table_lock); 118 } 119 120 mutex_unlock(&ddev->filelist_mutex); 121 } 122 123 /* 124 * Call from drm_gem_handle_create which appear in both new and open ioctl 125 * case. 126 */ 127 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 128 struct drm_file *file_priv) 129 { 130 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 131 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 132 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 133 struct amdgpu_vm *vm = &fpriv->vm; 134 struct amdgpu_bo_va *bo_va; 135 struct mm_struct *mm; 136 int r; 137 138 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 139 if (mm && mm != current->mm) 140 return -EPERM; 141 142 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 143 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 144 return -EPERM; 145 146 r = amdgpu_bo_reserve(abo, false); 147 if (r) 148 return r; 149 150 bo_va = amdgpu_vm_bo_find(vm, abo); 151 if (!bo_va) { 152 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 153 } else { 154 ++bo_va->ref_count; 155 } 156 amdgpu_bo_unreserve(abo); 157 return 0; 158 } 159 160 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 161 struct drm_file *file_priv) 162 { 163 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 164 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 165 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 166 struct amdgpu_vm *vm = &fpriv->vm; 167 168 struct amdgpu_bo_list_entry vm_pd; 169 struct list_head list, duplicates; 170 struct dma_fence *fence = NULL; 171 struct ttm_validate_buffer tv; 172 struct ww_acquire_ctx ticket; 173 struct amdgpu_bo_va *bo_va; 174 long r; 175 176 INIT_LIST_HEAD(&list); 177 INIT_LIST_HEAD(&duplicates); 178 179 tv.bo = &bo->tbo; 180 tv.num_shared = 2; 181 list_add(&tv.head, &list); 182 183 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 184 185 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 186 if (r) { 187 dev_err(adev->dev, "leaking bo va because " 188 "we fail to reserve bo (%ld)\n", r); 189 return; 190 } 191 bo_va = amdgpu_vm_bo_find(vm, bo); 192 if (!bo_va || --bo_va->ref_count) 193 goto out_unlock; 194 195 amdgpu_vm_bo_rmv(adev, bo_va); 196 if (!amdgpu_vm_ready(vm)) 197 goto out_unlock; 198 199 fence = dma_resv_get_excl(bo->tbo.base.resv); 200 if (fence) { 201 amdgpu_bo_fence(bo, fence, true); 202 fence = NULL; 203 } 204 205 r = amdgpu_vm_clear_freed(adev, vm, &fence); 206 if (r || !fence) 207 goto out_unlock; 208 209 amdgpu_bo_fence(bo, fence, true); 210 dma_fence_put(fence); 211 212 out_unlock: 213 if (unlikely(r < 0)) 214 dev_err(adev->dev, "failed to clear page " 215 "tables on GEM object close (%ld)\n", r); 216 ttm_eu_backoff_reservation(&ticket, &list); 217 } 218 219 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 220 .free = amdgpu_gem_object_free, 221 .open = amdgpu_gem_object_open, 222 .close = amdgpu_gem_object_close, 223 .export = amdgpu_gem_prime_export, 224 .vmap = drm_gem_ttm_vmap, 225 .vunmap = drm_gem_ttm_vunmap, 226 }; 227 228 /* 229 * GEM ioctls. 230 */ 231 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 232 struct drm_file *filp) 233 { 234 struct amdgpu_device *adev = drm_to_adev(dev); 235 struct amdgpu_fpriv *fpriv = filp->driver_priv; 236 struct amdgpu_vm *vm = &fpriv->vm; 237 union drm_amdgpu_gem_create *args = data; 238 uint64_t flags = args->in.domain_flags; 239 uint64_t size = args->in.bo_size; 240 struct dma_resv *resv = NULL; 241 struct drm_gem_object *gobj; 242 uint32_t handle; 243 int r; 244 245 /* reject invalid gem flags */ 246 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 247 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 248 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 249 AMDGPU_GEM_CREATE_VRAM_CLEARED | 250 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 251 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 252 AMDGPU_GEM_CREATE_ENCRYPTED)) 253 254 return -EINVAL; 255 256 /* reject invalid gem domains */ 257 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 258 return -EINVAL; 259 260 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 261 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 262 return -EINVAL; 263 } 264 265 /* create a gem object to contain this object in */ 266 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 267 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 268 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 269 /* if gds bo is created from user space, it must be 270 * passed to bo list 271 */ 272 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 273 return -EINVAL; 274 } 275 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 276 } 277 278 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 279 r = amdgpu_bo_reserve(vm->root.base.bo, false); 280 if (r) 281 return r; 282 283 resv = vm->root.base.bo->tbo.base.resv; 284 } 285 286 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 287 (u32)(0xffffffff & args->in.domains), 288 flags, ttm_bo_type_device, resv, &gobj); 289 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 290 if (!r) { 291 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 292 293 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 294 } 295 amdgpu_bo_unreserve(vm->root.base.bo); 296 } 297 if (r) 298 return r; 299 300 r = drm_gem_handle_create(filp, gobj, &handle); 301 /* drop reference from allocate - handle holds it now */ 302 drm_gem_object_put(gobj); 303 if (r) 304 return r; 305 306 memset(args, 0, sizeof(*args)); 307 args->out.handle = handle; 308 return 0; 309 } 310 311 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 312 struct drm_file *filp) 313 { 314 struct ttm_operation_ctx ctx = { true, false }; 315 struct amdgpu_device *adev = drm_to_adev(dev); 316 struct drm_amdgpu_gem_userptr *args = data; 317 struct drm_gem_object *gobj; 318 struct amdgpu_bo *bo; 319 uint32_t handle; 320 int r; 321 322 args->addr = untagged_addr(args->addr); 323 324 if (offset_in_page(args->addr | args->size)) 325 return -EINVAL; 326 327 /* reject unknown flag values */ 328 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 329 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 330 AMDGPU_GEM_USERPTR_REGISTER)) 331 return -EINVAL; 332 333 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 334 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 335 336 /* if we want to write to it we must install a MMU notifier */ 337 return -EACCES; 338 } 339 340 /* create a gem object to contain this object in */ 341 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 342 0, ttm_bo_type_device, NULL, &gobj); 343 if (r) 344 return r; 345 346 bo = gem_to_amdgpu_bo(gobj); 347 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 348 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 349 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 350 if (r) 351 goto release_object; 352 353 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 354 r = amdgpu_mn_register(bo, args->addr); 355 if (r) 356 goto release_object; 357 } 358 359 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 360 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 361 if (r) 362 goto release_object; 363 364 r = amdgpu_bo_reserve(bo, true); 365 if (r) 366 goto user_pages_done; 367 368 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 369 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 370 amdgpu_bo_unreserve(bo); 371 if (r) 372 goto user_pages_done; 373 } 374 375 r = drm_gem_handle_create(filp, gobj, &handle); 376 if (r) 377 goto user_pages_done; 378 379 args->handle = handle; 380 381 user_pages_done: 382 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 383 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 384 385 release_object: 386 drm_gem_object_put(gobj); 387 388 return r; 389 } 390 391 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 392 struct drm_device *dev, 393 uint32_t handle, uint64_t *offset_p) 394 { 395 struct drm_gem_object *gobj; 396 struct amdgpu_bo *robj; 397 398 gobj = drm_gem_object_lookup(filp, handle); 399 if (gobj == NULL) { 400 return -ENOENT; 401 } 402 robj = gem_to_amdgpu_bo(gobj); 403 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 404 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 405 drm_gem_object_put(gobj); 406 return -EPERM; 407 } 408 *offset_p = amdgpu_bo_mmap_offset(robj); 409 drm_gem_object_put(gobj); 410 return 0; 411 } 412 413 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 414 struct drm_file *filp) 415 { 416 union drm_amdgpu_gem_mmap *args = data; 417 uint32_t handle = args->in.handle; 418 memset(args, 0, sizeof(*args)); 419 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 420 } 421 422 /** 423 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 424 * 425 * @timeout_ns: timeout in ns 426 * 427 * Calculate the timeout in jiffies from an absolute timeout in ns. 428 */ 429 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 430 { 431 unsigned long timeout_jiffies; 432 ktime_t timeout; 433 434 /* clamp timeout if it's to large */ 435 if (((int64_t)timeout_ns) < 0) 436 return MAX_SCHEDULE_TIMEOUT; 437 438 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 439 if (ktime_to_ns(timeout) < 0) 440 return 0; 441 442 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 443 /* clamp timeout to avoid unsigned-> signed overflow */ 444 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 445 return MAX_SCHEDULE_TIMEOUT - 1; 446 447 return timeout_jiffies; 448 } 449 450 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 451 struct drm_file *filp) 452 { 453 union drm_amdgpu_gem_wait_idle *args = data; 454 struct drm_gem_object *gobj; 455 struct amdgpu_bo *robj; 456 uint32_t handle = args->in.handle; 457 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 458 int r = 0; 459 long ret; 460 461 gobj = drm_gem_object_lookup(filp, handle); 462 if (gobj == NULL) { 463 return -ENOENT; 464 } 465 robj = gem_to_amdgpu_bo(gobj); 466 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 467 timeout); 468 469 /* ret == 0 means not signaled, 470 * ret > 0 means signaled 471 * ret < 0 means interrupted before timeout 472 */ 473 if (ret >= 0) { 474 memset(args, 0, sizeof(*args)); 475 args->out.status = (ret == 0); 476 } else 477 r = ret; 478 479 drm_gem_object_put(gobj); 480 return r; 481 } 482 483 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 484 struct drm_file *filp) 485 { 486 struct drm_amdgpu_gem_metadata *args = data; 487 struct drm_gem_object *gobj; 488 struct amdgpu_bo *robj; 489 int r = -1; 490 491 DRM_DEBUG("%d \n", args->handle); 492 gobj = drm_gem_object_lookup(filp, args->handle); 493 if (gobj == NULL) 494 return -ENOENT; 495 robj = gem_to_amdgpu_bo(gobj); 496 497 r = amdgpu_bo_reserve(robj, false); 498 if (unlikely(r != 0)) 499 goto out; 500 501 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 502 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 503 r = amdgpu_bo_get_metadata(robj, args->data.data, 504 sizeof(args->data.data), 505 &args->data.data_size_bytes, 506 &args->data.flags); 507 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 508 if (args->data.data_size_bytes > sizeof(args->data.data)) { 509 r = -EINVAL; 510 goto unreserve; 511 } 512 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 513 if (!r) 514 r = amdgpu_bo_set_metadata(robj, args->data.data, 515 args->data.data_size_bytes, 516 args->data.flags); 517 } 518 519 unreserve: 520 amdgpu_bo_unreserve(robj); 521 out: 522 drm_gem_object_put(gobj); 523 return r; 524 } 525 526 /** 527 * amdgpu_gem_va_update_vm -update the bo_va in its VM 528 * 529 * @adev: amdgpu_device pointer 530 * @vm: vm to update 531 * @bo_va: bo_va to update 532 * @operation: map, unmap or clear 533 * 534 * Update the bo_va directly after setting its address. Errors are not 535 * vital here, so they are not reported back to userspace. 536 */ 537 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 538 struct amdgpu_vm *vm, 539 struct amdgpu_bo_va *bo_va, 540 uint32_t operation) 541 { 542 int r; 543 544 if (!amdgpu_vm_ready(vm)) 545 return; 546 547 r = amdgpu_vm_clear_freed(adev, vm, NULL); 548 if (r) 549 goto error; 550 551 if (operation == AMDGPU_VA_OP_MAP || 552 operation == AMDGPU_VA_OP_REPLACE) { 553 r = amdgpu_vm_bo_update(adev, bo_va, false); 554 if (r) 555 goto error; 556 } 557 558 r = amdgpu_vm_update_pdes(adev, vm, false); 559 560 error: 561 if (r && r != -ERESTARTSYS) 562 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 563 } 564 565 /** 566 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 567 * 568 * @adev: amdgpu_device pointer 569 * @flags: GEM UAPI flags 570 * 571 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 572 */ 573 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 574 { 575 uint64_t pte_flag = 0; 576 577 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 578 pte_flag |= AMDGPU_PTE_EXECUTABLE; 579 if (flags & AMDGPU_VM_PAGE_READABLE) 580 pte_flag |= AMDGPU_PTE_READABLE; 581 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 582 pte_flag |= AMDGPU_PTE_WRITEABLE; 583 if (flags & AMDGPU_VM_PAGE_PRT) 584 pte_flag |= AMDGPU_PTE_PRT; 585 586 if (adev->gmc.gmc_funcs->map_mtype) 587 pte_flag |= amdgpu_gmc_map_mtype(adev, 588 flags & AMDGPU_VM_MTYPE_MASK); 589 590 return pte_flag; 591 } 592 593 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 594 struct drm_file *filp) 595 { 596 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 597 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 598 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 599 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 600 AMDGPU_VM_PAGE_PRT; 601 602 struct drm_amdgpu_gem_va *args = data; 603 struct drm_gem_object *gobj; 604 struct amdgpu_device *adev = drm_to_adev(dev); 605 struct amdgpu_fpriv *fpriv = filp->driver_priv; 606 struct amdgpu_bo *abo; 607 struct amdgpu_bo_va *bo_va; 608 struct amdgpu_bo_list_entry vm_pd; 609 struct ttm_validate_buffer tv; 610 struct ww_acquire_ctx ticket; 611 struct list_head list, duplicates; 612 uint64_t va_flags; 613 uint64_t vm_size; 614 int r = 0; 615 616 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 617 dev_dbg(&dev->pdev->dev, 618 "va_address 0x%LX is in reserved area 0x%LX\n", 619 args->va_address, AMDGPU_VA_RESERVED_SIZE); 620 return -EINVAL; 621 } 622 623 if (args->va_address >= AMDGPU_GMC_HOLE_START && 624 args->va_address < AMDGPU_GMC_HOLE_END) { 625 dev_dbg(&dev->pdev->dev, 626 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 627 args->va_address, AMDGPU_GMC_HOLE_START, 628 AMDGPU_GMC_HOLE_END); 629 return -EINVAL; 630 } 631 632 args->va_address &= AMDGPU_GMC_HOLE_MASK; 633 634 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 635 vm_size -= AMDGPU_VA_RESERVED_SIZE; 636 if (args->va_address + args->map_size > vm_size) { 637 dev_dbg(&dev->pdev->dev, 638 "va_address 0x%llx is in top reserved area 0x%llx\n", 639 args->va_address + args->map_size, vm_size); 640 return -EINVAL; 641 } 642 643 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 644 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 645 args->flags); 646 return -EINVAL; 647 } 648 649 switch (args->operation) { 650 case AMDGPU_VA_OP_MAP: 651 case AMDGPU_VA_OP_UNMAP: 652 case AMDGPU_VA_OP_CLEAR: 653 case AMDGPU_VA_OP_REPLACE: 654 break; 655 default: 656 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 657 args->operation); 658 return -EINVAL; 659 } 660 661 INIT_LIST_HEAD(&list); 662 INIT_LIST_HEAD(&duplicates); 663 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 664 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 665 gobj = drm_gem_object_lookup(filp, args->handle); 666 if (gobj == NULL) 667 return -ENOENT; 668 abo = gem_to_amdgpu_bo(gobj); 669 tv.bo = &abo->tbo; 670 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 671 tv.num_shared = 1; 672 else 673 tv.num_shared = 0; 674 list_add(&tv.head, &list); 675 } else { 676 gobj = NULL; 677 abo = NULL; 678 } 679 680 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 681 682 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 683 if (r) 684 goto error_unref; 685 686 if (abo) { 687 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 688 if (!bo_va) { 689 r = -ENOENT; 690 goto error_backoff; 691 } 692 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 693 bo_va = fpriv->prt_va; 694 } else { 695 bo_va = NULL; 696 } 697 698 switch (args->operation) { 699 case AMDGPU_VA_OP_MAP: 700 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 701 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 702 args->offset_in_bo, args->map_size, 703 va_flags); 704 break; 705 case AMDGPU_VA_OP_UNMAP: 706 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 707 break; 708 709 case AMDGPU_VA_OP_CLEAR: 710 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 711 args->va_address, 712 args->map_size); 713 break; 714 case AMDGPU_VA_OP_REPLACE: 715 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 716 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 717 args->offset_in_bo, args->map_size, 718 va_flags); 719 break; 720 default: 721 break; 722 } 723 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 724 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 725 args->operation); 726 727 error_backoff: 728 ttm_eu_backoff_reservation(&ticket, &list); 729 730 error_unref: 731 drm_gem_object_put(gobj); 732 return r; 733 } 734 735 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 736 struct drm_file *filp) 737 { 738 struct amdgpu_device *adev = drm_to_adev(dev); 739 struct drm_amdgpu_gem_op *args = data; 740 struct drm_gem_object *gobj; 741 struct amdgpu_vm_bo_base *base; 742 struct amdgpu_bo *robj; 743 int r; 744 745 gobj = drm_gem_object_lookup(filp, args->handle); 746 if (gobj == NULL) { 747 return -ENOENT; 748 } 749 robj = gem_to_amdgpu_bo(gobj); 750 751 r = amdgpu_bo_reserve(robj, false); 752 if (unlikely(r)) 753 goto out; 754 755 switch (args->op) { 756 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 757 struct drm_amdgpu_gem_create_in info; 758 void __user *out = u64_to_user_ptr(args->value); 759 760 info.bo_size = robj->tbo.base.size; 761 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 762 info.domains = robj->preferred_domains; 763 info.domain_flags = robj->flags; 764 amdgpu_bo_unreserve(robj); 765 if (copy_to_user(out, &info, sizeof(info))) 766 r = -EFAULT; 767 break; 768 } 769 case AMDGPU_GEM_OP_SET_PLACEMENT: 770 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 771 r = -EINVAL; 772 amdgpu_bo_unreserve(robj); 773 break; 774 } 775 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 776 r = -EPERM; 777 amdgpu_bo_unreserve(robj); 778 break; 779 } 780 for (base = robj->vm_bo; base; base = base->next) 781 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 782 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 783 r = -EINVAL; 784 amdgpu_bo_unreserve(robj); 785 goto out; 786 } 787 788 789 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 790 AMDGPU_GEM_DOMAIN_GTT | 791 AMDGPU_GEM_DOMAIN_CPU); 792 robj->allowed_domains = robj->preferred_domains; 793 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 794 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 795 796 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 797 amdgpu_vm_bo_invalidate(adev, robj, true); 798 799 amdgpu_bo_unreserve(robj); 800 break; 801 default: 802 amdgpu_bo_unreserve(robj); 803 r = -EINVAL; 804 } 805 806 out: 807 drm_gem_object_put(gobj); 808 return r; 809 } 810 811 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 812 struct drm_device *dev, 813 struct drm_mode_create_dumb *args) 814 { 815 struct amdgpu_device *adev = drm_to_adev(dev); 816 struct drm_gem_object *gobj; 817 uint32_t handle; 818 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 819 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 820 u32 domain; 821 int r; 822 823 /* 824 * The buffer returned from this function should be cleared, but 825 * it can only be done if the ring is enabled or we'll fail to 826 * create the buffer. 827 */ 828 if (adev->mman.buffer_funcs_enabled) 829 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 830 831 args->pitch = amdgpu_align_pitch(adev, args->width, 832 DIV_ROUND_UP(args->bpp, 8), 0); 833 args->size = (u64)args->pitch * args->height; 834 args->size = ALIGN(args->size, PAGE_SIZE); 835 domain = amdgpu_bo_get_preferred_pin_domain(adev, 836 amdgpu_display_supported_domains(adev, flags)); 837 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 838 ttm_bo_type_device, NULL, &gobj); 839 if (r) 840 return -ENOMEM; 841 842 r = drm_gem_handle_create(file_priv, gobj, &handle); 843 /* drop reference from allocate - handle holds it now */ 844 drm_gem_object_put(gobj); 845 if (r) { 846 return r; 847 } 848 args->handle = handle; 849 return 0; 850 } 851 852 #if defined(CONFIG_DEBUG_FS) 853 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 854 { 855 struct drm_info_node *node = (struct drm_info_node *)m->private; 856 struct drm_device *dev = node->minor->dev; 857 struct drm_file *file; 858 int r; 859 860 r = mutex_lock_interruptible(&dev->filelist_mutex); 861 if (r) 862 return r; 863 864 list_for_each_entry(file, &dev->filelist, lhead) { 865 struct task_struct *task; 866 struct drm_gem_object *gobj; 867 int id; 868 869 /* 870 * Although we have a valid reference on file->pid, that does 871 * not guarantee that the task_struct who called get_pid() is 872 * still alive (e.g. get_pid(current) => fork() => exit()). 873 * Therefore, we need to protect this ->comm access using RCU. 874 */ 875 rcu_read_lock(); 876 task = pid_task(file->pid, PIDTYPE_PID); 877 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 878 task ? task->comm : "<unknown>"); 879 rcu_read_unlock(); 880 881 spin_lock(&file->table_lock); 882 idr_for_each_entry(&file->object_idr, gobj, id) { 883 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 884 885 amdgpu_bo_print_info(id, bo, m); 886 } 887 spin_unlock(&file->table_lock); 888 } 889 890 mutex_unlock(&dev->filelist_mutex); 891 return 0; 892 } 893 894 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 895 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 896 }; 897 #endif 898 899 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 900 { 901 #if defined(CONFIG_DEBUG_FS) 902 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 903 ARRAY_SIZE(amdgpu_debugfs_gem_list)); 904 #endif 905 return 0; 906 } 907