xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c (revision 4ed91d48259d9ddd378424d008f2e6559f7e78f8)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
30 #include <drm/drmP.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
35 {
36 	struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
37 
38 	if (robj) {
39 		if (robj->gem_base.import_attach)
40 			drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
41 		amdgpu_mn_unregister(robj);
42 		amdgpu_bo_unref(&robj);
43 	}
44 }
45 
46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47 				int alignment, u32 initial_domain,
48 				u64 flags, bool kernel,
49 				struct drm_gem_object **obj)
50 {
51 	struct amdgpu_bo *robj;
52 	unsigned long max_size;
53 	int r;
54 
55 	*obj = NULL;
56 	/* At least align on page size */
57 	if (alignment < PAGE_SIZE) {
58 		alignment = PAGE_SIZE;
59 	}
60 
61 	if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) {
62 		/* Maximum bo size is the unpinned gtt size since we use the gtt to
63 		 * handle vram to system pool migrations.
64 		 */
65 		max_size = adev->mc.gtt_size - adev->gart_pin_size;
66 		if (size > max_size) {
67 			DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
68 				  size >> 20, max_size >> 20);
69 			return -ENOMEM;
70 		}
71 	}
72 retry:
73 	r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
74 			     flags, NULL, NULL, &robj);
75 	if (r) {
76 		if (r != -ERESTARTSYS) {
77 			if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
78 				initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
79 				goto retry;
80 			}
81 			DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
82 				  size, initial_domain, alignment, r);
83 		}
84 		return r;
85 	}
86 	*obj = &robj->gem_base;
87 
88 	return 0;
89 }
90 
91 void amdgpu_gem_force_release(struct amdgpu_device *adev)
92 {
93 	struct drm_device *ddev = adev->ddev;
94 	struct drm_file *file;
95 
96 	mutex_lock(&ddev->filelist_mutex);
97 
98 	list_for_each_entry(file, &ddev->filelist, lhead) {
99 		struct drm_gem_object *gobj;
100 		int handle;
101 
102 		WARN_ONCE(1, "Still active user space clients!\n");
103 		spin_lock(&file->table_lock);
104 		idr_for_each_entry(&file->object_idr, gobj, handle) {
105 			WARN_ONCE(1, "And also active allocations!\n");
106 			drm_gem_object_unreference_unlocked(gobj);
107 		}
108 		idr_destroy(&file->object_idr);
109 		spin_unlock(&file->table_lock);
110 	}
111 
112 	mutex_unlock(&ddev->filelist_mutex);
113 }
114 
115 /*
116  * Call from drm_gem_handle_create which appear in both new and open ioctl
117  * case.
118  */
119 int amdgpu_gem_object_open(struct drm_gem_object *obj,
120 			   struct drm_file *file_priv)
121 {
122 	struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
123 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
124 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
125 	struct amdgpu_vm *vm = &fpriv->vm;
126 	struct amdgpu_bo_va *bo_va;
127 	int r;
128 	r = amdgpu_bo_reserve(abo, false);
129 	if (r)
130 		return r;
131 
132 	bo_va = amdgpu_vm_bo_find(vm, abo);
133 	if (!bo_va) {
134 		bo_va = amdgpu_vm_bo_add(adev, vm, abo);
135 	} else {
136 		++bo_va->ref_count;
137 	}
138 	amdgpu_bo_unreserve(abo);
139 	return 0;
140 }
141 
142 void amdgpu_gem_object_close(struct drm_gem_object *obj,
143 			     struct drm_file *file_priv)
144 {
145 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
146 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
147 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
148 	struct amdgpu_vm *vm = &fpriv->vm;
149 
150 	struct amdgpu_bo_list_entry vm_pd;
151 	struct list_head list, duplicates;
152 	struct ttm_validate_buffer tv;
153 	struct ww_acquire_ctx ticket;
154 	struct amdgpu_bo_va *bo_va;
155 	int r;
156 
157 	INIT_LIST_HEAD(&list);
158 	INIT_LIST_HEAD(&duplicates);
159 
160 	tv.bo = &bo->tbo;
161 	tv.shared = true;
162 	list_add(&tv.head, &list);
163 
164 	amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
165 
166 	r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
167 	if (r) {
168 		dev_err(adev->dev, "leaking bo va because "
169 			"we fail to reserve bo (%d)\n", r);
170 		return;
171 	}
172 	bo_va = amdgpu_vm_bo_find(vm, bo);
173 	if (bo_va) {
174 		if (--bo_va->ref_count == 0) {
175 			amdgpu_vm_bo_rmv(adev, bo_va);
176 		}
177 	}
178 	ttm_eu_backoff_reservation(&ticket, &list);
179 }
180 
181 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
182 {
183 	if (r == -EDEADLK) {
184 		r = amdgpu_gpu_reset(adev);
185 		if (!r)
186 			r = -EAGAIN;
187 	}
188 	return r;
189 }
190 
191 /*
192  * GEM ioctls.
193  */
194 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
195 			    struct drm_file *filp)
196 {
197 	struct amdgpu_device *adev = dev->dev_private;
198 	union drm_amdgpu_gem_create *args = data;
199 	uint64_t size = args->in.bo_size;
200 	struct drm_gem_object *gobj;
201 	uint32_t handle;
202 	bool kernel = false;
203 	int r;
204 
205 	/* reject invalid gem flags */
206 	if (args->in.domain_flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
207 				      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
208 				      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
209 				      AMDGPU_GEM_CREATE_VRAM_CLEARED|
210 				      AMDGPU_GEM_CREATE_SHADOW |
211 				      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
212 		r = -EINVAL;
213 		goto error_unlock;
214 	}
215 	/* reject invalid gem domains */
216 	if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
217 				 AMDGPU_GEM_DOMAIN_GTT |
218 				 AMDGPU_GEM_DOMAIN_VRAM |
219 				 AMDGPU_GEM_DOMAIN_GDS |
220 				 AMDGPU_GEM_DOMAIN_GWS |
221 				 AMDGPU_GEM_DOMAIN_OA)) {
222 		r = -EINVAL;
223 		goto error_unlock;
224 	}
225 
226 	/* create a gem object to contain this object in */
227 	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
228 	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
229 		kernel = true;
230 		if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
231 			size = size << AMDGPU_GDS_SHIFT;
232 		else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
233 			size = size << AMDGPU_GWS_SHIFT;
234 		else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
235 			size = size << AMDGPU_OA_SHIFT;
236 		else {
237 			r = -EINVAL;
238 			goto error_unlock;
239 		}
240 	}
241 	size = roundup(size, PAGE_SIZE);
242 
243 	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
244 				     (u32)(0xffffffff & args->in.domains),
245 				     args->in.domain_flags,
246 				     kernel, &gobj);
247 	if (r)
248 		goto error_unlock;
249 
250 	r = drm_gem_handle_create(filp, gobj, &handle);
251 	/* drop reference from allocate - handle holds it now */
252 	drm_gem_object_unreference_unlocked(gobj);
253 	if (r)
254 		goto error_unlock;
255 
256 	memset(args, 0, sizeof(*args));
257 	args->out.handle = handle;
258 	return 0;
259 
260 error_unlock:
261 	r = amdgpu_gem_handle_lockup(adev, r);
262 	return r;
263 }
264 
265 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
266 			     struct drm_file *filp)
267 {
268 	struct amdgpu_device *adev = dev->dev_private;
269 	struct drm_amdgpu_gem_userptr *args = data;
270 	struct drm_gem_object *gobj;
271 	struct amdgpu_bo *bo;
272 	uint32_t handle;
273 	int r;
274 
275 	if (offset_in_page(args->addr | args->size))
276 		return -EINVAL;
277 
278 	/* reject unknown flag values */
279 	if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
280 	    AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
281 	    AMDGPU_GEM_USERPTR_REGISTER))
282 		return -EINVAL;
283 
284 	if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
285 	     !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
286 
287 		/* if we want to write to it we must install a MMU notifier */
288 		return -EACCES;
289 	}
290 
291 	/* create a gem object to contain this object in */
292 	r = amdgpu_gem_object_create(adev, args->size, 0,
293 				     AMDGPU_GEM_DOMAIN_CPU, 0,
294 				     0, &gobj);
295 	if (r)
296 		goto handle_lockup;
297 
298 	bo = gem_to_amdgpu_bo(gobj);
299 	bo->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
300 	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
301 	r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
302 	if (r)
303 		goto release_object;
304 
305 	if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
306 		r = amdgpu_mn_register(bo, args->addr);
307 		if (r)
308 			goto release_object;
309 	}
310 
311 	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
312 		down_read(&current->mm->mmap_sem);
313 
314 		r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
315 						 bo->tbo.ttm->pages);
316 		if (r)
317 			goto unlock_mmap_sem;
318 
319 		r = amdgpu_bo_reserve(bo, true);
320 		if (r)
321 			goto free_pages;
322 
323 		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
324 		r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
325 		amdgpu_bo_unreserve(bo);
326 		if (r)
327 			goto free_pages;
328 
329 		up_read(&current->mm->mmap_sem);
330 	}
331 
332 	r = drm_gem_handle_create(filp, gobj, &handle);
333 	/* drop reference from allocate - handle holds it now */
334 	drm_gem_object_unreference_unlocked(gobj);
335 	if (r)
336 		goto handle_lockup;
337 
338 	args->handle = handle;
339 	return 0;
340 
341 free_pages:
342 	release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
343 
344 unlock_mmap_sem:
345 	up_read(&current->mm->mmap_sem);
346 
347 release_object:
348 	drm_gem_object_unreference_unlocked(gobj);
349 
350 handle_lockup:
351 	r = amdgpu_gem_handle_lockup(adev, r);
352 
353 	return r;
354 }
355 
356 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
357 			  struct drm_device *dev,
358 			  uint32_t handle, uint64_t *offset_p)
359 {
360 	struct drm_gem_object *gobj;
361 	struct amdgpu_bo *robj;
362 
363 	gobj = drm_gem_object_lookup(filp, handle);
364 	if (gobj == NULL) {
365 		return -ENOENT;
366 	}
367 	robj = gem_to_amdgpu_bo(gobj);
368 	if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
369 	    (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
370 		drm_gem_object_unreference_unlocked(gobj);
371 		return -EPERM;
372 	}
373 	*offset_p = amdgpu_bo_mmap_offset(robj);
374 	drm_gem_object_unreference_unlocked(gobj);
375 	return 0;
376 }
377 
378 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
379 			  struct drm_file *filp)
380 {
381 	union drm_amdgpu_gem_mmap *args = data;
382 	uint32_t handle = args->in.handle;
383 	memset(args, 0, sizeof(*args));
384 	return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
385 }
386 
387 /**
388  * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
389  *
390  * @timeout_ns: timeout in ns
391  *
392  * Calculate the timeout in jiffies from an absolute timeout in ns.
393  */
394 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
395 {
396 	unsigned long timeout_jiffies;
397 	ktime_t timeout;
398 
399 	/* clamp timeout if it's to large */
400 	if (((int64_t)timeout_ns) < 0)
401 		return MAX_SCHEDULE_TIMEOUT;
402 
403 	timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
404 	if (ktime_to_ns(timeout) < 0)
405 		return 0;
406 
407 	timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
408 	/*  clamp timeout to avoid unsigned-> signed overflow */
409 	if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
410 		return MAX_SCHEDULE_TIMEOUT - 1;
411 
412 	return timeout_jiffies;
413 }
414 
415 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
416 			      struct drm_file *filp)
417 {
418 	struct amdgpu_device *adev = dev->dev_private;
419 	union drm_amdgpu_gem_wait_idle *args = data;
420 	struct drm_gem_object *gobj;
421 	struct amdgpu_bo *robj;
422 	uint32_t handle = args->in.handle;
423 	unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
424 	int r = 0;
425 	long ret;
426 
427 	gobj = drm_gem_object_lookup(filp, handle);
428 	if (gobj == NULL) {
429 		return -ENOENT;
430 	}
431 	robj = gem_to_amdgpu_bo(gobj);
432 	ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
433 						  timeout);
434 
435 	/* ret == 0 means not signaled,
436 	 * ret > 0 means signaled
437 	 * ret < 0 means interrupted before timeout
438 	 */
439 	if (ret >= 0) {
440 		memset(args, 0, sizeof(*args));
441 		args->out.status = (ret == 0);
442 	} else
443 		r = ret;
444 
445 	drm_gem_object_unreference_unlocked(gobj);
446 	r = amdgpu_gem_handle_lockup(adev, r);
447 	return r;
448 }
449 
450 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
451 				struct drm_file *filp)
452 {
453 	struct drm_amdgpu_gem_metadata *args = data;
454 	struct drm_gem_object *gobj;
455 	struct amdgpu_bo *robj;
456 	int r = -1;
457 
458 	DRM_DEBUG("%d \n", args->handle);
459 	gobj = drm_gem_object_lookup(filp, args->handle);
460 	if (gobj == NULL)
461 		return -ENOENT;
462 	robj = gem_to_amdgpu_bo(gobj);
463 
464 	r = amdgpu_bo_reserve(robj, false);
465 	if (unlikely(r != 0))
466 		goto out;
467 
468 	if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
469 		amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
470 		r = amdgpu_bo_get_metadata(robj, args->data.data,
471 					   sizeof(args->data.data),
472 					   &args->data.data_size_bytes,
473 					   &args->data.flags);
474 	} else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
475 		if (args->data.data_size_bytes > sizeof(args->data.data)) {
476 			r = -EINVAL;
477 			goto unreserve;
478 		}
479 		r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
480 		if (!r)
481 			r = amdgpu_bo_set_metadata(robj, args->data.data,
482 						   args->data.data_size_bytes,
483 						   args->data.flags);
484 	}
485 
486 unreserve:
487 	amdgpu_bo_unreserve(robj);
488 out:
489 	drm_gem_object_unreference_unlocked(gobj);
490 	return r;
491 }
492 
493 static int amdgpu_gem_va_check(void *param, struct amdgpu_bo *bo)
494 {
495 	/* if anything is swapped out don't swap it in here,
496 	   just abort and wait for the next CS */
497 	if (!amdgpu_bo_gpu_accessible(bo))
498 		return -ERESTARTSYS;
499 
500 	if (bo->shadow && !amdgpu_bo_gpu_accessible(bo->shadow))
501 		return -ERESTARTSYS;
502 
503 	return 0;
504 }
505 
506 /**
507  * amdgpu_gem_va_update_vm -update the bo_va in its VM
508  *
509  * @adev: amdgpu_device pointer
510  * @bo_va: bo_va to update
511  * @list: validation list
512  * @operation: map or unmap
513  *
514  * Update the bo_va directly after setting its address. Errors are not
515  * vital here, so they are not reported back to userspace.
516  */
517 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
518 				    struct amdgpu_bo_va *bo_va,
519 				    struct list_head *list,
520 				    uint32_t operation)
521 {
522 	struct ttm_validate_buffer *entry;
523 	int r = -ERESTARTSYS;
524 
525 	list_for_each_entry(entry, list, head) {
526 		struct amdgpu_bo *bo =
527 			container_of(entry->bo, struct amdgpu_bo, tbo);
528 		if (amdgpu_gem_va_check(NULL, bo))
529 			goto error;
530 	}
531 
532 	r = amdgpu_vm_validate_pt_bos(adev, bo_va->vm, amdgpu_gem_va_check,
533 				      NULL);
534 	if (r)
535 		goto error;
536 
537 	r = amdgpu_vm_update_page_directory(adev, bo_va->vm);
538 	if (r)
539 		goto error;
540 
541 	r = amdgpu_vm_clear_freed(adev, bo_va->vm);
542 	if (r)
543 		goto error;
544 
545 	if (operation == AMDGPU_VA_OP_MAP)
546 		r = amdgpu_vm_bo_update(adev, bo_va, false);
547 
548 error:
549 	if (r && r != -ERESTARTSYS)
550 		DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
551 }
552 
553 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
554 			  struct drm_file *filp)
555 {
556 	struct drm_amdgpu_gem_va *args = data;
557 	struct drm_gem_object *gobj;
558 	struct amdgpu_device *adev = dev->dev_private;
559 	struct amdgpu_fpriv *fpriv = filp->driver_priv;
560 	struct amdgpu_bo *abo;
561 	struct amdgpu_bo_va *bo_va;
562 	struct amdgpu_bo_list_entry vm_pd;
563 	struct ttm_validate_buffer tv;
564 	struct ww_acquire_ctx ticket;
565 	struct list_head list;
566 	uint32_t invalid_flags, va_flags = 0;
567 	int r = 0;
568 
569 	if (!adev->vm_manager.enabled)
570 		return -ENOTTY;
571 
572 	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
573 		dev_err(&dev->pdev->dev,
574 			"va_address 0x%lX is in reserved area 0x%X\n",
575 			(unsigned long)args->va_address,
576 			AMDGPU_VA_RESERVED_SIZE);
577 		return -EINVAL;
578 	}
579 
580 	invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE |
581 			AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE);
582 	if ((args->flags & invalid_flags)) {
583 		dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
584 			args->flags, invalid_flags);
585 		return -EINVAL;
586 	}
587 
588 	switch (args->operation) {
589 	case AMDGPU_VA_OP_MAP:
590 	case AMDGPU_VA_OP_UNMAP:
591 		break;
592 	default:
593 		dev_err(&dev->pdev->dev, "unsupported operation %d\n",
594 			args->operation);
595 		return -EINVAL;
596 	}
597 
598 	gobj = drm_gem_object_lookup(filp, args->handle);
599 	if (gobj == NULL)
600 		return -ENOENT;
601 	abo = gem_to_amdgpu_bo(gobj);
602 	INIT_LIST_HEAD(&list);
603 	tv.bo = &abo->tbo;
604 	tv.shared = false;
605 	list_add(&tv.head, &list);
606 
607 	amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
608 
609 	r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
610 	if (r) {
611 		drm_gem_object_unreference_unlocked(gobj);
612 		return r;
613 	}
614 
615 	bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
616 	if (!bo_va) {
617 		ttm_eu_backoff_reservation(&ticket, &list);
618 		drm_gem_object_unreference_unlocked(gobj);
619 		return -ENOENT;
620 	}
621 
622 	switch (args->operation) {
623 	case AMDGPU_VA_OP_MAP:
624 		if (args->flags & AMDGPU_VM_PAGE_READABLE)
625 			va_flags |= AMDGPU_PTE_READABLE;
626 		if (args->flags & AMDGPU_VM_PAGE_WRITEABLE)
627 			va_flags |= AMDGPU_PTE_WRITEABLE;
628 		if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE)
629 			va_flags |= AMDGPU_PTE_EXECUTABLE;
630 		r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
631 				     args->offset_in_bo, args->map_size,
632 				     va_flags);
633 		break;
634 	case AMDGPU_VA_OP_UNMAP:
635 		r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
636 		break;
637 	default:
638 		break;
639 	}
640 	if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) &&
641 	    !amdgpu_vm_debug)
642 		amdgpu_gem_va_update_vm(adev, bo_va, &list, args->operation);
643 	ttm_eu_backoff_reservation(&ticket, &list);
644 
645 	drm_gem_object_unreference_unlocked(gobj);
646 	return r;
647 }
648 
649 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
650 			struct drm_file *filp)
651 {
652 	struct drm_amdgpu_gem_op *args = data;
653 	struct drm_gem_object *gobj;
654 	struct amdgpu_bo *robj;
655 	int r;
656 
657 	gobj = drm_gem_object_lookup(filp, args->handle);
658 	if (gobj == NULL) {
659 		return -ENOENT;
660 	}
661 	robj = gem_to_amdgpu_bo(gobj);
662 
663 	r = amdgpu_bo_reserve(robj, false);
664 	if (unlikely(r))
665 		goto out;
666 
667 	switch (args->op) {
668 	case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
669 		struct drm_amdgpu_gem_create_in info;
670 		void __user *out = (void __user *)(long)args->value;
671 
672 		info.bo_size = robj->gem_base.size;
673 		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
674 		info.domains = robj->prefered_domains;
675 		info.domain_flags = robj->flags;
676 		amdgpu_bo_unreserve(robj);
677 		if (copy_to_user(out, &info, sizeof(info)))
678 			r = -EFAULT;
679 		break;
680 	}
681 	case AMDGPU_GEM_OP_SET_PLACEMENT:
682 		if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
683 			r = -EPERM;
684 			amdgpu_bo_unreserve(robj);
685 			break;
686 		}
687 		robj->prefered_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
688 							AMDGPU_GEM_DOMAIN_GTT |
689 							AMDGPU_GEM_DOMAIN_CPU);
690 		robj->allowed_domains = robj->prefered_domains;
691 		if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
692 			robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
693 
694 		amdgpu_bo_unreserve(robj);
695 		break;
696 	default:
697 		amdgpu_bo_unreserve(robj);
698 		r = -EINVAL;
699 	}
700 
701 out:
702 	drm_gem_object_unreference_unlocked(gobj);
703 	return r;
704 }
705 
706 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
707 			    struct drm_device *dev,
708 			    struct drm_mode_create_dumb *args)
709 {
710 	struct amdgpu_device *adev = dev->dev_private;
711 	struct drm_gem_object *gobj;
712 	uint32_t handle;
713 	int r;
714 
715 	args->pitch = amdgpu_align_pitch(adev, args->width,
716 					 DIV_ROUND_UP(args->bpp, 8), 0);
717 	args->size = (u64)args->pitch * args->height;
718 	args->size = ALIGN(args->size, PAGE_SIZE);
719 
720 	r = amdgpu_gem_object_create(adev, args->size, 0,
721 				     AMDGPU_GEM_DOMAIN_VRAM,
722 				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
723 				     ttm_bo_type_device,
724 				     &gobj);
725 	if (r)
726 		return -ENOMEM;
727 
728 	r = drm_gem_handle_create(file_priv, gobj, &handle);
729 	/* drop reference from allocate - handle holds it now */
730 	drm_gem_object_unreference_unlocked(gobj);
731 	if (r) {
732 		return r;
733 	}
734 	args->handle = handle;
735 	return 0;
736 }
737 
738 #if defined(CONFIG_DEBUG_FS)
739 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
740 {
741 	struct drm_gem_object *gobj = ptr;
742 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
743 	struct seq_file *m = data;
744 
745 	unsigned domain;
746 	const char *placement;
747 	unsigned pin_count;
748 
749 	domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
750 	switch (domain) {
751 	case AMDGPU_GEM_DOMAIN_VRAM:
752 		placement = "VRAM";
753 		break;
754 	case AMDGPU_GEM_DOMAIN_GTT:
755 		placement = " GTT";
756 		break;
757 	case AMDGPU_GEM_DOMAIN_CPU:
758 	default:
759 		placement = " CPU";
760 		break;
761 	}
762 	seq_printf(m, "\t0x%08x: %12ld byte %s @ 0x%010Lx",
763 		   id, amdgpu_bo_size(bo), placement,
764 		   amdgpu_bo_gpu_offset(bo));
765 
766 	pin_count = ACCESS_ONCE(bo->pin_count);
767 	if (pin_count)
768 		seq_printf(m, " pin count %d", pin_count);
769 	seq_printf(m, "\n");
770 
771 	return 0;
772 }
773 
774 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
775 {
776 	struct drm_info_node *node = (struct drm_info_node *)m->private;
777 	struct drm_device *dev = node->minor->dev;
778 	struct drm_file *file;
779 	int r;
780 
781 	r = mutex_lock_interruptible(&dev->filelist_mutex);
782 	if (r)
783 		return r;
784 
785 	list_for_each_entry(file, &dev->filelist, lhead) {
786 		struct task_struct *task;
787 
788 		/*
789 		 * Although we have a valid reference on file->pid, that does
790 		 * not guarantee that the task_struct who called get_pid() is
791 		 * still alive (e.g. get_pid(current) => fork() => exit()).
792 		 * Therefore, we need to protect this ->comm access using RCU.
793 		 */
794 		rcu_read_lock();
795 		task = pid_task(file->pid, PIDTYPE_PID);
796 		seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
797 			   task ? task->comm : "<unknown>");
798 		rcu_read_unlock();
799 
800 		spin_lock(&file->table_lock);
801 		idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
802 		spin_unlock(&file->table_lock);
803 	}
804 
805 	mutex_unlock(&dev->filelist_mutex);
806 	return 0;
807 }
808 
809 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
810 	{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
811 };
812 #endif
813 
814 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
815 {
816 #if defined(CONFIG_DEBUG_FS)
817 	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
818 #endif
819 	return 0;
820 }
821