1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_gem_ttm_helper.h> 37 38 #include "amdgpu.h" 39 #include "amdgpu_display.h" 40 #include "amdgpu_dma_buf.h" 41 #include "amdgpu_hmm.h" 42 #include "amdgpu_xgmi.h" 43 44 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; 45 46 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) 47 { 48 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 49 struct drm_device *ddev = bo->base.dev; 50 vm_fault_t ret; 51 int idx; 52 53 ret = ttm_bo_vm_reserve(bo, vmf); 54 if (ret) 55 return ret; 56 57 if (drm_dev_enter(ddev, &idx)) { 58 ret = amdgpu_bo_fault_reserve_notify(bo); 59 if (ret) { 60 drm_dev_exit(idx); 61 goto unlock; 62 } 63 64 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 65 TTM_BO_VM_NUM_PREFAULT); 66 67 drm_dev_exit(idx); 68 } else { 69 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); 70 } 71 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 72 return ret; 73 74 unlock: 75 dma_resv_unlock(bo->base.resv); 76 return ret; 77 } 78 79 static const struct vm_operations_struct amdgpu_gem_vm_ops = { 80 .fault = amdgpu_gem_fault, 81 .open = ttm_bo_vm_open, 82 .close = ttm_bo_vm_close, 83 .access = ttm_bo_vm_access 84 }; 85 86 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 87 { 88 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 89 90 if (robj) { 91 amdgpu_hmm_unregister(robj); 92 amdgpu_bo_unref(&robj); 93 } 94 } 95 96 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 97 int alignment, u32 initial_domain, 98 u64 flags, enum ttm_bo_type type, 99 struct dma_resv *resv, 100 struct drm_gem_object **obj) 101 { 102 struct amdgpu_bo *bo; 103 struct amdgpu_bo_user *ubo; 104 struct amdgpu_bo_param bp; 105 int r; 106 107 memset(&bp, 0, sizeof(bp)); 108 *obj = NULL; 109 110 bp.size = size; 111 bp.byte_align = alignment; 112 bp.type = type; 113 bp.resv = resv; 114 bp.preferred_domain = initial_domain; 115 bp.flags = flags; 116 bp.domain = initial_domain; 117 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 118 119 r = amdgpu_bo_create_user(adev, &bp, &ubo); 120 if (r) 121 return r; 122 123 bo = &ubo->bo; 124 *obj = &bo->tbo.base; 125 (*obj)->funcs = &amdgpu_gem_object_funcs; 126 127 return 0; 128 } 129 130 void amdgpu_gem_force_release(struct amdgpu_device *adev) 131 { 132 struct drm_device *ddev = adev_to_drm(adev); 133 struct drm_file *file; 134 135 mutex_lock(&ddev->filelist_mutex); 136 137 list_for_each_entry(file, &ddev->filelist, lhead) { 138 struct drm_gem_object *gobj; 139 int handle; 140 141 WARN_ONCE(1, "Still active user space clients!\n"); 142 spin_lock(&file->table_lock); 143 idr_for_each_entry(&file->object_idr, gobj, handle) { 144 WARN_ONCE(1, "And also active allocations!\n"); 145 drm_gem_object_put(gobj); 146 } 147 idr_destroy(&file->object_idr); 148 spin_unlock(&file->table_lock); 149 } 150 151 mutex_unlock(&ddev->filelist_mutex); 152 } 153 154 /* 155 * Call from drm_gem_handle_create which appear in both new and open ioctl 156 * case. 157 */ 158 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 159 struct drm_file *file_priv) 160 { 161 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 162 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 163 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 164 struct amdgpu_vm *vm = &fpriv->vm; 165 struct amdgpu_bo_va *bo_va; 166 struct mm_struct *mm; 167 int r; 168 169 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 170 if (mm && mm != current->mm) 171 return -EPERM; 172 173 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 174 abo->tbo.base.resv != vm->root.bo->tbo.base.resv) 175 return -EPERM; 176 177 r = amdgpu_bo_reserve(abo, false); 178 if (r) 179 return r; 180 181 bo_va = amdgpu_vm_bo_find(vm, abo); 182 if (!bo_va) { 183 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 184 } else { 185 ++bo_va->ref_count; 186 } 187 amdgpu_bo_unreserve(abo); 188 return 0; 189 } 190 191 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 192 struct drm_file *file_priv) 193 { 194 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 195 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 196 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 197 struct amdgpu_vm *vm = &fpriv->vm; 198 199 struct amdgpu_bo_list_entry vm_pd; 200 struct list_head list, duplicates; 201 struct dma_fence *fence = NULL; 202 struct ttm_validate_buffer tv; 203 struct ww_acquire_ctx ticket; 204 struct amdgpu_bo_va *bo_va; 205 long r; 206 207 INIT_LIST_HEAD(&list); 208 INIT_LIST_HEAD(&duplicates); 209 210 tv.bo = &bo->tbo; 211 tv.num_shared = 2; 212 list_add(&tv.head, &list); 213 214 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 215 216 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 217 if (r) { 218 dev_err(adev->dev, "leaking bo va because " 219 "we fail to reserve bo (%ld)\n", r); 220 return; 221 } 222 bo_va = amdgpu_vm_bo_find(vm, bo); 223 if (!bo_va || --bo_va->ref_count) 224 goto out_unlock; 225 226 amdgpu_vm_bo_del(adev, bo_va); 227 if (!amdgpu_vm_ready(vm)) 228 goto out_unlock; 229 230 r = amdgpu_vm_clear_freed(adev, vm, &fence); 231 if (r || !fence) 232 goto out_unlock; 233 234 amdgpu_bo_fence(bo, fence, true); 235 dma_fence_put(fence); 236 237 out_unlock: 238 if (unlikely(r < 0)) 239 dev_err(adev->dev, "failed to clear page " 240 "tables on GEM object close (%ld)\n", r); 241 ttm_eu_backoff_reservation(&ticket, &list); 242 } 243 244 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) 245 { 246 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 247 248 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 249 return -EPERM; 250 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 251 return -EPERM; 252 253 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings 254 * for debugger access to invisible VRAM. Should have used MAP_SHARED 255 * instead. Clearing VM_MAYWRITE prevents the mapping from ever 256 * becoming writable and makes is_cow_mapping(vm_flags) false. 257 */ 258 if (is_cow_mapping(vma->vm_flags) && 259 !(vma->vm_flags & VM_ACCESS_FLAGS)) 260 vma->vm_flags &= ~VM_MAYWRITE; 261 262 return drm_gem_ttm_mmap(obj, vma); 263 } 264 265 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 266 .free = amdgpu_gem_object_free, 267 .open = amdgpu_gem_object_open, 268 .close = amdgpu_gem_object_close, 269 .export = amdgpu_gem_prime_export, 270 .vmap = drm_gem_ttm_vmap, 271 .vunmap = drm_gem_ttm_vunmap, 272 .mmap = amdgpu_gem_object_mmap, 273 .vm_ops = &amdgpu_gem_vm_ops, 274 }; 275 276 /* 277 * GEM ioctls. 278 */ 279 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 280 struct drm_file *filp) 281 { 282 struct amdgpu_device *adev = drm_to_adev(dev); 283 struct amdgpu_fpriv *fpriv = filp->driver_priv; 284 struct amdgpu_vm *vm = &fpriv->vm; 285 union drm_amdgpu_gem_create *args = data; 286 uint64_t flags = args->in.domain_flags; 287 uint64_t size = args->in.bo_size; 288 struct dma_resv *resv = NULL; 289 struct drm_gem_object *gobj; 290 uint32_t handle, initial_domain; 291 int r; 292 293 /* reject invalid gem flags */ 294 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 295 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 296 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 297 AMDGPU_GEM_CREATE_VRAM_CLEARED | 298 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 299 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 300 AMDGPU_GEM_CREATE_ENCRYPTED | 301 AMDGPU_GEM_CREATE_DISCARDABLE)) 302 return -EINVAL; 303 304 /* reject invalid gem domains */ 305 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 306 return -EINVAL; 307 308 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 309 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 310 return -EINVAL; 311 } 312 313 /* create a gem object to contain this object in */ 314 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 315 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 316 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 317 /* if gds bo is created from user space, it must be 318 * passed to bo list 319 */ 320 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 321 return -EINVAL; 322 } 323 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 324 } 325 326 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 327 r = amdgpu_bo_reserve(vm->root.bo, false); 328 if (r) 329 return r; 330 331 resv = vm->root.bo->tbo.base.resv; 332 } 333 334 initial_domain = (u32)(0xffffffff & args->in.domains); 335 retry: 336 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 337 initial_domain, 338 flags, ttm_bo_type_device, resv, &gobj); 339 if (r && r != -ERESTARTSYS) { 340 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 341 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 342 goto retry; 343 } 344 345 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 346 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 347 goto retry; 348 } 349 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 350 size, initial_domain, args->in.alignment, r); 351 } 352 353 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 354 if (!r) { 355 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 356 357 abo->parent = amdgpu_bo_ref(vm->root.bo); 358 } 359 amdgpu_bo_unreserve(vm->root.bo); 360 } 361 if (r) 362 return r; 363 364 r = drm_gem_handle_create(filp, gobj, &handle); 365 /* drop reference from allocate - handle holds it now */ 366 drm_gem_object_put(gobj); 367 if (r) 368 return r; 369 370 memset(args, 0, sizeof(*args)); 371 args->out.handle = handle; 372 return 0; 373 } 374 375 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 376 struct drm_file *filp) 377 { 378 struct ttm_operation_ctx ctx = { true, false }; 379 struct amdgpu_device *adev = drm_to_adev(dev); 380 struct drm_amdgpu_gem_userptr *args = data; 381 struct drm_gem_object *gobj; 382 struct hmm_range *range; 383 struct amdgpu_bo *bo; 384 uint32_t handle; 385 int r; 386 387 args->addr = untagged_addr(args->addr); 388 389 if (offset_in_page(args->addr | args->size)) 390 return -EINVAL; 391 392 /* reject unknown flag values */ 393 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 394 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 395 AMDGPU_GEM_USERPTR_REGISTER)) 396 return -EINVAL; 397 398 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 399 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 400 401 /* if we want to write to it we must install a MMU notifier */ 402 return -EACCES; 403 } 404 405 /* create a gem object to contain this object in */ 406 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 407 0, ttm_bo_type_device, NULL, &gobj); 408 if (r) 409 return r; 410 411 bo = gem_to_amdgpu_bo(gobj); 412 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 413 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 414 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 415 if (r) 416 goto release_object; 417 418 r = amdgpu_hmm_register(bo, args->addr); 419 if (r) 420 goto release_object; 421 422 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 423 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, 424 &range); 425 if (r) 426 goto release_object; 427 428 r = amdgpu_bo_reserve(bo, true); 429 if (r) 430 goto user_pages_done; 431 432 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 433 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 434 amdgpu_bo_unreserve(bo); 435 if (r) 436 goto user_pages_done; 437 } 438 439 r = drm_gem_handle_create(filp, gobj, &handle); 440 if (r) 441 goto user_pages_done; 442 443 args->handle = handle; 444 445 user_pages_done: 446 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 447 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 448 449 release_object: 450 drm_gem_object_put(gobj); 451 452 return r; 453 } 454 455 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 456 struct drm_device *dev, 457 uint32_t handle, uint64_t *offset_p) 458 { 459 struct drm_gem_object *gobj; 460 struct amdgpu_bo *robj; 461 462 gobj = drm_gem_object_lookup(filp, handle); 463 if (gobj == NULL) { 464 return -ENOENT; 465 } 466 robj = gem_to_amdgpu_bo(gobj); 467 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 468 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 469 drm_gem_object_put(gobj); 470 return -EPERM; 471 } 472 *offset_p = amdgpu_bo_mmap_offset(robj); 473 drm_gem_object_put(gobj); 474 return 0; 475 } 476 477 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 478 struct drm_file *filp) 479 { 480 union drm_amdgpu_gem_mmap *args = data; 481 uint32_t handle = args->in.handle; 482 memset(args, 0, sizeof(*args)); 483 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 484 } 485 486 /** 487 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 488 * 489 * @timeout_ns: timeout in ns 490 * 491 * Calculate the timeout in jiffies from an absolute timeout in ns. 492 */ 493 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 494 { 495 unsigned long timeout_jiffies; 496 ktime_t timeout; 497 498 /* clamp timeout if it's to large */ 499 if (((int64_t)timeout_ns) < 0) 500 return MAX_SCHEDULE_TIMEOUT; 501 502 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 503 if (ktime_to_ns(timeout) < 0) 504 return 0; 505 506 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 507 /* clamp timeout to avoid unsigned-> signed overflow */ 508 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 509 return MAX_SCHEDULE_TIMEOUT - 1; 510 511 return timeout_jiffies; 512 } 513 514 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 515 struct drm_file *filp) 516 { 517 union drm_amdgpu_gem_wait_idle *args = data; 518 struct drm_gem_object *gobj; 519 struct amdgpu_bo *robj; 520 uint32_t handle = args->in.handle; 521 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 522 int r = 0; 523 long ret; 524 525 gobj = drm_gem_object_lookup(filp, handle); 526 if (gobj == NULL) { 527 return -ENOENT; 528 } 529 robj = gem_to_amdgpu_bo(gobj); 530 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, 531 true, timeout); 532 533 /* ret == 0 means not signaled, 534 * ret > 0 means signaled 535 * ret < 0 means interrupted before timeout 536 */ 537 if (ret >= 0) { 538 memset(args, 0, sizeof(*args)); 539 args->out.status = (ret == 0); 540 } else 541 r = ret; 542 543 drm_gem_object_put(gobj); 544 return r; 545 } 546 547 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 548 struct drm_file *filp) 549 { 550 struct drm_amdgpu_gem_metadata *args = data; 551 struct drm_gem_object *gobj; 552 struct amdgpu_bo *robj; 553 int r = -1; 554 555 DRM_DEBUG("%d \n", args->handle); 556 gobj = drm_gem_object_lookup(filp, args->handle); 557 if (gobj == NULL) 558 return -ENOENT; 559 robj = gem_to_amdgpu_bo(gobj); 560 561 r = amdgpu_bo_reserve(robj, false); 562 if (unlikely(r != 0)) 563 goto out; 564 565 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 566 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 567 r = amdgpu_bo_get_metadata(robj, args->data.data, 568 sizeof(args->data.data), 569 &args->data.data_size_bytes, 570 &args->data.flags); 571 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 572 if (args->data.data_size_bytes > sizeof(args->data.data)) { 573 r = -EINVAL; 574 goto unreserve; 575 } 576 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 577 if (!r) 578 r = amdgpu_bo_set_metadata(robj, args->data.data, 579 args->data.data_size_bytes, 580 args->data.flags); 581 } 582 583 unreserve: 584 amdgpu_bo_unreserve(robj); 585 out: 586 drm_gem_object_put(gobj); 587 return r; 588 } 589 590 /** 591 * amdgpu_gem_va_update_vm -update the bo_va in its VM 592 * 593 * @adev: amdgpu_device pointer 594 * @vm: vm to update 595 * @bo_va: bo_va to update 596 * @operation: map, unmap or clear 597 * 598 * Update the bo_va directly after setting its address. Errors are not 599 * vital here, so they are not reported back to userspace. 600 */ 601 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 602 struct amdgpu_vm *vm, 603 struct amdgpu_bo_va *bo_va, 604 uint32_t operation) 605 { 606 int r; 607 608 if (!amdgpu_vm_ready(vm)) 609 return; 610 611 r = amdgpu_vm_clear_freed(adev, vm, NULL); 612 if (r) 613 goto error; 614 615 if (operation == AMDGPU_VA_OP_MAP || 616 operation == AMDGPU_VA_OP_REPLACE) { 617 r = amdgpu_vm_bo_update(adev, bo_va, false); 618 if (r) 619 goto error; 620 } 621 622 r = amdgpu_vm_update_pdes(adev, vm, false); 623 624 error: 625 if (r && r != -ERESTARTSYS) 626 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 627 } 628 629 /** 630 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 631 * 632 * @adev: amdgpu_device pointer 633 * @flags: GEM UAPI flags 634 * 635 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 636 */ 637 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 638 { 639 uint64_t pte_flag = 0; 640 641 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 642 pte_flag |= AMDGPU_PTE_EXECUTABLE; 643 if (flags & AMDGPU_VM_PAGE_READABLE) 644 pte_flag |= AMDGPU_PTE_READABLE; 645 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 646 pte_flag |= AMDGPU_PTE_WRITEABLE; 647 if (flags & AMDGPU_VM_PAGE_PRT) 648 pte_flag |= AMDGPU_PTE_PRT; 649 if (flags & AMDGPU_VM_PAGE_NOALLOC) 650 pte_flag |= AMDGPU_PTE_NOALLOC; 651 652 if (adev->gmc.gmc_funcs->map_mtype) 653 pte_flag |= amdgpu_gmc_map_mtype(adev, 654 flags & AMDGPU_VM_MTYPE_MASK); 655 656 return pte_flag; 657 } 658 659 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 660 struct drm_file *filp) 661 { 662 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 663 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 664 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK | 665 AMDGPU_VM_PAGE_NOALLOC; 666 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 667 AMDGPU_VM_PAGE_PRT; 668 669 struct drm_amdgpu_gem_va *args = data; 670 struct drm_gem_object *gobj; 671 struct amdgpu_device *adev = drm_to_adev(dev); 672 struct amdgpu_fpriv *fpriv = filp->driver_priv; 673 struct amdgpu_bo *abo; 674 struct amdgpu_bo_va *bo_va; 675 struct amdgpu_bo_list_entry vm_pd; 676 struct ttm_validate_buffer tv; 677 struct ww_acquire_ctx ticket; 678 struct list_head list, duplicates; 679 uint64_t va_flags; 680 uint64_t vm_size; 681 int r = 0; 682 683 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 684 dev_dbg(dev->dev, 685 "va_address 0x%LX is in reserved area 0x%LX\n", 686 args->va_address, AMDGPU_VA_RESERVED_SIZE); 687 return -EINVAL; 688 } 689 690 if (args->va_address >= AMDGPU_GMC_HOLE_START && 691 args->va_address < AMDGPU_GMC_HOLE_END) { 692 dev_dbg(dev->dev, 693 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 694 args->va_address, AMDGPU_GMC_HOLE_START, 695 AMDGPU_GMC_HOLE_END); 696 return -EINVAL; 697 } 698 699 args->va_address &= AMDGPU_GMC_HOLE_MASK; 700 701 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 702 vm_size -= AMDGPU_VA_RESERVED_SIZE; 703 if (args->va_address + args->map_size > vm_size) { 704 dev_dbg(dev->dev, 705 "va_address 0x%llx is in top reserved area 0x%llx\n", 706 args->va_address + args->map_size, vm_size); 707 return -EINVAL; 708 } 709 710 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 711 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 712 args->flags); 713 return -EINVAL; 714 } 715 716 switch (args->operation) { 717 case AMDGPU_VA_OP_MAP: 718 case AMDGPU_VA_OP_UNMAP: 719 case AMDGPU_VA_OP_CLEAR: 720 case AMDGPU_VA_OP_REPLACE: 721 break; 722 default: 723 dev_dbg(dev->dev, "unsupported operation %d\n", 724 args->operation); 725 return -EINVAL; 726 } 727 728 INIT_LIST_HEAD(&list); 729 INIT_LIST_HEAD(&duplicates); 730 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 731 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 732 gobj = drm_gem_object_lookup(filp, args->handle); 733 if (gobj == NULL) 734 return -ENOENT; 735 abo = gem_to_amdgpu_bo(gobj); 736 tv.bo = &abo->tbo; 737 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 738 tv.num_shared = 1; 739 else 740 tv.num_shared = 0; 741 list_add(&tv.head, &list); 742 } else { 743 gobj = NULL; 744 abo = NULL; 745 } 746 747 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 748 749 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 750 if (r) 751 goto error_unref; 752 753 if (abo) { 754 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 755 if (!bo_va) { 756 r = -ENOENT; 757 goto error_backoff; 758 } 759 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 760 bo_va = fpriv->prt_va; 761 } else { 762 bo_va = NULL; 763 } 764 765 switch (args->operation) { 766 case AMDGPU_VA_OP_MAP: 767 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 768 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 769 args->offset_in_bo, args->map_size, 770 va_flags); 771 break; 772 case AMDGPU_VA_OP_UNMAP: 773 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 774 break; 775 776 case AMDGPU_VA_OP_CLEAR: 777 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 778 args->va_address, 779 args->map_size); 780 break; 781 case AMDGPU_VA_OP_REPLACE: 782 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 783 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 784 args->offset_in_bo, args->map_size, 785 va_flags); 786 break; 787 default: 788 break; 789 } 790 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 791 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 792 args->operation); 793 794 error_backoff: 795 ttm_eu_backoff_reservation(&ticket, &list); 796 797 error_unref: 798 drm_gem_object_put(gobj); 799 return r; 800 } 801 802 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 803 struct drm_file *filp) 804 { 805 struct amdgpu_device *adev = drm_to_adev(dev); 806 struct drm_amdgpu_gem_op *args = data; 807 struct drm_gem_object *gobj; 808 struct amdgpu_vm_bo_base *base; 809 struct amdgpu_bo *robj; 810 int r; 811 812 gobj = drm_gem_object_lookup(filp, args->handle); 813 if (gobj == NULL) { 814 return -ENOENT; 815 } 816 robj = gem_to_amdgpu_bo(gobj); 817 818 r = amdgpu_bo_reserve(robj, false); 819 if (unlikely(r)) 820 goto out; 821 822 switch (args->op) { 823 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 824 struct drm_amdgpu_gem_create_in info; 825 void __user *out = u64_to_user_ptr(args->value); 826 827 info.bo_size = robj->tbo.base.size; 828 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; 829 info.domains = robj->preferred_domains; 830 info.domain_flags = robj->flags; 831 amdgpu_bo_unreserve(robj); 832 if (copy_to_user(out, &info, sizeof(info))) 833 r = -EFAULT; 834 break; 835 } 836 case AMDGPU_GEM_OP_SET_PLACEMENT: 837 if (robj->tbo.base.import_attach && 838 args->value & AMDGPU_GEM_DOMAIN_VRAM) { 839 r = -EINVAL; 840 amdgpu_bo_unreserve(robj); 841 break; 842 } 843 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 844 r = -EPERM; 845 amdgpu_bo_unreserve(robj); 846 break; 847 } 848 for (base = robj->vm_bo; base; base = base->next) 849 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 850 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { 851 r = -EINVAL; 852 amdgpu_bo_unreserve(robj); 853 goto out; 854 } 855 856 857 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 858 AMDGPU_GEM_DOMAIN_GTT | 859 AMDGPU_GEM_DOMAIN_CPU); 860 robj->allowed_domains = robj->preferred_domains; 861 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 862 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 863 864 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 865 amdgpu_vm_bo_invalidate(adev, robj, true); 866 867 amdgpu_bo_unreserve(robj); 868 break; 869 default: 870 amdgpu_bo_unreserve(robj); 871 r = -EINVAL; 872 } 873 874 out: 875 drm_gem_object_put(gobj); 876 return r; 877 } 878 879 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, 880 int width, 881 int cpp, 882 bool tiled) 883 { 884 int aligned = width; 885 int pitch_mask = 0; 886 887 switch (cpp) { 888 case 1: 889 pitch_mask = 255; 890 break; 891 case 2: 892 pitch_mask = 127; 893 break; 894 case 3: 895 case 4: 896 pitch_mask = 63; 897 break; 898 } 899 900 aligned += pitch_mask; 901 aligned &= ~pitch_mask; 902 return aligned * cpp; 903 } 904 905 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 906 struct drm_device *dev, 907 struct drm_mode_create_dumb *args) 908 { 909 struct amdgpu_device *adev = drm_to_adev(dev); 910 struct drm_gem_object *gobj; 911 uint32_t handle; 912 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 913 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 914 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 915 u32 domain; 916 int r; 917 918 /* 919 * The buffer returned from this function should be cleared, but 920 * it can only be done if the ring is enabled or we'll fail to 921 * create the buffer. 922 */ 923 if (adev->mman.buffer_funcs_enabled) 924 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 925 926 args->pitch = amdgpu_gem_align_pitch(adev, args->width, 927 DIV_ROUND_UP(args->bpp, 8), 0); 928 args->size = (u64)args->pitch * args->height; 929 args->size = ALIGN(args->size, PAGE_SIZE); 930 domain = amdgpu_bo_get_preferred_domain(adev, 931 amdgpu_display_supported_domains(adev, flags)); 932 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 933 ttm_bo_type_device, NULL, &gobj); 934 if (r) 935 return -ENOMEM; 936 937 r = drm_gem_handle_create(file_priv, gobj, &handle); 938 /* drop reference from allocate - handle holds it now */ 939 drm_gem_object_put(gobj); 940 if (r) { 941 return r; 942 } 943 args->handle = handle; 944 return 0; 945 } 946 947 #if defined(CONFIG_DEBUG_FS) 948 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) 949 { 950 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 951 struct drm_device *dev = adev_to_drm(adev); 952 struct drm_file *file; 953 int r; 954 955 r = mutex_lock_interruptible(&dev->filelist_mutex); 956 if (r) 957 return r; 958 959 list_for_each_entry(file, &dev->filelist, lhead) { 960 struct task_struct *task; 961 struct drm_gem_object *gobj; 962 int id; 963 964 /* 965 * Although we have a valid reference on file->pid, that does 966 * not guarantee that the task_struct who called get_pid() is 967 * still alive (e.g. get_pid(current) => fork() => exit()). 968 * Therefore, we need to protect this ->comm access using RCU. 969 */ 970 rcu_read_lock(); 971 task = pid_task(file->pid, PIDTYPE_PID); 972 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 973 task ? task->comm : "<unknown>"); 974 rcu_read_unlock(); 975 976 spin_lock(&file->table_lock); 977 idr_for_each_entry(&file->object_idr, gobj, id) { 978 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 979 980 amdgpu_bo_print_info(id, bo, m); 981 } 982 spin_unlock(&file->table_lock); 983 } 984 985 mutex_unlock(&dev->filelist_mutex); 986 return 0; 987 } 988 989 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); 990 991 #endif 992 993 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 994 { 995 #if defined(CONFIG_DEBUG_FS) 996 struct drm_minor *minor = adev_to_drm(adev)->primary; 997 struct dentry *root = minor->debugfs_root; 998 999 debugfs_create_file("amdgpu_gem_info", 0444, root, adev, 1000 &amdgpu_debugfs_gem_info_fops); 1001 #endif 1002 } 1003