1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_drv.h> 36 #include <drm/drm_gem_ttm_helper.h> 37 38 #include "amdgpu.h" 39 #include "amdgpu_display.h" 40 #include "amdgpu_dma_buf.h" 41 #include "amdgpu_hmm.h" 42 #include "amdgpu_xgmi.h" 43 44 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; 45 46 static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) 47 { 48 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 49 struct drm_device *ddev = bo->base.dev; 50 vm_fault_t ret; 51 int idx; 52 53 ret = ttm_bo_vm_reserve(bo, vmf); 54 if (ret) 55 return ret; 56 57 if (drm_dev_enter(ddev, &idx)) { 58 ret = amdgpu_bo_fault_reserve_notify(bo); 59 if (ret) { 60 drm_dev_exit(idx); 61 goto unlock; 62 } 63 64 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 65 TTM_BO_VM_NUM_PREFAULT); 66 67 drm_dev_exit(idx); 68 } else { 69 ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); 70 } 71 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 72 return ret; 73 74 unlock: 75 dma_resv_unlock(bo->base.resv); 76 return ret; 77 } 78 79 static const struct vm_operations_struct amdgpu_gem_vm_ops = { 80 .fault = amdgpu_gem_fault, 81 .open = ttm_bo_vm_open, 82 .close = ttm_bo_vm_close, 83 .access = ttm_bo_vm_access 84 }; 85 86 static void amdgpu_gem_object_free(struct drm_gem_object *gobj) 87 { 88 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 89 90 if (robj) { 91 amdgpu_hmm_unregister(robj); 92 amdgpu_bo_unref(&robj); 93 } 94 } 95 96 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 97 int alignment, u32 initial_domain, 98 u64 flags, enum ttm_bo_type type, 99 struct dma_resv *resv, 100 struct drm_gem_object **obj) 101 { 102 struct amdgpu_bo *bo; 103 struct amdgpu_bo_user *ubo; 104 struct amdgpu_bo_param bp; 105 int r; 106 107 memset(&bp, 0, sizeof(bp)); 108 *obj = NULL; 109 110 bp.size = size; 111 bp.byte_align = alignment; 112 bp.type = type; 113 bp.resv = resv; 114 bp.preferred_domain = initial_domain; 115 bp.flags = flags; 116 bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU; 117 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 118 119 r = amdgpu_bo_create_user(adev, &bp, &ubo); 120 if (r) 121 return r; 122 123 bo = &ubo->bo; 124 *obj = &bo->tbo.base; 125 (*obj)->funcs = &amdgpu_gem_object_funcs; 126 127 return 0; 128 } 129 130 void amdgpu_gem_force_release(struct amdgpu_device *adev) 131 { 132 struct drm_device *ddev = adev_to_drm(adev); 133 struct drm_file *file; 134 135 mutex_lock(&ddev->filelist_mutex); 136 137 list_for_each_entry(file, &ddev->filelist, lhead) { 138 struct drm_gem_object *gobj; 139 int handle; 140 141 WARN_ONCE(1, "Still active user space clients!\n"); 142 spin_lock(&file->table_lock); 143 idr_for_each_entry(&file->object_idr, gobj, handle) { 144 WARN_ONCE(1, "And also active allocations!\n"); 145 drm_gem_object_put(gobj); 146 } 147 idr_destroy(&file->object_idr); 148 spin_unlock(&file->table_lock); 149 } 150 151 mutex_unlock(&ddev->filelist_mutex); 152 } 153 154 /* 155 * Call from drm_gem_handle_create which appear in both new and open ioctl 156 * case. 157 */ 158 static int amdgpu_gem_object_open(struct drm_gem_object *obj, 159 struct drm_file *file_priv) 160 { 161 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 162 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 163 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 164 struct amdgpu_vm *vm = &fpriv->vm; 165 struct amdgpu_bo_va *bo_va; 166 struct mm_struct *mm; 167 int r; 168 169 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 170 if (mm && mm != current->mm) 171 return -EPERM; 172 173 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 174 abo->tbo.base.resv != vm->root.bo->tbo.base.resv) 175 return -EPERM; 176 177 r = amdgpu_bo_reserve(abo, false); 178 if (r) 179 return r; 180 181 bo_va = amdgpu_vm_bo_find(vm, abo); 182 if (!bo_va) { 183 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 184 } else { 185 ++bo_va->ref_count; 186 } 187 amdgpu_bo_unreserve(abo); 188 return 0; 189 } 190 191 static void amdgpu_gem_object_close(struct drm_gem_object *obj, 192 struct drm_file *file_priv) 193 { 194 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 195 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 196 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 197 struct amdgpu_vm *vm = &fpriv->vm; 198 199 struct amdgpu_bo_list_entry vm_pd; 200 struct list_head list, duplicates; 201 struct dma_fence *fence = NULL; 202 struct ttm_validate_buffer tv; 203 struct ww_acquire_ctx ticket; 204 struct amdgpu_bo_va *bo_va; 205 long r; 206 207 INIT_LIST_HEAD(&list); 208 INIT_LIST_HEAD(&duplicates); 209 210 tv.bo = &bo->tbo; 211 tv.num_shared = 2; 212 list_add(&tv.head, &list); 213 214 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 215 216 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 217 if (r) { 218 dev_err(adev->dev, "leaking bo va because " 219 "we fail to reserve bo (%ld)\n", r); 220 return; 221 } 222 bo_va = amdgpu_vm_bo_find(vm, bo); 223 if (!bo_va || --bo_va->ref_count) 224 goto out_unlock; 225 226 amdgpu_vm_bo_del(adev, bo_va); 227 if (!amdgpu_vm_ready(vm)) 228 goto out_unlock; 229 230 r = amdgpu_vm_clear_freed(adev, vm, &fence); 231 if (r || !fence) 232 goto out_unlock; 233 234 amdgpu_bo_fence(bo, fence, true); 235 dma_fence_put(fence); 236 237 out_unlock: 238 if (unlikely(r < 0)) 239 dev_err(adev->dev, "failed to clear page " 240 "tables on GEM object close (%ld)\n", r); 241 ttm_eu_backoff_reservation(&ticket, &list); 242 } 243 244 static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) 245 { 246 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 247 248 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 249 return -EPERM; 250 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 251 return -EPERM; 252 253 /* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings 254 * for debugger access to invisible VRAM. Should have used MAP_SHARED 255 * instead. Clearing VM_MAYWRITE prevents the mapping from ever 256 * becoming writable and makes is_cow_mapping(vm_flags) false. 257 */ 258 if (is_cow_mapping(vma->vm_flags) && 259 !(vma->vm_flags & VM_ACCESS_FLAGS)) 260 vma->vm_flags &= ~VM_MAYWRITE; 261 262 return drm_gem_ttm_mmap(obj, vma); 263 } 264 265 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { 266 .free = amdgpu_gem_object_free, 267 .open = amdgpu_gem_object_open, 268 .close = amdgpu_gem_object_close, 269 .export = amdgpu_gem_prime_export, 270 .vmap = drm_gem_ttm_vmap, 271 .vunmap = drm_gem_ttm_vunmap, 272 .mmap = amdgpu_gem_object_mmap, 273 .vm_ops = &amdgpu_gem_vm_ops, 274 }; 275 276 /* 277 * GEM ioctls. 278 */ 279 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 280 struct drm_file *filp) 281 { 282 struct amdgpu_device *adev = drm_to_adev(dev); 283 struct amdgpu_fpriv *fpriv = filp->driver_priv; 284 struct amdgpu_vm *vm = &fpriv->vm; 285 union drm_amdgpu_gem_create *args = data; 286 uint64_t flags = args->in.domain_flags; 287 uint64_t size = args->in.bo_size; 288 struct dma_resv *resv = NULL; 289 struct drm_gem_object *gobj; 290 uint32_t handle, initial_domain; 291 int r; 292 293 /* reject invalid gem flags */ 294 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 295 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 296 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 297 AMDGPU_GEM_CREATE_VRAM_CLEARED | 298 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 299 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 300 AMDGPU_GEM_CREATE_ENCRYPTED | 301 AMDGPU_GEM_CREATE_DISCARDABLE)) 302 return -EINVAL; 303 304 /* reject invalid gem domains */ 305 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 306 return -EINVAL; 307 308 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 309 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 310 return -EINVAL; 311 } 312 313 /* create a gem object to contain this object in */ 314 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 315 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 316 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 317 /* if gds bo is created from user space, it must be 318 * passed to bo list 319 */ 320 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 321 return -EINVAL; 322 } 323 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 324 } 325 326 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 327 r = amdgpu_bo_reserve(vm->root.bo, false); 328 if (r) 329 return r; 330 331 resv = vm->root.bo->tbo.base.resv; 332 } 333 334 initial_domain = (u32)(0xffffffff & args->in.domains); 335 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 336 initial_domain, flags, ttm_bo_type_device, 337 resv, &gobj); 338 if (r && r != -ERESTARTSYS) { 339 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 340 size, initial_domain, args->in.alignment, r); 341 } 342 343 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 344 if (!r) { 345 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 346 347 abo->parent = amdgpu_bo_ref(vm->root.bo); 348 } 349 amdgpu_bo_unreserve(vm->root.bo); 350 } 351 if (r) 352 return r; 353 354 r = drm_gem_handle_create(filp, gobj, &handle); 355 /* drop reference from allocate - handle holds it now */ 356 drm_gem_object_put(gobj); 357 if (r) 358 return r; 359 360 memset(args, 0, sizeof(*args)); 361 args->out.handle = handle; 362 return 0; 363 } 364 365 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 366 struct drm_file *filp) 367 { 368 struct ttm_operation_ctx ctx = { true, false }; 369 struct amdgpu_device *adev = drm_to_adev(dev); 370 struct drm_amdgpu_gem_userptr *args = data; 371 struct drm_gem_object *gobj; 372 struct hmm_range *range; 373 struct amdgpu_bo *bo; 374 uint32_t handle; 375 int r; 376 377 args->addr = untagged_addr(args->addr); 378 379 if (offset_in_page(args->addr | args->size)) 380 return -EINVAL; 381 382 /* reject unknown flag values */ 383 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 384 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 385 AMDGPU_GEM_USERPTR_REGISTER)) 386 return -EINVAL; 387 388 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 389 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 390 391 /* if we want to write to it we must install a MMU notifier */ 392 return -EACCES; 393 } 394 395 /* create a gem object to contain this object in */ 396 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 397 0, ttm_bo_type_device, NULL, &gobj); 398 if (r) 399 return r; 400 401 bo = gem_to_amdgpu_bo(gobj); 402 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 403 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 404 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 405 if (r) 406 goto release_object; 407 408 r = amdgpu_hmm_register(bo, args->addr); 409 if (r) 410 goto release_object; 411 412 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 413 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, 414 &range); 415 if (r) 416 goto release_object; 417 418 r = amdgpu_bo_reserve(bo, true); 419 if (r) 420 goto user_pages_done; 421 422 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 423 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 424 amdgpu_bo_unreserve(bo); 425 if (r) 426 goto user_pages_done; 427 } 428 429 r = drm_gem_handle_create(filp, gobj, &handle); 430 if (r) 431 goto user_pages_done; 432 433 args->handle = handle; 434 435 user_pages_done: 436 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 437 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 438 439 release_object: 440 drm_gem_object_put(gobj); 441 442 return r; 443 } 444 445 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 446 struct drm_device *dev, 447 uint32_t handle, uint64_t *offset_p) 448 { 449 struct drm_gem_object *gobj; 450 struct amdgpu_bo *robj; 451 452 gobj = drm_gem_object_lookup(filp, handle); 453 if (gobj == NULL) { 454 return -ENOENT; 455 } 456 robj = gem_to_amdgpu_bo(gobj); 457 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 458 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 459 drm_gem_object_put(gobj); 460 return -EPERM; 461 } 462 *offset_p = amdgpu_bo_mmap_offset(robj); 463 drm_gem_object_put(gobj); 464 return 0; 465 } 466 467 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 468 struct drm_file *filp) 469 { 470 union drm_amdgpu_gem_mmap *args = data; 471 uint32_t handle = args->in.handle; 472 memset(args, 0, sizeof(*args)); 473 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 474 } 475 476 /** 477 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 478 * 479 * @timeout_ns: timeout in ns 480 * 481 * Calculate the timeout in jiffies from an absolute timeout in ns. 482 */ 483 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 484 { 485 unsigned long timeout_jiffies; 486 ktime_t timeout; 487 488 /* clamp timeout if it's to large */ 489 if (((int64_t)timeout_ns) < 0) 490 return MAX_SCHEDULE_TIMEOUT; 491 492 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 493 if (ktime_to_ns(timeout) < 0) 494 return 0; 495 496 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 497 /* clamp timeout to avoid unsigned-> signed overflow */ 498 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 499 return MAX_SCHEDULE_TIMEOUT - 1; 500 501 return timeout_jiffies; 502 } 503 504 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 505 struct drm_file *filp) 506 { 507 union drm_amdgpu_gem_wait_idle *args = data; 508 struct drm_gem_object *gobj; 509 struct amdgpu_bo *robj; 510 uint32_t handle = args->in.handle; 511 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 512 int r = 0; 513 long ret; 514 515 gobj = drm_gem_object_lookup(filp, handle); 516 if (gobj == NULL) { 517 return -ENOENT; 518 } 519 robj = gem_to_amdgpu_bo(gobj); 520 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, 521 true, timeout); 522 523 /* ret == 0 means not signaled, 524 * ret > 0 means signaled 525 * ret < 0 means interrupted before timeout 526 */ 527 if (ret >= 0) { 528 memset(args, 0, sizeof(*args)); 529 args->out.status = (ret == 0); 530 } else 531 r = ret; 532 533 drm_gem_object_put(gobj); 534 return r; 535 } 536 537 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 538 struct drm_file *filp) 539 { 540 struct drm_amdgpu_gem_metadata *args = data; 541 struct drm_gem_object *gobj; 542 struct amdgpu_bo *robj; 543 int r = -1; 544 545 DRM_DEBUG("%d \n", args->handle); 546 gobj = drm_gem_object_lookup(filp, args->handle); 547 if (gobj == NULL) 548 return -ENOENT; 549 robj = gem_to_amdgpu_bo(gobj); 550 551 r = amdgpu_bo_reserve(robj, false); 552 if (unlikely(r != 0)) 553 goto out; 554 555 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 556 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 557 r = amdgpu_bo_get_metadata(robj, args->data.data, 558 sizeof(args->data.data), 559 &args->data.data_size_bytes, 560 &args->data.flags); 561 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 562 if (args->data.data_size_bytes > sizeof(args->data.data)) { 563 r = -EINVAL; 564 goto unreserve; 565 } 566 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 567 if (!r) 568 r = amdgpu_bo_set_metadata(robj, args->data.data, 569 args->data.data_size_bytes, 570 args->data.flags); 571 } 572 573 unreserve: 574 amdgpu_bo_unreserve(robj); 575 out: 576 drm_gem_object_put(gobj); 577 return r; 578 } 579 580 /** 581 * amdgpu_gem_va_update_vm -update the bo_va in its VM 582 * 583 * @adev: amdgpu_device pointer 584 * @vm: vm to update 585 * @bo_va: bo_va to update 586 * @operation: map, unmap or clear 587 * 588 * Update the bo_va directly after setting its address. Errors are not 589 * vital here, so they are not reported back to userspace. 590 */ 591 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 592 struct amdgpu_vm *vm, 593 struct amdgpu_bo_va *bo_va, 594 uint32_t operation) 595 { 596 int r; 597 598 if (!amdgpu_vm_ready(vm)) 599 return; 600 601 r = amdgpu_vm_clear_freed(adev, vm, NULL); 602 if (r) 603 goto error; 604 605 if (operation == AMDGPU_VA_OP_MAP || 606 operation == AMDGPU_VA_OP_REPLACE) { 607 r = amdgpu_vm_bo_update(adev, bo_va, false); 608 if (r) 609 goto error; 610 } 611 612 r = amdgpu_vm_update_pdes(adev, vm, false); 613 614 error: 615 if (r && r != -ERESTARTSYS) 616 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 617 } 618 619 /** 620 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 621 * 622 * @adev: amdgpu_device pointer 623 * @flags: GEM UAPI flags 624 * 625 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 626 */ 627 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 628 { 629 uint64_t pte_flag = 0; 630 631 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 632 pte_flag |= AMDGPU_PTE_EXECUTABLE; 633 if (flags & AMDGPU_VM_PAGE_READABLE) 634 pte_flag |= AMDGPU_PTE_READABLE; 635 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 636 pte_flag |= AMDGPU_PTE_WRITEABLE; 637 if (flags & AMDGPU_VM_PAGE_PRT) 638 pte_flag |= AMDGPU_PTE_PRT; 639 if (flags & AMDGPU_VM_PAGE_NOALLOC) 640 pte_flag |= AMDGPU_PTE_NOALLOC; 641 642 if (adev->gmc.gmc_funcs->map_mtype) 643 pte_flag |= amdgpu_gmc_map_mtype(adev, 644 flags & AMDGPU_VM_MTYPE_MASK); 645 646 return pte_flag; 647 } 648 649 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 650 struct drm_file *filp) 651 { 652 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 653 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 654 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK | 655 AMDGPU_VM_PAGE_NOALLOC; 656 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 657 AMDGPU_VM_PAGE_PRT; 658 659 struct drm_amdgpu_gem_va *args = data; 660 struct drm_gem_object *gobj; 661 struct amdgpu_device *adev = drm_to_adev(dev); 662 struct amdgpu_fpriv *fpriv = filp->driver_priv; 663 struct amdgpu_bo *abo; 664 struct amdgpu_bo_va *bo_va; 665 struct amdgpu_bo_list_entry vm_pd; 666 struct ttm_validate_buffer tv; 667 struct ww_acquire_ctx ticket; 668 struct list_head list, duplicates; 669 uint64_t va_flags; 670 uint64_t vm_size; 671 int r = 0; 672 673 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 674 dev_dbg(dev->dev, 675 "va_address 0x%LX is in reserved area 0x%LX\n", 676 args->va_address, AMDGPU_VA_RESERVED_SIZE); 677 return -EINVAL; 678 } 679 680 if (args->va_address >= AMDGPU_GMC_HOLE_START && 681 args->va_address < AMDGPU_GMC_HOLE_END) { 682 dev_dbg(dev->dev, 683 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 684 args->va_address, AMDGPU_GMC_HOLE_START, 685 AMDGPU_GMC_HOLE_END); 686 return -EINVAL; 687 } 688 689 args->va_address &= AMDGPU_GMC_HOLE_MASK; 690 691 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 692 vm_size -= AMDGPU_VA_RESERVED_SIZE; 693 if (args->va_address + args->map_size > vm_size) { 694 dev_dbg(dev->dev, 695 "va_address 0x%llx is in top reserved area 0x%llx\n", 696 args->va_address + args->map_size, vm_size); 697 return -EINVAL; 698 } 699 700 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 701 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n", 702 args->flags); 703 return -EINVAL; 704 } 705 706 switch (args->operation) { 707 case AMDGPU_VA_OP_MAP: 708 case AMDGPU_VA_OP_UNMAP: 709 case AMDGPU_VA_OP_CLEAR: 710 case AMDGPU_VA_OP_REPLACE: 711 break; 712 default: 713 dev_dbg(dev->dev, "unsupported operation %d\n", 714 args->operation); 715 return -EINVAL; 716 } 717 718 INIT_LIST_HEAD(&list); 719 INIT_LIST_HEAD(&duplicates); 720 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 721 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 722 gobj = drm_gem_object_lookup(filp, args->handle); 723 if (gobj == NULL) 724 return -ENOENT; 725 abo = gem_to_amdgpu_bo(gobj); 726 tv.bo = &abo->tbo; 727 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 728 tv.num_shared = 1; 729 else 730 tv.num_shared = 0; 731 list_add(&tv.head, &list); 732 } else { 733 gobj = NULL; 734 abo = NULL; 735 } 736 737 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 738 739 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 740 if (r) 741 goto error_unref; 742 743 if (abo) { 744 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 745 if (!bo_va) { 746 r = -ENOENT; 747 goto error_backoff; 748 } 749 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 750 bo_va = fpriv->prt_va; 751 } else { 752 bo_va = NULL; 753 } 754 755 switch (args->operation) { 756 case AMDGPU_VA_OP_MAP: 757 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 758 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 759 args->offset_in_bo, args->map_size, 760 va_flags); 761 break; 762 case AMDGPU_VA_OP_UNMAP: 763 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 764 break; 765 766 case AMDGPU_VA_OP_CLEAR: 767 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 768 args->va_address, 769 args->map_size); 770 break; 771 case AMDGPU_VA_OP_REPLACE: 772 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 773 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 774 args->offset_in_bo, args->map_size, 775 va_flags); 776 break; 777 default: 778 break; 779 } 780 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 781 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 782 args->operation); 783 784 error_backoff: 785 ttm_eu_backoff_reservation(&ticket, &list); 786 787 error_unref: 788 drm_gem_object_put(gobj); 789 return r; 790 } 791 792 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 793 struct drm_file *filp) 794 { 795 struct amdgpu_device *adev = drm_to_adev(dev); 796 struct drm_amdgpu_gem_op *args = data; 797 struct drm_gem_object *gobj; 798 struct amdgpu_vm_bo_base *base; 799 struct amdgpu_bo *robj; 800 int r; 801 802 gobj = drm_gem_object_lookup(filp, args->handle); 803 if (gobj == NULL) { 804 return -ENOENT; 805 } 806 robj = gem_to_amdgpu_bo(gobj); 807 808 r = amdgpu_bo_reserve(robj, false); 809 if (unlikely(r)) 810 goto out; 811 812 switch (args->op) { 813 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 814 struct drm_amdgpu_gem_create_in info; 815 void __user *out = u64_to_user_ptr(args->value); 816 817 info.bo_size = robj->tbo.base.size; 818 info.alignment = robj->tbo.page_alignment << PAGE_SHIFT; 819 info.domains = robj->preferred_domains; 820 info.domain_flags = robj->flags; 821 amdgpu_bo_unreserve(robj); 822 if (copy_to_user(out, &info, sizeof(info))) 823 r = -EFAULT; 824 break; 825 } 826 case AMDGPU_GEM_OP_SET_PLACEMENT: 827 if (robj->tbo.base.import_attach && 828 args->value & AMDGPU_GEM_DOMAIN_VRAM) { 829 r = -EINVAL; 830 amdgpu_bo_unreserve(robj); 831 break; 832 } 833 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 834 r = -EPERM; 835 amdgpu_bo_unreserve(robj); 836 break; 837 } 838 for (base = robj->vm_bo; base; base = base->next) 839 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 840 amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) { 841 r = -EINVAL; 842 amdgpu_bo_unreserve(robj); 843 goto out; 844 } 845 846 847 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 848 AMDGPU_GEM_DOMAIN_GTT | 849 AMDGPU_GEM_DOMAIN_CPU); 850 robj->allowed_domains = robj->preferred_domains; 851 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 852 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 853 854 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 855 amdgpu_vm_bo_invalidate(adev, robj, true); 856 857 amdgpu_bo_unreserve(robj); 858 break; 859 default: 860 amdgpu_bo_unreserve(robj); 861 r = -EINVAL; 862 } 863 864 out: 865 drm_gem_object_put(gobj); 866 return r; 867 } 868 869 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, 870 int width, 871 int cpp, 872 bool tiled) 873 { 874 int aligned = width; 875 int pitch_mask = 0; 876 877 switch (cpp) { 878 case 1: 879 pitch_mask = 255; 880 break; 881 case 2: 882 pitch_mask = 127; 883 break; 884 case 3: 885 case 4: 886 pitch_mask = 63; 887 break; 888 } 889 890 aligned += pitch_mask; 891 aligned &= ~pitch_mask; 892 return aligned * cpp; 893 } 894 895 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 896 struct drm_device *dev, 897 struct drm_mode_create_dumb *args) 898 { 899 struct amdgpu_device *adev = drm_to_adev(dev); 900 struct drm_gem_object *gobj; 901 uint32_t handle; 902 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 903 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 904 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 905 u32 domain; 906 int r; 907 908 /* 909 * The buffer returned from this function should be cleared, but 910 * it can only be done if the ring is enabled or we'll fail to 911 * create the buffer. 912 */ 913 if (adev->mman.buffer_funcs_enabled) 914 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 915 916 args->pitch = amdgpu_gem_align_pitch(adev, args->width, 917 DIV_ROUND_UP(args->bpp, 8), 0); 918 args->size = (u64)args->pitch * args->height; 919 args->size = ALIGN(args->size, PAGE_SIZE); 920 domain = amdgpu_bo_get_preferred_domain(adev, 921 amdgpu_display_supported_domains(adev, flags)); 922 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 923 ttm_bo_type_device, NULL, &gobj); 924 if (r) 925 return -ENOMEM; 926 927 r = drm_gem_handle_create(file_priv, gobj, &handle); 928 /* drop reference from allocate - handle holds it now */ 929 drm_gem_object_put(gobj); 930 if (r) { 931 return r; 932 } 933 args->handle = handle; 934 return 0; 935 } 936 937 #if defined(CONFIG_DEBUG_FS) 938 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) 939 { 940 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 941 struct drm_device *dev = adev_to_drm(adev); 942 struct drm_file *file; 943 int r; 944 945 r = mutex_lock_interruptible(&dev->filelist_mutex); 946 if (r) 947 return r; 948 949 list_for_each_entry(file, &dev->filelist, lhead) { 950 struct task_struct *task; 951 struct drm_gem_object *gobj; 952 int id; 953 954 /* 955 * Although we have a valid reference on file->pid, that does 956 * not guarantee that the task_struct who called get_pid() is 957 * still alive (e.g. get_pid(current) => fork() => exit()). 958 * Therefore, we need to protect this ->comm access using RCU. 959 */ 960 rcu_read_lock(); 961 task = pid_task(file->pid, PIDTYPE_PID); 962 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 963 task ? task->comm : "<unknown>"); 964 rcu_read_unlock(); 965 966 spin_lock(&file->table_lock); 967 idr_for_each_entry(&file->object_idr, gobj, id) { 968 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 969 970 amdgpu_bo_print_info(id, bo, m); 971 } 972 spin_unlock(&file->table_lock); 973 } 974 975 mutex_unlock(&dev->filelist_mutex); 976 return 0; 977 } 978 979 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info); 980 981 #endif 982 983 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 984 { 985 #if defined(CONFIG_DEBUG_FS) 986 struct drm_minor *minor = adev_to_drm(adev)->primary; 987 struct dentry *root = minor->debugfs_root; 988 989 debugfs_create_file("amdgpu_gem_info", 0444, root, adev, 990 &amdgpu_debugfs_gem_info_fops); 991 #endif 992 } 993