1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/ktime.h> 29 #include <linux/module.h> 30 #include <linux/pagemap.h> 31 #include <linux/pci.h> 32 #include <linux/dma-buf.h> 33 34 #include <drm/amdgpu_drm.h> 35 #include <drm/drm_debugfs.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_display.h" 39 #include "amdgpu_xgmi.h" 40 41 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 42 { 43 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 44 45 if (robj) { 46 amdgpu_mn_unregister(robj); 47 amdgpu_bo_unref(&robj); 48 } 49 } 50 51 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 52 int alignment, u32 initial_domain, 53 u64 flags, enum ttm_bo_type type, 54 struct dma_resv *resv, 55 struct drm_gem_object **obj) 56 { 57 struct amdgpu_bo *bo; 58 struct amdgpu_bo_param bp; 59 int r; 60 61 memset(&bp, 0, sizeof(bp)); 62 *obj = NULL; 63 64 bp.size = size; 65 bp.byte_align = alignment; 66 bp.type = type; 67 bp.resv = resv; 68 bp.preferred_domain = initial_domain; 69 retry: 70 bp.flags = flags; 71 bp.domain = initial_domain; 72 r = amdgpu_bo_create(adev, &bp, &bo); 73 if (r) { 74 if (r != -ERESTARTSYS) { 75 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 76 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 77 goto retry; 78 } 79 80 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 81 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 82 goto retry; 83 } 84 DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 85 size, initial_domain, alignment, r); 86 } 87 return r; 88 } 89 *obj = &bo->tbo.base; 90 91 return 0; 92 } 93 94 void amdgpu_gem_force_release(struct amdgpu_device *adev) 95 { 96 struct drm_device *ddev = adev->ddev; 97 struct drm_file *file; 98 99 mutex_lock(&ddev->filelist_mutex); 100 101 list_for_each_entry(file, &ddev->filelist, lhead) { 102 struct drm_gem_object *gobj; 103 int handle; 104 105 WARN_ONCE(1, "Still active user space clients!\n"); 106 spin_lock(&file->table_lock); 107 idr_for_each_entry(&file->object_idr, gobj, handle) { 108 WARN_ONCE(1, "And also active allocations!\n"); 109 drm_gem_object_put(gobj); 110 } 111 idr_destroy(&file->object_idr); 112 spin_unlock(&file->table_lock); 113 } 114 115 mutex_unlock(&ddev->filelist_mutex); 116 } 117 118 /* 119 * Call from drm_gem_handle_create which appear in both new and open ioctl 120 * case. 121 */ 122 int amdgpu_gem_object_open(struct drm_gem_object *obj, 123 struct drm_file *file_priv) 124 { 125 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 126 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 127 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 128 struct amdgpu_vm *vm = &fpriv->vm; 129 struct amdgpu_bo_va *bo_va; 130 struct mm_struct *mm; 131 int r; 132 133 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 134 if (mm && mm != current->mm) 135 return -EPERM; 136 137 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 138 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 139 return -EPERM; 140 141 r = amdgpu_bo_reserve(abo, false); 142 if (r) 143 return r; 144 145 bo_va = amdgpu_vm_bo_find(vm, abo); 146 if (!bo_va) { 147 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 148 } else { 149 ++bo_va->ref_count; 150 } 151 amdgpu_bo_unreserve(abo); 152 return 0; 153 } 154 155 void amdgpu_gem_object_close(struct drm_gem_object *obj, 156 struct drm_file *file_priv) 157 { 158 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 159 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 160 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 161 struct amdgpu_vm *vm = &fpriv->vm; 162 163 struct amdgpu_bo_list_entry vm_pd; 164 struct list_head list, duplicates; 165 struct ttm_validate_buffer tv; 166 struct ww_acquire_ctx ticket; 167 struct amdgpu_bo_va *bo_va; 168 int r; 169 170 INIT_LIST_HEAD(&list); 171 INIT_LIST_HEAD(&duplicates); 172 173 tv.bo = &bo->tbo; 174 tv.num_shared = 1; 175 list_add(&tv.head, &list); 176 177 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 178 179 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 180 if (r) { 181 dev_err(adev->dev, "leaking bo va because " 182 "we fail to reserve bo (%d)\n", r); 183 return; 184 } 185 bo_va = amdgpu_vm_bo_find(vm, bo); 186 if (bo_va && --bo_va->ref_count == 0) { 187 amdgpu_vm_bo_rmv(adev, bo_va); 188 189 if (amdgpu_vm_ready(vm)) { 190 struct dma_fence *fence = NULL; 191 192 r = amdgpu_vm_clear_freed(adev, vm, &fence); 193 if (unlikely(r)) { 194 dev_err(adev->dev, "failed to clear page " 195 "tables on GEM object close (%d)\n", r); 196 } 197 198 if (fence) { 199 amdgpu_bo_fence(bo, fence, true); 200 dma_fence_put(fence); 201 } 202 } 203 } 204 ttm_eu_backoff_reservation(&ticket, &list); 205 } 206 207 /* 208 * GEM ioctls. 209 */ 210 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 211 struct drm_file *filp) 212 { 213 struct amdgpu_device *adev = dev->dev_private; 214 struct amdgpu_fpriv *fpriv = filp->driver_priv; 215 struct amdgpu_vm *vm = &fpriv->vm; 216 union drm_amdgpu_gem_create *args = data; 217 uint64_t flags = args->in.domain_flags; 218 uint64_t size = args->in.bo_size; 219 struct dma_resv *resv = NULL; 220 struct drm_gem_object *gobj; 221 uint32_t handle; 222 int r; 223 224 /* reject invalid gem flags */ 225 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 226 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 227 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 228 AMDGPU_GEM_CREATE_VRAM_CLEARED | 229 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 230 AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) 231 232 return -EINVAL; 233 234 /* reject invalid gem domains */ 235 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 236 return -EINVAL; 237 238 /* create a gem object to contain this object in */ 239 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 240 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 241 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 242 /* if gds bo is created from user space, it must be 243 * passed to bo list 244 */ 245 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 246 return -EINVAL; 247 } 248 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 249 } 250 251 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 252 r = amdgpu_bo_reserve(vm->root.base.bo, false); 253 if (r) 254 return r; 255 256 resv = vm->root.base.bo->tbo.base.resv; 257 } 258 259 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 260 (u32)(0xffffffff & args->in.domains), 261 flags, ttm_bo_type_device, resv, &gobj); 262 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 263 if (!r) { 264 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 265 266 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 267 } 268 amdgpu_bo_unreserve(vm->root.base.bo); 269 } 270 if (r) 271 return r; 272 273 r = drm_gem_handle_create(filp, gobj, &handle); 274 /* drop reference from allocate - handle holds it now */ 275 drm_gem_object_put(gobj); 276 if (r) 277 return r; 278 279 memset(args, 0, sizeof(*args)); 280 args->out.handle = handle; 281 return 0; 282 } 283 284 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 285 struct drm_file *filp) 286 { 287 struct ttm_operation_ctx ctx = { true, false }; 288 struct amdgpu_device *adev = dev->dev_private; 289 struct drm_amdgpu_gem_userptr *args = data; 290 struct drm_gem_object *gobj; 291 struct amdgpu_bo *bo; 292 uint32_t handle; 293 int r; 294 295 args->addr = untagged_addr(args->addr); 296 297 if (offset_in_page(args->addr | args->size)) 298 return -EINVAL; 299 300 /* reject unknown flag values */ 301 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 302 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 303 AMDGPU_GEM_USERPTR_REGISTER)) 304 return -EINVAL; 305 306 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 307 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 308 309 /* if we want to write to it we must install a MMU notifier */ 310 return -EACCES; 311 } 312 313 /* create a gem object to contain this object in */ 314 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 315 0, ttm_bo_type_device, NULL, &gobj); 316 if (r) 317 return r; 318 319 bo = gem_to_amdgpu_bo(gobj); 320 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 321 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 322 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 323 if (r) 324 goto release_object; 325 326 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 327 r = amdgpu_mn_register(bo, args->addr); 328 if (r) 329 goto release_object; 330 } 331 332 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 333 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 334 if (r) 335 goto release_object; 336 337 r = amdgpu_bo_reserve(bo, true); 338 if (r) 339 goto user_pages_done; 340 341 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 342 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 343 amdgpu_bo_unreserve(bo); 344 if (r) 345 goto user_pages_done; 346 } 347 348 r = drm_gem_handle_create(filp, gobj, &handle); 349 if (r) 350 goto user_pages_done; 351 352 args->handle = handle; 353 354 user_pages_done: 355 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 356 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 357 358 release_object: 359 drm_gem_object_put(gobj); 360 361 return r; 362 } 363 364 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 365 struct drm_device *dev, 366 uint32_t handle, uint64_t *offset_p) 367 { 368 struct drm_gem_object *gobj; 369 struct amdgpu_bo *robj; 370 371 gobj = drm_gem_object_lookup(filp, handle); 372 if (gobj == NULL) { 373 return -ENOENT; 374 } 375 robj = gem_to_amdgpu_bo(gobj); 376 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 377 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 378 drm_gem_object_put(gobj); 379 return -EPERM; 380 } 381 *offset_p = amdgpu_bo_mmap_offset(robj); 382 drm_gem_object_put(gobj); 383 return 0; 384 } 385 386 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 387 struct drm_file *filp) 388 { 389 union drm_amdgpu_gem_mmap *args = data; 390 uint32_t handle = args->in.handle; 391 memset(args, 0, sizeof(*args)); 392 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 393 } 394 395 /** 396 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 397 * 398 * @timeout_ns: timeout in ns 399 * 400 * Calculate the timeout in jiffies from an absolute timeout in ns. 401 */ 402 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 403 { 404 unsigned long timeout_jiffies; 405 ktime_t timeout; 406 407 /* clamp timeout if it's to large */ 408 if (((int64_t)timeout_ns) < 0) 409 return MAX_SCHEDULE_TIMEOUT; 410 411 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 412 if (ktime_to_ns(timeout) < 0) 413 return 0; 414 415 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 416 /* clamp timeout to avoid unsigned-> signed overflow */ 417 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 418 return MAX_SCHEDULE_TIMEOUT - 1; 419 420 return timeout_jiffies; 421 } 422 423 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 424 struct drm_file *filp) 425 { 426 union drm_amdgpu_gem_wait_idle *args = data; 427 struct drm_gem_object *gobj; 428 struct amdgpu_bo *robj; 429 uint32_t handle = args->in.handle; 430 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 431 int r = 0; 432 long ret; 433 434 gobj = drm_gem_object_lookup(filp, handle); 435 if (gobj == NULL) { 436 return -ENOENT; 437 } 438 robj = gem_to_amdgpu_bo(gobj); 439 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 440 timeout); 441 442 /* ret == 0 means not signaled, 443 * ret > 0 means signaled 444 * ret < 0 means interrupted before timeout 445 */ 446 if (ret >= 0) { 447 memset(args, 0, sizeof(*args)); 448 args->out.status = (ret == 0); 449 } else 450 r = ret; 451 452 drm_gem_object_put(gobj); 453 return r; 454 } 455 456 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 457 struct drm_file *filp) 458 { 459 struct drm_amdgpu_gem_metadata *args = data; 460 struct drm_gem_object *gobj; 461 struct amdgpu_bo *robj; 462 int r = -1; 463 464 DRM_DEBUG("%d \n", args->handle); 465 gobj = drm_gem_object_lookup(filp, args->handle); 466 if (gobj == NULL) 467 return -ENOENT; 468 robj = gem_to_amdgpu_bo(gobj); 469 470 r = amdgpu_bo_reserve(robj, false); 471 if (unlikely(r != 0)) 472 goto out; 473 474 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 475 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 476 r = amdgpu_bo_get_metadata(robj, args->data.data, 477 sizeof(args->data.data), 478 &args->data.data_size_bytes, 479 &args->data.flags); 480 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 481 if (args->data.data_size_bytes > sizeof(args->data.data)) { 482 r = -EINVAL; 483 goto unreserve; 484 } 485 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 486 if (!r) 487 r = amdgpu_bo_set_metadata(robj, args->data.data, 488 args->data.data_size_bytes, 489 args->data.flags); 490 } 491 492 unreserve: 493 amdgpu_bo_unreserve(robj); 494 out: 495 drm_gem_object_put(gobj); 496 return r; 497 } 498 499 /** 500 * amdgpu_gem_va_update_vm -update the bo_va in its VM 501 * 502 * @adev: amdgpu_device pointer 503 * @vm: vm to update 504 * @bo_va: bo_va to update 505 * @operation: map, unmap or clear 506 * 507 * Update the bo_va directly after setting its address. Errors are not 508 * vital here, so they are not reported back to userspace. 509 */ 510 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 511 struct amdgpu_vm *vm, 512 struct amdgpu_bo_va *bo_va, 513 uint32_t operation) 514 { 515 int r; 516 517 if (!amdgpu_vm_ready(vm)) 518 return; 519 520 r = amdgpu_vm_clear_freed(adev, vm, NULL); 521 if (r) 522 goto error; 523 524 if (operation == AMDGPU_VA_OP_MAP || 525 operation == AMDGPU_VA_OP_REPLACE) { 526 r = amdgpu_vm_bo_update(adev, bo_va, false); 527 if (r) 528 goto error; 529 } 530 531 r = amdgpu_vm_update_pdes(adev, vm, false); 532 533 error: 534 if (r && r != -ERESTARTSYS) 535 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 536 } 537 538 /** 539 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 540 * 541 * @adev: amdgpu_device pointer 542 * @flags: GEM UAPI flags 543 * 544 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 545 */ 546 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 547 { 548 uint64_t pte_flag = 0; 549 550 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 551 pte_flag |= AMDGPU_PTE_EXECUTABLE; 552 if (flags & AMDGPU_VM_PAGE_READABLE) 553 pte_flag |= AMDGPU_PTE_READABLE; 554 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 555 pte_flag |= AMDGPU_PTE_WRITEABLE; 556 if (flags & AMDGPU_VM_PAGE_PRT) 557 pte_flag |= AMDGPU_PTE_PRT; 558 559 if (adev->gmc.gmc_funcs->map_mtype) 560 pte_flag |= amdgpu_gmc_map_mtype(adev, 561 flags & AMDGPU_VM_MTYPE_MASK); 562 563 return pte_flag; 564 } 565 566 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 567 struct drm_file *filp) 568 { 569 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 570 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 571 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 572 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 573 AMDGPU_VM_PAGE_PRT; 574 575 struct drm_amdgpu_gem_va *args = data; 576 struct drm_gem_object *gobj; 577 struct amdgpu_device *adev = dev->dev_private; 578 struct amdgpu_fpriv *fpriv = filp->driver_priv; 579 struct amdgpu_bo *abo; 580 struct amdgpu_bo_va *bo_va; 581 struct amdgpu_bo_list_entry vm_pd; 582 struct ttm_validate_buffer tv; 583 struct ww_acquire_ctx ticket; 584 struct list_head list, duplicates; 585 uint64_t va_flags; 586 int r = 0; 587 588 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 589 dev_dbg(&dev->pdev->dev, 590 "va_address 0x%LX is in reserved area 0x%LX\n", 591 args->va_address, AMDGPU_VA_RESERVED_SIZE); 592 return -EINVAL; 593 } 594 595 if (args->va_address >= AMDGPU_GMC_HOLE_START && 596 args->va_address < AMDGPU_GMC_HOLE_END) { 597 dev_dbg(&dev->pdev->dev, 598 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 599 args->va_address, AMDGPU_GMC_HOLE_START, 600 AMDGPU_GMC_HOLE_END); 601 return -EINVAL; 602 } 603 604 args->va_address &= AMDGPU_GMC_HOLE_MASK; 605 606 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 607 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 608 args->flags); 609 return -EINVAL; 610 } 611 612 switch (args->operation) { 613 case AMDGPU_VA_OP_MAP: 614 case AMDGPU_VA_OP_UNMAP: 615 case AMDGPU_VA_OP_CLEAR: 616 case AMDGPU_VA_OP_REPLACE: 617 break; 618 default: 619 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 620 args->operation); 621 return -EINVAL; 622 } 623 624 INIT_LIST_HEAD(&list); 625 INIT_LIST_HEAD(&duplicates); 626 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 627 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 628 gobj = drm_gem_object_lookup(filp, args->handle); 629 if (gobj == NULL) 630 return -ENOENT; 631 abo = gem_to_amdgpu_bo(gobj); 632 tv.bo = &abo->tbo; 633 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 634 tv.num_shared = 1; 635 else 636 tv.num_shared = 0; 637 list_add(&tv.head, &list); 638 } else { 639 gobj = NULL; 640 abo = NULL; 641 } 642 643 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 644 645 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 646 if (r) 647 goto error_unref; 648 649 if (abo) { 650 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 651 if (!bo_va) { 652 r = -ENOENT; 653 goto error_backoff; 654 } 655 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 656 bo_va = fpriv->prt_va; 657 } else { 658 bo_va = NULL; 659 } 660 661 switch (args->operation) { 662 case AMDGPU_VA_OP_MAP: 663 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 664 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 665 args->offset_in_bo, args->map_size, 666 va_flags); 667 break; 668 case AMDGPU_VA_OP_UNMAP: 669 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 670 break; 671 672 case AMDGPU_VA_OP_CLEAR: 673 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 674 args->va_address, 675 args->map_size); 676 break; 677 case AMDGPU_VA_OP_REPLACE: 678 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 679 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 680 args->offset_in_bo, args->map_size, 681 va_flags); 682 break; 683 default: 684 break; 685 } 686 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 687 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 688 args->operation); 689 690 error_backoff: 691 ttm_eu_backoff_reservation(&ticket, &list); 692 693 error_unref: 694 drm_gem_object_put(gobj); 695 return r; 696 } 697 698 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 699 struct drm_file *filp) 700 { 701 struct amdgpu_device *adev = dev->dev_private; 702 struct drm_amdgpu_gem_op *args = data; 703 struct drm_gem_object *gobj; 704 struct amdgpu_vm_bo_base *base; 705 struct amdgpu_bo *robj; 706 int r; 707 708 gobj = drm_gem_object_lookup(filp, args->handle); 709 if (gobj == NULL) { 710 return -ENOENT; 711 } 712 robj = gem_to_amdgpu_bo(gobj); 713 714 r = amdgpu_bo_reserve(robj, false); 715 if (unlikely(r)) 716 goto out; 717 718 switch (args->op) { 719 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 720 struct drm_amdgpu_gem_create_in info; 721 void __user *out = u64_to_user_ptr(args->value); 722 723 info.bo_size = robj->tbo.base.size; 724 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 725 info.domains = robj->preferred_domains; 726 info.domain_flags = robj->flags; 727 amdgpu_bo_unreserve(robj); 728 if (copy_to_user(out, &info, sizeof(info))) 729 r = -EFAULT; 730 break; 731 } 732 case AMDGPU_GEM_OP_SET_PLACEMENT: 733 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 734 r = -EINVAL; 735 amdgpu_bo_unreserve(robj); 736 break; 737 } 738 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 739 r = -EPERM; 740 amdgpu_bo_unreserve(robj); 741 break; 742 } 743 for (base = robj->vm_bo; base; base = base->next) 744 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 745 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 746 r = -EINVAL; 747 amdgpu_bo_unreserve(robj); 748 goto out; 749 } 750 751 752 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 753 AMDGPU_GEM_DOMAIN_GTT | 754 AMDGPU_GEM_DOMAIN_CPU); 755 robj->allowed_domains = robj->preferred_domains; 756 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 757 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 758 759 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 760 amdgpu_vm_bo_invalidate(adev, robj, true); 761 762 amdgpu_bo_unreserve(robj); 763 break; 764 default: 765 amdgpu_bo_unreserve(robj); 766 r = -EINVAL; 767 } 768 769 out: 770 drm_gem_object_put(gobj); 771 return r; 772 } 773 774 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 775 struct drm_device *dev, 776 struct drm_mode_create_dumb *args) 777 { 778 struct amdgpu_device *adev = dev->dev_private; 779 struct drm_gem_object *gobj; 780 uint32_t handle; 781 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 782 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 783 u32 domain; 784 int r; 785 786 /* 787 * The buffer returned from this function should be cleared, but 788 * it can only be done if the ring is enabled or we'll fail to 789 * create the buffer. 790 */ 791 if (adev->mman.buffer_funcs_enabled) 792 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 793 794 args->pitch = amdgpu_align_pitch(adev, args->width, 795 DIV_ROUND_UP(args->bpp, 8), 0); 796 args->size = (u64)args->pitch * args->height; 797 args->size = ALIGN(args->size, PAGE_SIZE); 798 domain = amdgpu_bo_get_preferred_pin_domain(adev, 799 amdgpu_display_supported_domains(adev, flags)); 800 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 801 ttm_bo_type_device, NULL, &gobj); 802 if (r) 803 return -ENOMEM; 804 805 r = drm_gem_handle_create(file_priv, gobj, &handle); 806 /* drop reference from allocate - handle holds it now */ 807 drm_gem_object_put(gobj); 808 if (r) { 809 return r; 810 } 811 args->handle = handle; 812 return 0; 813 } 814 815 #if defined(CONFIG_DEBUG_FS) 816 817 #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 818 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 819 seq_printf((m), " " #flag); \ 820 } 821 822 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 823 { 824 struct drm_gem_object *gobj = ptr; 825 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 826 struct seq_file *m = data; 827 828 struct dma_buf_attachment *attachment; 829 struct dma_buf *dma_buf; 830 unsigned domain; 831 const char *placement; 832 unsigned pin_count; 833 834 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 835 switch (domain) { 836 case AMDGPU_GEM_DOMAIN_VRAM: 837 placement = "VRAM"; 838 break; 839 case AMDGPU_GEM_DOMAIN_GTT: 840 placement = " GTT"; 841 break; 842 case AMDGPU_GEM_DOMAIN_CPU: 843 default: 844 placement = " CPU"; 845 break; 846 } 847 seq_printf(m, "\t0x%08x: %12ld byte %s", 848 id, amdgpu_bo_size(bo), placement); 849 850 pin_count = READ_ONCE(bo->pin_count); 851 if (pin_count) 852 seq_printf(m, " pin count %d", pin_count); 853 854 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 855 attachment = READ_ONCE(bo->tbo.base.import_attach); 856 857 if (attachment) 858 seq_printf(m, " imported from %p%s", dma_buf, 859 attachment->peer2peer ? " P2P" : ""); 860 else if (dma_buf) 861 seq_printf(m, " exported as %p", dma_buf); 862 863 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 864 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 865 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 866 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 867 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 868 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 869 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 870 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 871 872 seq_printf(m, "\n"); 873 874 return 0; 875 } 876 877 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 878 { 879 struct drm_info_node *node = (struct drm_info_node *)m->private; 880 struct drm_device *dev = node->minor->dev; 881 struct drm_file *file; 882 int r; 883 884 r = mutex_lock_interruptible(&dev->filelist_mutex); 885 if (r) 886 return r; 887 888 list_for_each_entry(file, &dev->filelist, lhead) { 889 struct task_struct *task; 890 891 /* 892 * Although we have a valid reference on file->pid, that does 893 * not guarantee that the task_struct who called get_pid() is 894 * still alive (e.g. get_pid(current) => fork() => exit()). 895 * Therefore, we need to protect this ->comm access using RCU. 896 */ 897 rcu_read_lock(); 898 task = pid_task(file->pid, PIDTYPE_PID); 899 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 900 task ? task->comm : "<unknown>"); 901 rcu_read_unlock(); 902 903 spin_lock(&file->table_lock); 904 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 905 spin_unlock(&file->table_lock); 906 } 907 908 mutex_unlock(&dev->filelist_mutex); 909 return 0; 910 } 911 912 static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 913 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 914 }; 915 #endif 916 917 int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 918 { 919 #if defined(CONFIG_DEBUG_FS) 920 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 921 #endif 922 return 0; 923 } 924