1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 #include <drm/drm_drv.h> 38 39 /* 40 * GART 41 * The GART (Graphics Aperture Remapping Table) is an aperture 42 * in the GPU's address space. System pages can be mapped into 43 * the aperture and look like contiguous pages from the GPU's 44 * perspective. A page table maps the pages in the aperture 45 * to the actual backing pages in system memory. 46 * 47 * Radeon GPUs support both an internal GART, as described above, 48 * and AGP. AGP works similarly, but the GART table is configured 49 * and maintained by the northbridge rather than the driver. 50 * Radeon hw has a separate AGP aperture that is programmed to 51 * point to the AGP aperture provided by the northbridge and the 52 * requests are passed through to the northbridge aperture. 53 * Both AGP and internal GART can be used at the same time, however 54 * that is not currently supported by the driver. 55 * 56 * This file handles the common internal GART management. 57 */ 58 59 /* 60 * Common GART table functions. 61 */ 62 63 /** 64 * amdgpu_gart_dummy_page_init - init dummy page used by the driver 65 * 66 * @adev: amdgpu_device pointer 67 * 68 * Allocate the dummy page used by the driver (all asics). 69 * This dummy page is used by the driver as a filler for gart entries 70 * when pages are taken out of the GART 71 * Returns 0 on sucess, -ENOMEM on failure. 72 */ 73 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 74 { 75 struct page *dummy_page = ttm_glob.dummy_read_page; 76 77 if (adev->dummy_page_addr) 78 return 0; 79 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 80 PAGE_SIZE, DMA_BIDIRECTIONAL); 81 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 82 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 83 adev->dummy_page_addr = 0; 84 return -ENOMEM; 85 } 86 return 0; 87 } 88 89 /** 90 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver 91 * 92 * @adev: amdgpu_device pointer 93 * 94 * Frees the dummy page used by the driver (all asics). 95 */ 96 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 97 { 98 if (!adev->dummy_page_addr) 99 return; 100 dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 101 DMA_BIDIRECTIONAL); 102 adev->dummy_page_addr = 0; 103 } 104 105 /** 106 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 107 * 108 * @adev: amdgpu_device pointer 109 * 110 * Allocate video memory for GART page table 111 * (pcie r4xx, r5xx+). These asics require the 112 * gart table to be in video memory. 113 * Returns 0 for success, error for failure. 114 */ 115 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 116 { 117 int r; 118 119 if (adev->gart.bo == NULL) { 120 struct amdgpu_bo_param bp; 121 122 memset(&bp, 0, sizeof(bp)); 123 bp.size = adev->gart.table_size; 124 bp.byte_align = PAGE_SIZE; 125 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 126 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 127 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 128 bp.type = ttm_bo_type_kernel; 129 bp.resv = NULL; 130 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 131 132 r = amdgpu_bo_create(adev, &bp, &adev->gart.bo); 133 if (r) { 134 return r; 135 } 136 } 137 return 0; 138 } 139 140 /** 141 * amdgpu_gart_table_vram_pin - pin gart page table in vram 142 * 143 * @adev: amdgpu_device pointer 144 * 145 * Pin the GART page table in vram so it will not be moved 146 * by the memory manager (pcie r4xx, r5xx+). These asics require the 147 * gart table to be in video memory. 148 * Returns 0 for success, error for failure. 149 */ 150 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 151 { 152 int r; 153 154 r = amdgpu_bo_reserve(adev->gart.bo, false); 155 if (unlikely(r != 0)) 156 return r; 157 r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM); 158 if (r) { 159 amdgpu_bo_unreserve(adev->gart.bo); 160 return r; 161 } 162 r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr); 163 if (r) 164 amdgpu_bo_unpin(adev->gart.bo); 165 amdgpu_bo_unreserve(adev->gart.bo); 166 return r; 167 } 168 169 /** 170 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram 171 * 172 * @adev: amdgpu_device pointer 173 * 174 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 175 * These asics require the gart table to be in video memory. 176 */ 177 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) 178 { 179 int r; 180 181 if (adev->gart.bo == NULL) { 182 return; 183 } 184 r = amdgpu_bo_reserve(adev->gart.bo, true); 185 if (likely(r == 0)) { 186 amdgpu_bo_kunmap(adev->gart.bo); 187 amdgpu_bo_unpin(adev->gart.bo); 188 amdgpu_bo_unreserve(adev->gart.bo); 189 adev->gart.ptr = NULL; 190 } 191 } 192 193 /** 194 * amdgpu_gart_table_vram_free - free gart page table vram 195 * 196 * @adev: amdgpu_device pointer 197 * 198 * Free the video memory used for the GART page table 199 * (pcie r4xx, r5xx+). These asics require the gart table to 200 * be in video memory. 201 */ 202 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 203 { 204 if (adev->gart.bo == NULL) { 205 return; 206 } 207 amdgpu_bo_unref(&adev->gart.bo); 208 adev->gart.ptr = NULL; 209 } 210 211 /* 212 * Common gart functions. 213 */ 214 /** 215 * amdgpu_gart_unbind - unbind pages from the gart page table 216 * 217 * @adev: amdgpu_device pointer 218 * @offset: offset into the GPU's gart aperture 219 * @pages: number of pages to unbind 220 * 221 * Unbinds the requested pages from the gart page table and 222 * replaces them with the dummy page (all asics). 223 * Returns 0 for success, -EINVAL for failure. 224 */ 225 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 226 int pages) 227 { 228 unsigned t; 229 unsigned p; 230 int i, j; 231 u64 page_base; 232 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 233 uint64_t flags = 0; 234 int idx; 235 236 if (!adev->gart.ready) { 237 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 238 return -EINVAL; 239 } 240 241 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 242 return 0; 243 244 t = offset / AMDGPU_GPU_PAGE_SIZE; 245 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 246 for (i = 0; i < pages; i++, p++) { 247 page_base = adev->dummy_page_addr; 248 if (!adev->gart.ptr) 249 continue; 250 251 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 252 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 253 t, page_base, flags); 254 page_base += AMDGPU_GPU_PAGE_SIZE; 255 } 256 } 257 mb(); 258 amdgpu_device_flush_hdp(adev, NULL); 259 for (i = 0; i < adev->num_vmhubs; i++) 260 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 261 262 drm_dev_exit(idx); 263 return 0; 264 } 265 266 /** 267 * amdgpu_gart_map - map dma_addresses into GART entries 268 * 269 * @adev: amdgpu_device pointer 270 * @offset: offset into the GPU's gart aperture 271 * @pages: number of pages to bind 272 * @dma_addr: DMA addresses of pages 273 * @flags: page table entry flags 274 * @dst: CPU address of the gart table 275 * 276 * Map the dma_addresses into GART entries (all asics). 277 * Returns 0 for success, -EINVAL for failure. 278 */ 279 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 280 int pages, dma_addr_t *dma_addr, uint64_t flags, 281 void *dst) 282 { 283 uint64_t page_base; 284 unsigned i, j, t; 285 int idx; 286 287 if (!adev->gart.ready) { 288 WARN(1, "trying to bind memory to uninitialized GART !\n"); 289 return -EINVAL; 290 } 291 292 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 293 return 0; 294 295 t = offset / AMDGPU_GPU_PAGE_SIZE; 296 297 for (i = 0; i < pages; i++) { 298 page_base = dma_addr[i]; 299 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 300 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 301 page_base += AMDGPU_GPU_PAGE_SIZE; 302 } 303 } 304 drm_dev_exit(idx); 305 return 0; 306 } 307 308 /** 309 * amdgpu_gart_bind - bind pages into the gart page table 310 * 311 * @adev: amdgpu_device pointer 312 * @offset: offset into the GPU's gart aperture 313 * @pages: number of pages to bind 314 * @dma_addr: DMA addresses of pages 315 * @flags: page table entry flags 316 * 317 * Binds the requested pages to the gart page table 318 * (all asics). 319 * Returns 0 for success, -EINVAL for failure. 320 */ 321 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 322 int pages, dma_addr_t *dma_addr, 323 uint64_t flags) 324 { 325 if (!adev->gart.ready) { 326 WARN(1, "trying to bind memory to uninitialized GART !\n"); 327 return -EINVAL; 328 } 329 330 if (!adev->gart.ptr) 331 return 0; 332 333 return amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 334 adev->gart.ptr); 335 } 336 337 /** 338 * amdgpu_gart_invalidate_tlb - invalidate gart TLB 339 * 340 * @adev: amdgpu device driver pointer 341 * 342 * Invalidate gart TLB which can be use as a way to flush gart changes 343 * 344 */ 345 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 346 { 347 int i; 348 349 mb(); 350 amdgpu_device_flush_hdp(adev, NULL); 351 for (i = 0; i < adev->num_vmhubs; i++) 352 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 353 } 354 355 /** 356 * amdgpu_gart_init - init the driver info for managing the gart 357 * 358 * @adev: amdgpu_device pointer 359 * 360 * Allocate the dummy page and init the gart driver info (all asics). 361 * Returns 0 for success, error for failure. 362 */ 363 int amdgpu_gart_init(struct amdgpu_device *adev) 364 { 365 int r; 366 367 if (adev->dummy_page_addr) 368 return 0; 369 370 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 371 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 372 DRM_ERROR("Page size is smaller than GPU page size!\n"); 373 return -EINVAL; 374 } 375 r = amdgpu_gart_dummy_page_init(adev); 376 if (r) 377 return r; 378 /* Compute table size */ 379 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 380 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 381 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 382 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 383 384 return 0; 385 } 386