1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 38 /* 39 * GART 40 * The GART (Graphics Aperture Remapping Table) is an aperture 41 * in the GPU's address space. System pages can be mapped into 42 * the aperture and look like contiguous pages from the GPU's 43 * perspective. A page table maps the pages in the aperture 44 * to the actual backing pages in system memory. 45 * 46 * Radeon GPUs support both an internal GART, as described above, 47 * and AGP. AGP works similarly, but the GART table is configured 48 * and maintained by the northbridge rather than the driver. 49 * Radeon hw has a separate AGP aperture that is programmed to 50 * point to the AGP aperture provided by the northbridge and the 51 * requests are passed through to the northbridge aperture. 52 * Both AGP and internal GART can be used at the same time, however 53 * that is not currently supported by the driver. 54 * 55 * This file handles the common internal GART management. 56 */ 57 58 /* 59 * Common GART table functions. 60 */ 61 62 /** 63 * amdgpu_dummy_page_init - init dummy page used by the driver 64 * 65 * @adev: amdgpu_device pointer 66 * 67 * Allocate the dummy page used by the driver (all asics). 68 * This dummy page is used by the driver as a filler for gart entries 69 * when pages are taken out of the GART 70 * Returns 0 on sucess, -ENOMEM on failure. 71 */ 72 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 73 { 74 struct page *dummy_page = ttm_bo_glob.dummy_read_page; 75 76 if (adev->dummy_page_addr) 77 return 0; 78 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 79 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 80 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 81 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 82 adev->dummy_page_addr = 0; 83 return -ENOMEM; 84 } 85 return 0; 86 } 87 88 /** 89 * amdgpu_dummy_page_fini - free dummy page used by the driver 90 * 91 * @adev: amdgpu_device pointer 92 * 93 * Frees the dummy page used by the driver (all asics). 94 */ 95 static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 96 { 97 if (!adev->dummy_page_addr) 98 return; 99 pci_unmap_page(adev->pdev, adev->dummy_page_addr, 100 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 101 adev->dummy_page_addr = 0; 102 } 103 104 /** 105 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 106 * 107 * @adev: amdgpu_device pointer 108 * 109 * Allocate video memory for GART page table 110 * (pcie r4xx, r5xx+). These asics require the 111 * gart table to be in video memory. 112 * Returns 0 for success, error for failure. 113 */ 114 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 115 { 116 int r; 117 118 if (adev->gart.bo == NULL) { 119 struct amdgpu_bo_param bp; 120 121 memset(&bp, 0, sizeof(bp)); 122 bp.size = adev->gart.table_size; 123 bp.byte_align = PAGE_SIZE; 124 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 125 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 126 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 127 bp.type = ttm_bo_type_kernel; 128 bp.resv = NULL; 129 r = amdgpu_bo_create(adev, &bp, &adev->gart.bo); 130 if (r) { 131 return r; 132 } 133 } 134 return 0; 135 } 136 137 /** 138 * amdgpu_gart_table_vram_pin - pin gart page table in vram 139 * 140 * @adev: amdgpu_device pointer 141 * 142 * Pin the GART page table in vram so it will not be moved 143 * by the memory manager (pcie r4xx, r5xx+). These asics require the 144 * gart table to be in video memory. 145 * Returns 0 for success, error for failure. 146 */ 147 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 148 { 149 int r; 150 151 r = amdgpu_bo_reserve(adev->gart.bo, false); 152 if (unlikely(r != 0)) 153 return r; 154 r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM); 155 if (r) { 156 amdgpu_bo_unreserve(adev->gart.bo); 157 return r; 158 } 159 r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr); 160 if (r) 161 amdgpu_bo_unpin(adev->gart.bo); 162 amdgpu_bo_unreserve(adev->gart.bo); 163 return r; 164 } 165 166 /** 167 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram 168 * 169 * @adev: amdgpu_device pointer 170 * 171 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 172 * These asics require the gart table to be in video memory. 173 */ 174 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) 175 { 176 int r; 177 178 if (adev->gart.bo == NULL) { 179 return; 180 } 181 r = amdgpu_bo_reserve(adev->gart.bo, true); 182 if (likely(r == 0)) { 183 amdgpu_bo_kunmap(adev->gart.bo); 184 amdgpu_bo_unpin(adev->gart.bo); 185 amdgpu_bo_unreserve(adev->gart.bo); 186 adev->gart.ptr = NULL; 187 } 188 } 189 190 /** 191 * amdgpu_gart_table_vram_free - free gart page table vram 192 * 193 * @adev: amdgpu_device pointer 194 * 195 * Free the video memory used for the GART page table 196 * (pcie r4xx, r5xx+). These asics require the gart table to 197 * be in video memory. 198 */ 199 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 200 { 201 if (adev->gart.bo == NULL) { 202 return; 203 } 204 amdgpu_bo_unref(&adev->gart.bo); 205 } 206 207 /* 208 * Common gart functions. 209 */ 210 /** 211 * amdgpu_gart_unbind - unbind pages from the gart page table 212 * 213 * @adev: amdgpu_device pointer 214 * @offset: offset into the GPU's gart aperture 215 * @pages: number of pages to unbind 216 * 217 * Unbinds the requested pages from the gart page table and 218 * replaces them with the dummy page (all asics). 219 * Returns 0 for success, -EINVAL for failure. 220 */ 221 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 222 int pages) 223 { 224 unsigned t; 225 unsigned p; 226 int i, j; 227 u64 page_base; 228 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 229 uint64_t flags = 0; 230 231 if (!adev->gart.ready) { 232 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 233 return -EINVAL; 234 } 235 236 t = offset / AMDGPU_GPU_PAGE_SIZE; 237 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 238 for (i = 0; i < pages; i++, p++) { 239 page_base = adev->dummy_page_addr; 240 if (!adev->gart.ptr) 241 continue; 242 243 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 244 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 245 t, page_base, flags); 246 page_base += AMDGPU_GPU_PAGE_SIZE; 247 } 248 } 249 mb(); 250 amdgpu_asic_flush_hdp(adev, NULL); 251 for (i = 0; i < adev->num_vmhubs; i++) 252 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 253 254 return 0; 255 } 256 257 /** 258 * amdgpu_gart_map - map dma_addresses into GART entries 259 * 260 * @adev: amdgpu_device pointer 261 * @offset: offset into the GPU's gart aperture 262 * @pages: number of pages to bind 263 * @dma_addr: DMA addresses of pages 264 * @flags: page table entry flags 265 * @dst: CPU address of the gart table 266 * 267 * Map the dma_addresses into GART entries (all asics). 268 * Returns 0 for success, -EINVAL for failure. 269 */ 270 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 271 int pages, dma_addr_t *dma_addr, uint64_t flags, 272 void *dst) 273 { 274 uint64_t page_base; 275 unsigned i, j, t; 276 277 if (!adev->gart.ready) { 278 WARN(1, "trying to bind memory to uninitialized GART !\n"); 279 return -EINVAL; 280 } 281 282 t = offset / AMDGPU_GPU_PAGE_SIZE; 283 284 for (i = 0; i < pages; i++) { 285 page_base = dma_addr[i]; 286 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 287 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 288 page_base += AMDGPU_GPU_PAGE_SIZE; 289 } 290 } 291 return 0; 292 } 293 294 /** 295 * amdgpu_gart_bind - bind pages into the gart page table 296 * 297 * @adev: amdgpu_device pointer 298 * @offset: offset into the GPU's gart aperture 299 * @pages: number of pages to bind 300 * @pagelist: pages to bind 301 * @dma_addr: DMA addresses of pages 302 * @flags: page table entry flags 303 * 304 * Binds the requested pages to the gart page table 305 * (all asics). 306 * Returns 0 for success, -EINVAL for failure. 307 */ 308 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 309 int pages, struct page **pagelist, dma_addr_t *dma_addr, 310 uint64_t flags) 311 { 312 int r, i; 313 314 if (!adev->gart.ready) { 315 WARN(1, "trying to bind memory to uninitialized GART !\n"); 316 return -EINVAL; 317 } 318 319 if (!adev->gart.ptr) 320 return 0; 321 322 r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 323 adev->gart.ptr); 324 if (r) 325 return r; 326 327 mb(); 328 amdgpu_asic_flush_hdp(adev, NULL); 329 for (i = 0; i < adev->num_vmhubs; i++) 330 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 331 return 0; 332 } 333 334 /** 335 * amdgpu_gart_init - init the driver info for managing the gart 336 * 337 * @adev: amdgpu_device pointer 338 * 339 * Allocate the dummy page and init the gart driver info (all asics). 340 * Returns 0 for success, error for failure. 341 */ 342 int amdgpu_gart_init(struct amdgpu_device *adev) 343 { 344 int r; 345 346 if (adev->dummy_page_addr) 347 return 0; 348 349 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 350 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 351 DRM_ERROR("Page size is smaller than GPU page size!\n"); 352 return -EINVAL; 353 } 354 r = amdgpu_gart_dummy_page_init(adev); 355 if (r) 356 return r; 357 /* Compute table size */ 358 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 359 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 360 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 361 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 362 363 return 0; 364 } 365 366 /** 367 * amdgpu_gart_fini - tear down the driver info for managing the gart 368 * 369 * @adev: amdgpu_device pointer 370 * 371 * Tear down the gart driver info and free the dummy page (all asics). 372 */ 373 void amdgpu_gart_fini(struct amdgpu_device *adev) 374 { 375 amdgpu_gart_dummy_page_fini(adev); 376 } 377