1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #ifdef CONFIG_X86 31 #include <asm/set_memory.h> 32 #endif 33 #include "amdgpu.h" 34 35 /* 36 * GART 37 * The GART (Graphics Aperture Remapping Table) is an aperture 38 * in the GPU's address space. System pages can be mapped into 39 * the aperture and look like contiguous pages from the GPU's 40 * perspective. A page table maps the pages in the aperture 41 * to the actual backing pages in system memory. 42 * 43 * Radeon GPUs support both an internal GART, as described above, 44 * and AGP. AGP works similarly, but the GART table is configured 45 * and maintained by the northbridge rather than the driver. 46 * Radeon hw has a separate AGP aperture that is programmed to 47 * point to the AGP aperture provided by the northbridge and the 48 * requests are passed through to the northbridge aperture. 49 * Both AGP and internal GART can be used at the same time, however 50 * that is not currently supported by the driver. 51 * 52 * This file handles the common internal GART management. 53 */ 54 55 /* 56 * Common GART table functions. 57 */ 58 59 /** 60 * amdgpu_dummy_page_init - init dummy page used by the driver 61 * 62 * @adev: amdgpu_device pointer 63 * 64 * Allocate the dummy page used by the driver (all asics). 65 * This dummy page is used by the driver as a filler for gart entries 66 * when pages are taken out of the GART 67 * Returns 0 on sucess, -ENOMEM on failure. 68 */ 69 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 70 { 71 struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page; 72 73 if (adev->dummy_page_addr) 74 return 0; 75 adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0, 76 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 77 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) { 78 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 79 adev->dummy_page_addr = 0; 80 return -ENOMEM; 81 } 82 return 0; 83 } 84 85 /** 86 * amdgpu_dummy_page_fini - free dummy page used by the driver 87 * 88 * @adev: amdgpu_device pointer 89 * 90 * Frees the dummy page used by the driver (all asics). 91 */ 92 static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 93 { 94 if (!adev->dummy_page_addr) 95 return; 96 pci_unmap_page(adev->pdev, adev->dummy_page_addr, 97 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 98 adev->dummy_page_addr = 0; 99 } 100 101 /** 102 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 103 * 104 * @adev: amdgpu_device pointer 105 * 106 * Allocate video memory for GART page table 107 * (pcie r4xx, r5xx+). These asics require the 108 * gart table to be in video memory. 109 * Returns 0 for success, error for failure. 110 */ 111 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 112 { 113 int r; 114 115 if (adev->gart.robj == NULL) { 116 struct amdgpu_bo_param bp; 117 118 memset(&bp, 0, sizeof(bp)); 119 bp.size = adev->gart.table_size; 120 bp.byte_align = PAGE_SIZE; 121 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 122 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 123 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 124 bp.type = ttm_bo_type_kernel; 125 bp.resv = NULL; 126 r = amdgpu_bo_create(adev, &bp, &adev->gart.robj); 127 if (r) { 128 return r; 129 } 130 } 131 return 0; 132 } 133 134 /** 135 * amdgpu_gart_table_vram_pin - pin gart page table in vram 136 * 137 * @adev: amdgpu_device pointer 138 * 139 * Pin the GART page table in vram so it will not be moved 140 * by the memory manager (pcie r4xx, r5xx+). These asics require the 141 * gart table to be in video memory. 142 * Returns 0 for success, error for failure. 143 */ 144 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 145 { 146 uint64_t gpu_addr; 147 int r; 148 149 r = amdgpu_bo_reserve(adev->gart.robj, false); 150 if (unlikely(r != 0)) 151 return r; 152 r = amdgpu_bo_pin(adev->gart.robj, 153 AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); 154 if (r) { 155 amdgpu_bo_unreserve(adev->gart.robj); 156 return r; 157 } 158 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); 159 if (r) 160 amdgpu_bo_unpin(adev->gart.robj); 161 amdgpu_bo_unreserve(adev->gart.robj); 162 adev->gart.table_addr = gpu_addr; 163 return r; 164 } 165 166 /** 167 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram 168 * 169 * @adev: amdgpu_device pointer 170 * 171 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 172 * These asics require the gart table to be in video memory. 173 */ 174 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) 175 { 176 int r; 177 178 if (adev->gart.robj == NULL) { 179 return; 180 } 181 r = amdgpu_bo_reserve(adev->gart.robj, true); 182 if (likely(r == 0)) { 183 amdgpu_bo_kunmap(adev->gart.robj); 184 amdgpu_bo_unpin(adev->gart.robj); 185 amdgpu_bo_unreserve(adev->gart.robj); 186 adev->gart.ptr = NULL; 187 } 188 } 189 190 /** 191 * amdgpu_gart_table_vram_free - free gart page table vram 192 * 193 * @adev: amdgpu_device pointer 194 * 195 * Free the video memory used for the GART page table 196 * (pcie r4xx, r5xx+). These asics require the gart table to 197 * be in video memory. 198 */ 199 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 200 { 201 if (adev->gart.robj == NULL) { 202 return; 203 } 204 amdgpu_bo_unref(&adev->gart.robj); 205 } 206 207 /* 208 * Common gart functions. 209 */ 210 /** 211 * amdgpu_gart_unbind - unbind pages from the gart page table 212 * 213 * @adev: amdgpu_device pointer 214 * @offset: offset into the GPU's gart aperture 215 * @pages: number of pages to unbind 216 * 217 * Unbinds the requested pages from the gart page table and 218 * replaces them with the dummy page (all asics). 219 * Returns 0 for success, -EINVAL for failure. 220 */ 221 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 222 int pages) 223 { 224 unsigned t; 225 unsigned p; 226 int i, j; 227 u64 page_base; 228 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 229 uint64_t flags = 0; 230 231 if (!adev->gart.ready) { 232 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 233 return -EINVAL; 234 } 235 236 t = offset / AMDGPU_GPU_PAGE_SIZE; 237 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 238 for (i = 0; i < pages; i++, p++) { 239 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 240 adev->gart.pages[p] = NULL; 241 #endif 242 page_base = adev->dummy_page_addr; 243 if (!adev->gart.ptr) 244 continue; 245 246 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { 247 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 248 t, page_base, flags); 249 page_base += AMDGPU_GPU_PAGE_SIZE; 250 } 251 } 252 mb(); 253 amdgpu_asic_flush_hdp(adev, NULL); 254 amdgpu_gmc_flush_gpu_tlb(adev, 0); 255 return 0; 256 } 257 258 /** 259 * amdgpu_gart_map - map dma_addresses into GART entries 260 * 261 * @adev: amdgpu_device pointer 262 * @offset: offset into the GPU's gart aperture 263 * @pages: number of pages to bind 264 * @dma_addr: DMA addresses of pages 265 * 266 * Map the dma_addresses into GART entries (all asics). 267 * Returns 0 for success, -EINVAL for failure. 268 */ 269 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 270 int pages, dma_addr_t *dma_addr, uint64_t flags, 271 void *dst) 272 { 273 uint64_t page_base; 274 unsigned i, j, t; 275 276 if (!adev->gart.ready) { 277 WARN(1, "trying to bind memory to uninitialized GART !\n"); 278 return -EINVAL; 279 } 280 281 t = offset / AMDGPU_GPU_PAGE_SIZE; 282 283 for (i = 0; i < pages; i++) { 284 page_base = dma_addr[i]; 285 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { 286 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 287 page_base += AMDGPU_GPU_PAGE_SIZE; 288 } 289 } 290 return 0; 291 } 292 293 /** 294 * amdgpu_gart_bind - bind pages into the gart page table 295 * 296 * @adev: amdgpu_device pointer 297 * @offset: offset into the GPU's gart aperture 298 * @pages: number of pages to bind 299 * @pagelist: pages to bind 300 * @dma_addr: DMA addresses of pages 301 * 302 * Binds the requested pages to the gart page table 303 * (all asics). 304 * Returns 0 for success, -EINVAL for failure. 305 */ 306 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 307 int pages, struct page **pagelist, dma_addr_t *dma_addr, 308 uint64_t flags) 309 { 310 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 311 unsigned i,t,p; 312 #endif 313 int r; 314 315 if (!adev->gart.ready) { 316 WARN(1, "trying to bind memory to uninitialized GART !\n"); 317 return -EINVAL; 318 } 319 320 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 321 t = offset / AMDGPU_GPU_PAGE_SIZE; 322 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 323 for (i = 0; i < pages; i++, p++) 324 adev->gart.pages[p] = pagelist ? pagelist[i] : NULL; 325 #endif 326 327 if (!adev->gart.ptr) 328 return 0; 329 330 r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 331 adev->gart.ptr); 332 if (r) 333 return r; 334 335 mb(); 336 amdgpu_asic_flush_hdp(adev, NULL); 337 amdgpu_gmc_flush_gpu_tlb(adev, 0); 338 return 0; 339 } 340 341 /** 342 * amdgpu_gart_init - init the driver info for managing the gart 343 * 344 * @adev: amdgpu_device pointer 345 * 346 * Allocate the dummy page and init the gart driver info (all asics). 347 * Returns 0 for success, error for failure. 348 */ 349 int amdgpu_gart_init(struct amdgpu_device *adev) 350 { 351 int r; 352 353 if (adev->dummy_page_addr) 354 return 0; 355 356 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 357 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 358 DRM_ERROR("Page size is smaller than GPU page size!\n"); 359 return -EINVAL; 360 } 361 r = amdgpu_gart_dummy_page_init(adev); 362 if (r) 363 return r; 364 /* Compute table size */ 365 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 366 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 367 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 368 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 369 370 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 371 /* Allocate pages table */ 372 adev->gart.pages = vzalloc(array_size(sizeof(void *), 373 adev->gart.num_cpu_pages)); 374 if (adev->gart.pages == NULL) 375 return -ENOMEM; 376 #endif 377 378 return 0; 379 } 380 381 /** 382 * amdgpu_gart_fini - tear down the driver info for managing the gart 383 * 384 * @adev: amdgpu_device pointer 385 * 386 * Tear down the gart driver info and free the dummy page (all asics). 387 */ 388 void amdgpu_gart_fini(struct amdgpu_device *adev) 389 { 390 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 391 vfree(adev->gart.pages); 392 adev->gart.pages = NULL; 393 #endif 394 amdgpu_gart_dummy_page_fini(adev); 395 } 396