1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 38 /* 39 * GART 40 * The GART (Graphics Aperture Remapping Table) is an aperture 41 * in the GPU's address space. System pages can be mapped into 42 * the aperture and look like contiguous pages from the GPU's 43 * perspective. A page table maps the pages in the aperture 44 * to the actual backing pages in system memory. 45 * 46 * Radeon GPUs support both an internal GART, as described above, 47 * and AGP. AGP works similarly, but the GART table is configured 48 * and maintained by the northbridge rather than the driver. 49 * Radeon hw has a separate AGP aperture that is programmed to 50 * point to the AGP aperture provided by the northbridge and the 51 * requests are passed through to the northbridge aperture. 52 * Both AGP and internal GART can be used at the same time, however 53 * that is not currently supported by the driver. 54 * 55 * This file handles the common internal GART management. 56 */ 57 58 /* 59 * Common GART table functions. 60 */ 61 62 /** 63 * amdgpu_dummy_page_init - init dummy page used by the driver 64 * 65 * @adev: amdgpu_device pointer 66 * 67 * Allocate the dummy page used by the driver (all asics). 68 * This dummy page is used by the driver as a filler for gart entries 69 * when pages are taken out of the GART 70 * Returns 0 on sucess, -ENOMEM on failure. 71 */ 72 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 73 { 74 struct page *dummy_page = ttm_bo_glob.dummy_read_page; 75 76 if (adev->dummy_page_addr) 77 return 0; 78 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 79 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 80 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 81 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 82 adev->dummy_page_addr = 0; 83 return -ENOMEM; 84 } 85 return 0; 86 } 87 88 /** 89 * amdgpu_dummy_page_fini - free dummy page used by the driver 90 * 91 * @adev: amdgpu_device pointer 92 * 93 * Frees the dummy page used by the driver (all asics). 94 */ 95 static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 96 { 97 if (!adev->dummy_page_addr) 98 return; 99 pci_unmap_page(adev->pdev, adev->dummy_page_addr, 100 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 101 adev->dummy_page_addr = 0; 102 } 103 104 /** 105 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 106 * 107 * @adev: amdgpu_device pointer 108 * 109 * Allocate video memory for GART page table 110 * (pcie r4xx, r5xx+). These asics require the 111 * gart table to be in video memory. 112 * Returns 0 for success, error for failure. 113 */ 114 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 115 { 116 int r; 117 118 if (adev->gart.bo == NULL) { 119 struct amdgpu_bo_param bp; 120 121 memset(&bp, 0, sizeof(bp)); 122 bp.size = adev->gart.table_size; 123 bp.byte_align = PAGE_SIZE; 124 bp.domain = AMDGPU_GEM_DOMAIN_VRAM; 125 bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 126 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 127 bp.type = ttm_bo_type_kernel; 128 bp.resv = NULL; 129 r = amdgpu_bo_create(adev, &bp, &adev->gart.bo); 130 if (r) { 131 return r; 132 } 133 } 134 return 0; 135 } 136 137 /** 138 * amdgpu_gart_table_vram_pin - pin gart page table in vram 139 * 140 * @adev: amdgpu_device pointer 141 * 142 * Pin the GART page table in vram so it will not be moved 143 * by the memory manager (pcie r4xx, r5xx+). These asics require the 144 * gart table to be in video memory. 145 * Returns 0 for success, error for failure. 146 */ 147 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 148 { 149 int r; 150 151 r = amdgpu_bo_reserve(adev->gart.bo, false); 152 if (unlikely(r != 0)) 153 return r; 154 r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM); 155 if (r) { 156 amdgpu_bo_unreserve(adev->gart.bo); 157 return r; 158 } 159 r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr); 160 if (r) 161 amdgpu_bo_unpin(adev->gart.bo); 162 amdgpu_bo_unreserve(adev->gart.bo); 163 return r; 164 } 165 166 /** 167 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram 168 * 169 * @adev: amdgpu_device pointer 170 * 171 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 172 * These asics require the gart table to be in video memory. 173 */ 174 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) 175 { 176 int r; 177 178 if (adev->gart.bo == NULL) { 179 return; 180 } 181 r = amdgpu_bo_reserve(adev->gart.bo, true); 182 if (likely(r == 0)) { 183 amdgpu_bo_kunmap(adev->gart.bo); 184 amdgpu_bo_unpin(adev->gart.bo); 185 amdgpu_bo_unreserve(adev->gart.bo); 186 adev->gart.ptr = NULL; 187 } 188 } 189 190 /** 191 * amdgpu_gart_table_vram_free - free gart page table vram 192 * 193 * @adev: amdgpu_device pointer 194 * 195 * Free the video memory used for the GART page table 196 * (pcie r4xx, r5xx+). These asics require the gart table to 197 * be in video memory. 198 */ 199 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 200 { 201 if (adev->gart.bo == NULL) { 202 return; 203 } 204 amdgpu_bo_unref(&adev->gart.bo); 205 } 206 207 /* 208 * Common gart functions. 209 */ 210 /** 211 * amdgpu_gart_unbind - unbind pages from the gart page table 212 * 213 * @adev: amdgpu_device pointer 214 * @offset: offset into the GPU's gart aperture 215 * @pages: number of pages to unbind 216 * 217 * Unbinds the requested pages from the gart page table and 218 * replaces them with the dummy page (all asics). 219 * Returns 0 for success, -EINVAL for failure. 220 */ 221 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 222 int pages) 223 { 224 unsigned t; 225 unsigned p; 226 int i, j; 227 u64 page_base; 228 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 229 uint64_t flags = 0; 230 231 if (!adev->gart.ready) { 232 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 233 return -EINVAL; 234 } 235 236 t = offset / AMDGPU_GPU_PAGE_SIZE; 237 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 238 for (i = 0; i < pages; i++, p++) { 239 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 240 adev->gart.pages[p] = NULL; 241 #endif 242 page_base = adev->dummy_page_addr; 243 if (!adev->gart.ptr) 244 continue; 245 246 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 247 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 248 t, page_base, flags); 249 page_base += AMDGPU_GPU_PAGE_SIZE; 250 } 251 } 252 mb(); 253 amdgpu_asic_flush_hdp(adev, NULL); 254 for (i = 0; i < adev->num_vmhubs; i++) 255 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 256 257 return 0; 258 } 259 260 /** 261 * amdgpu_gart_map - map dma_addresses into GART entries 262 * 263 * @adev: amdgpu_device pointer 264 * @offset: offset into the GPU's gart aperture 265 * @pages: number of pages to bind 266 * @dma_addr: DMA addresses of pages 267 * @flags: page table entry flags 268 * @dst: CPU address of the gart table 269 * 270 * Map the dma_addresses into GART entries (all asics). 271 * Returns 0 for success, -EINVAL for failure. 272 */ 273 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 274 int pages, dma_addr_t *dma_addr, uint64_t flags, 275 void *dst) 276 { 277 uint64_t page_base; 278 unsigned i, j, t; 279 280 if (!adev->gart.ready) { 281 WARN(1, "trying to bind memory to uninitialized GART !\n"); 282 return -EINVAL; 283 } 284 285 t = offset / AMDGPU_GPU_PAGE_SIZE; 286 287 for (i = 0; i < pages; i++) { 288 page_base = dma_addr[i]; 289 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 290 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 291 page_base += AMDGPU_GPU_PAGE_SIZE; 292 } 293 } 294 return 0; 295 } 296 297 /** 298 * amdgpu_gart_bind - bind pages into the gart page table 299 * 300 * @adev: amdgpu_device pointer 301 * @offset: offset into the GPU's gart aperture 302 * @pages: number of pages to bind 303 * @pagelist: pages to bind 304 * @dma_addr: DMA addresses of pages 305 * @flags: page table entry flags 306 * 307 * Binds the requested pages to the gart page table 308 * (all asics). 309 * Returns 0 for success, -EINVAL for failure. 310 */ 311 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 312 int pages, struct page **pagelist, dma_addr_t *dma_addr, 313 uint64_t flags) 314 { 315 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 316 unsigned t,p; 317 #endif 318 int r, i; 319 320 if (!adev->gart.ready) { 321 WARN(1, "trying to bind memory to uninitialized GART !\n"); 322 return -EINVAL; 323 } 324 325 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 326 t = offset / AMDGPU_GPU_PAGE_SIZE; 327 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 328 for (i = 0; i < pages; i++, p++) 329 adev->gart.pages[p] = pagelist ? pagelist[i] : NULL; 330 #endif 331 332 if (!adev->gart.ptr) 333 return 0; 334 335 r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 336 adev->gart.ptr); 337 if (r) 338 return r; 339 340 mb(); 341 amdgpu_asic_flush_hdp(adev, NULL); 342 for (i = 0; i < adev->num_vmhubs; i++) 343 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 344 return 0; 345 } 346 347 /** 348 * amdgpu_gart_init - init the driver info for managing the gart 349 * 350 * @adev: amdgpu_device pointer 351 * 352 * Allocate the dummy page and init the gart driver info (all asics). 353 * Returns 0 for success, error for failure. 354 */ 355 int amdgpu_gart_init(struct amdgpu_device *adev) 356 { 357 int r; 358 359 if (adev->dummy_page_addr) 360 return 0; 361 362 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 363 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 364 DRM_ERROR("Page size is smaller than GPU page size!\n"); 365 return -EINVAL; 366 } 367 r = amdgpu_gart_dummy_page_init(adev); 368 if (r) 369 return r; 370 /* Compute table size */ 371 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 372 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 373 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 374 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 375 376 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 377 /* Allocate pages table */ 378 adev->gart.pages = vzalloc(array_size(sizeof(void *), 379 adev->gart.num_cpu_pages)); 380 if (adev->gart.pages == NULL) 381 return -ENOMEM; 382 #endif 383 384 return 0; 385 } 386 387 /** 388 * amdgpu_gart_fini - tear down the driver info for managing the gart 389 * 390 * @adev: amdgpu_device pointer 391 * 392 * Tear down the gart driver info and free the dummy page (all asics). 393 */ 394 void amdgpu_gart_fini(struct amdgpu_device *adev) 395 { 396 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 397 vfree(adev->gart.pages); 398 adev->gart.pages = NULL; 399 #endif 400 amdgpu_gart_dummy_page_fini(adev); 401 } 402