1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <drm/drmP.h>
29 #include <drm/amdgpu_drm.h>
30 #include "amdgpu.h"
31 
32 /*
33  * GART
34  * The GART (Graphics Aperture Remapping Table) is an aperture
35  * in the GPU's address space.  System pages can be mapped into
36  * the aperture and look like contiguous pages from the GPU's
37  * perspective.  A page table maps the pages in the aperture
38  * to the actual backing pages in system memory.
39  *
40  * Radeon GPUs support both an internal GART, as described above,
41  * and AGP.  AGP works similarly, but the GART table is configured
42  * and maintained by the northbridge rather than the driver.
43  * Radeon hw has a separate AGP aperture that is programmed to
44  * point to the AGP aperture provided by the northbridge and the
45  * requests are passed through to the northbridge aperture.
46  * Both AGP and internal GART can be used at the same time, however
47  * that is not currently supported by the driver.
48  *
49  * This file handles the common internal GART management.
50  */
51 
52 /*
53  * Common GART table functions.
54  */
55 /**
56  * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
57  *
58  * @adev: amdgpu_device pointer
59  *
60  * Allocate system memory for GART page table
61  * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
62  * gart table to be in system memory.
63  * Returns 0 for success, -ENOMEM for failure.
64  */
65 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
66 {
67 	void *ptr;
68 
69 	ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
70 				   &adev->gart.table_addr);
71 	if (ptr == NULL) {
72 		return -ENOMEM;
73 	}
74 #ifdef CONFIG_X86
75 	if (0) {
76 		set_memory_uc((unsigned long)ptr,
77 			      adev->gart.table_size >> PAGE_SHIFT);
78 	}
79 #endif
80 	adev->gart.ptr = ptr;
81 	memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
82 	return 0;
83 }
84 
85 /**
86  * amdgpu_gart_table_ram_free - free system ram for gart page table
87  *
88  * @adev: amdgpu_device pointer
89  *
90  * Free system memory for GART page table
91  * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
92  * gart table to be in system memory.
93  */
94 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
95 {
96 	if (adev->gart.ptr == NULL) {
97 		return;
98 	}
99 #ifdef CONFIG_X86
100 	if (0) {
101 		set_memory_wb((unsigned long)adev->gart.ptr,
102 			      adev->gart.table_size >> PAGE_SHIFT);
103 	}
104 #endif
105 	pci_free_consistent(adev->pdev, adev->gart.table_size,
106 			    (void *)adev->gart.ptr,
107 			    adev->gart.table_addr);
108 	adev->gart.ptr = NULL;
109 	adev->gart.table_addr = 0;
110 }
111 
112 /**
113  * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
114  *
115  * @adev: amdgpu_device pointer
116  *
117  * Allocate video memory for GART page table
118  * (pcie r4xx, r5xx+).  These asics require the
119  * gart table to be in video memory.
120  * Returns 0 for success, error for failure.
121  */
122 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
123 {
124 	int r;
125 
126 	if (adev->gart.robj == NULL) {
127 		r = amdgpu_bo_create(adev, adev->gart.table_size,
128 				     PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
129 				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
130 				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
131 				     NULL, NULL, &adev->gart.robj);
132 		if (r) {
133 			return r;
134 		}
135 	}
136 	return 0;
137 }
138 
139 /**
140  * amdgpu_gart_table_vram_pin - pin gart page table in vram
141  *
142  * @adev: amdgpu_device pointer
143  *
144  * Pin the GART page table in vram so it will not be moved
145  * by the memory manager (pcie r4xx, r5xx+).  These asics require the
146  * gart table to be in video memory.
147  * Returns 0 for success, error for failure.
148  */
149 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
150 {
151 	uint64_t gpu_addr;
152 	int r;
153 
154 	r = amdgpu_bo_reserve(adev->gart.robj, false);
155 	if (unlikely(r != 0))
156 		return r;
157 	r = amdgpu_bo_pin(adev->gart.robj,
158 				AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
159 	if (r) {
160 		amdgpu_bo_unreserve(adev->gart.robj);
161 		return r;
162 	}
163 	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
164 	if (r)
165 		amdgpu_bo_unpin(adev->gart.robj);
166 	amdgpu_bo_unreserve(adev->gart.robj);
167 	adev->gart.table_addr = gpu_addr;
168 	return r;
169 }
170 
171 /**
172  * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
173  *
174  * @adev: amdgpu_device pointer
175  *
176  * Unpin the GART page table in vram (pcie r4xx, r5xx+).
177  * These asics require the gart table to be in video memory.
178  */
179 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
180 {
181 	int r;
182 
183 	if (adev->gart.robj == NULL) {
184 		return;
185 	}
186 	r = amdgpu_bo_reserve(adev->gart.robj, false);
187 	if (likely(r == 0)) {
188 		amdgpu_bo_kunmap(adev->gart.robj);
189 		amdgpu_bo_unpin(adev->gart.robj);
190 		amdgpu_bo_unreserve(adev->gart.robj);
191 		adev->gart.ptr = NULL;
192 	}
193 }
194 
195 /**
196  * amdgpu_gart_table_vram_free - free gart page table vram
197  *
198  * @adev: amdgpu_device pointer
199  *
200  * Free the video memory used for the GART page table
201  * (pcie r4xx, r5xx+).  These asics require the gart table to
202  * be in video memory.
203  */
204 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
205 {
206 	if (adev->gart.robj == NULL) {
207 		return;
208 	}
209 	amdgpu_bo_unref(&adev->gart.robj);
210 }
211 
212 /*
213  * Common gart functions.
214  */
215 /**
216  * amdgpu_gart_unbind - unbind pages from the gart page table
217  *
218  * @adev: amdgpu_device pointer
219  * @offset: offset into the GPU's gart aperture
220  * @pages: number of pages to unbind
221  *
222  * Unbinds the requested pages from the gart page table and
223  * replaces them with the dummy page (all asics).
224  */
225 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
226 			int pages)
227 {
228 	unsigned t;
229 	unsigned p;
230 	int i, j;
231 	u64 page_base;
232 	uint32_t flags = AMDGPU_PTE_SYSTEM;
233 
234 	if (!adev->gart.ready) {
235 		WARN(1, "trying to unbind memory from uninitialized GART !\n");
236 		return;
237 	}
238 
239 	t = offset / AMDGPU_GPU_PAGE_SIZE;
240 	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
241 	for (i = 0; i < pages; i++, p++) {
242 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
243 		adev->gart.pages[p] = NULL;
244 #endif
245 		page_base = adev->dummy_page.addr;
246 		if (!adev->gart.ptr)
247 			continue;
248 
249 		for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
250 			amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
251 						t, page_base, flags);
252 			page_base += AMDGPU_GPU_PAGE_SIZE;
253 		}
254 	}
255 	mb();
256 	amdgpu_gart_flush_gpu_tlb(adev, 0);
257 }
258 
259 /**
260  * amdgpu_gart_bind - bind pages into the gart page table
261  *
262  * @adev: amdgpu_device pointer
263  * @offset: offset into the GPU's gart aperture
264  * @pages: number of pages to bind
265  * @pagelist: pages to bind
266  * @dma_addr: DMA addresses of pages
267  *
268  * Binds the requested pages to the gart page table
269  * (all asics).
270  * Returns 0 for success, -EINVAL for failure.
271  */
272 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
273 		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
274 		     uint32_t flags)
275 {
276 	unsigned t;
277 	unsigned p;
278 	uint64_t page_base;
279 	int i, j;
280 
281 	if (!adev->gart.ready) {
282 		WARN(1, "trying to bind memory to uninitialized GART !\n");
283 		return -EINVAL;
284 	}
285 
286 	t = offset / AMDGPU_GPU_PAGE_SIZE;
287 	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
288 
289 	for (i = 0; i < pages; i++, p++) {
290 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
291 		adev->gart.pages[p] = pagelist[i];
292 #endif
293 		if (adev->gart.ptr) {
294 			page_base = dma_addr[i];
295 			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
296 				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
297 				page_base += AMDGPU_GPU_PAGE_SIZE;
298 			}
299 		}
300 	}
301 	mb();
302 	amdgpu_gart_flush_gpu_tlb(adev, 0);
303 	return 0;
304 }
305 
306 /**
307  * amdgpu_gart_init - init the driver info for managing the gart
308  *
309  * @adev: amdgpu_device pointer
310  *
311  * Allocate the dummy page and init the gart driver info (all asics).
312  * Returns 0 for success, error for failure.
313  */
314 int amdgpu_gart_init(struct amdgpu_device *adev)
315 {
316 	int r;
317 
318 	if (adev->dummy_page.page)
319 		return 0;
320 
321 	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
322 	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
323 		DRM_ERROR("Page size is smaller than GPU page size!\n");
324 		return -EINVAL;
325 	}
326 	r = amdgpu_dummy_page_init(adev);
327 	if (r)
328 		return r;
329 	/* Compute table size */
330 	adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
331 	adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
332 	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
333 		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
334 
335 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
336 	/* Allocate pages table */
337 	adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
338 	if (adev->gart.pages == NULL) {
339 		amdgpu_gart_fini(adev);
340 		return -ENOMEM;
341 	}
342 #endif
343 
344 	return 0;
345 }
346 
347 /**
348  * amdgpu_gart_fini - tear down the driver info for managing the gart
349  *
350  * @adev: amdgpu_device pointer
351  *
352  * Tear down the gart driver info and free the dummy page (all asics).
353  */
354 void amdgpu_gart_fini(struct amdgpu_device *adev)
355 {
356 	if (adev->gart.ready) {
357 		/* unbind pages */
358 		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
359 	}
360 	adev->gart.ready = false;
361 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
362 	vfree(adev->gart.pages);
363 	adev->gart.pages = NULL;
364 #endif
365 	amdgpu_dummy_page_fini(adev);
366 }
367