1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include <drm/amdgpu_drm.h> 30 #ifdef CONFIG_X86 31 #include <asm/set_memory.h> 32 #endif 33 #include "amdgpu.h" 34 35 /* 36 * GART 37 * The GART (Graphics Aperture Remapping Table) is an aperture 38 * in the GPU's address space. System pages can be mapped into 39 * the aperture and look like contiguous pages from the GPU's 40 * perspective. A page table maps the pages in the aperture 41 * to the actual backing pages in system memory. 42 * 43 * Radeon GPUs support both an internal GART, as described above, 44 * and AGP. AGP works similarly, but the GART table is configured 45 * and maintained by the northbridge rather than the driver. 46 * Radeon hw has a separate AGP aperture that is programmed to 47 * point to the AGP aperture provided by the northbridge and the 48 * requests are passed through to the northbridge aperture. 49 * Both AGP and internal GART can be used at the same time, however 50 * that is not currently supported by the driver. 51 * 52 * This file handles the common internal GART management. 53 */ 54 55 /* 56 * Common GART table functions. 57 */ 58 59 /** 60 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table 61 * 62 * @adev: amdgpu_device pointer 63 * 64 * Allocate system memory for GART page table 65 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 66 * gart table to be in system memory. 67 * Returns 0 for success, -ENOMEM for failure. 68 */ 69 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) 70 { 71 void *ptr; 72 73 ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size, 74 &adev->gart.table_addr); 75 if (ptr == NULL) { 76 return -ENOMEM; 77 } 78 #ifdef CONFIG_X86 79 if (0) { 80 set_memory_uc((unsigned long)ptr, 81 adev->gart.table_size >> PAGE_SHIFT); 82 } 83 #endif 84 adev->gart.ptr = ptr; 85 memset((void *)adev->gart.ptr, 0, adev->gart.table_size); 86 return 0; 87 } 88 89 /** 90 * amdgpu_gart_table_ram_free - free system ram for gart page table 91 * 92 * @adev: amdgpu_device pointer 93 * 94 * Free system memory for GART page table 95 * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the 96 * gart table to be in system memory. 97 */ 98 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) 99 { 100 if (adev->gart.ptr == NULL) { 101 return; 102 } 103 #ifdef CONFIG_X86 104 if (0) { 105 set_memory_wb((unsigned long)adev->gart.ptr, 106 adev->gart.table_size >> PAGE_SHIFT); 107 } 108 #endif 109 pci_free_consistent(adev->pdev, adev->gart.table_size, 110 (void *)adev->gart.ptr, 111 adev->gart.table_addr); 112 adev->gart.ptr = NULL; 113 adev->gart.table_addr = 0; 114 } 115 116 /** 117 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 118 * 119 * @adev: amdgpu_device pointer 120 * 121 * Allocate video memory for GART page table 122 * (pcie r4xx, r5xx+). These asics require the 123 * gart table to be in video memory. 124 * Returns 0 for success, error for failure. 125 */ 126 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 127 { 128 int r; 129 130 if (adev->gart.robj == NULL) { 131 r = amdgpu_bo_create(adev, adev->gart.table_size, 132 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 133 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 134 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, 135 NULL, NULL, 0, &adev->gart.robj); 136 if (r) { 137 return r; 138 } 139 } 140 return 0; 141 } 142 143 /** 144 * amdgpu_gart_table_vram_pin - pin gart page table in vram 145 * 146 * @adev: amdgpu_device pointer 147 * 148 * Pin the GART page table in vram so it will not be moved 149 * by the memory manager (pcie r4xx, r5xx+). These asics require the 150 * gart table to be in video memory. 151 * Returns 0 for success, error for failure. 152 */ 153 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 154 { 155 uint64_t gpu_addr; 156 int r; 157 158 r = amdgpu_bo_reserve(adev->gart.robj, false); 159 if (unlikely(r != 0)) 160 return r; 161 r = amdgpu_bo_pin(adev->gart.robj, 162 AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr); 163 if (r) { 164 amdgpu_bo_unreserve(adev->gart.robj); 165 return r; 166 } 167 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); 168 if (r) 169 amdgpu_bo_unpin(adev->gart.robj); 170 amdgpu_bo_unreserve(adev->gart.robj); 171 adev->gart.table_addr = gpu_addr; 172 return r; 173 } 174 175 /** 176 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram 177 * 178 * @adev: amdgpu_device pointer 179 * 180 * Unpin the GART page table in vram (pcie r4xx, r5xx+). 181 * These asics require the gart table to be in video memory. 182 */ 183 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev) 184 { 185 int r; 186 187 if (adev->gart.robj == NULL) { 188 return; 189 } 190 r = amdgpu_bo_reserve(adev->gart.robj, true); 191 if (likely(r == 0)) { 192 amdgpu_bo_kunmap(adev->gart.robj); 193 amdgpu_bo_unpin(adev->gart.robj); 194 amdgpu_bo_unreserve(adev->gart.robj); 195 adev->gart.ptr = NULL; 196 } 197 } 198 199 /** 200 * amdgpu_gart_table_vram_free - free gart page table vram 201 * 202 * @adev: amdgpu_device pointer 203 * 204 * Free the video memory used for the GART page table 205 * (pcie r4xx, r5xx+). These asics require the gart table to 206 * be in video memory. 207 */ 208 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 209 { 210 if (adev->gart.robj == NULL) { 211 return; 212 } 213 amdgpu_bo_unref(&adev->gart.robj); 214 } 215 216 /* 217 * Common gart functions. 218 */ 219 /** 220 * amdgpu_gart_unbind - unbind pages from the gart page table 221 * 222 * @adev: amdgpu_device pointer 223 * @offset: offset into the GPU's gart aperture 224 * @pages: number of pages to unbind 225 * 226 * Unbinds the requested pages from the gart page table and 227 * replaces them with the dummy page (all asics). 228 * Returns 0 for success, -EINVAL for failure. 229 */ 230 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 231 int pages) 232 { 233 unsigned t; 234 unsigned p; 235 int i, j; 236 u64 page_base; 237 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 238 uint64_t flags = 0; 239 240 if (!adev->gart.ready) { 241 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 242 return -EINVAL; 243 } 244 245 t = offset / AMDGPU_GPU_PAGE_SIZE; 246 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 247 for (i = 0; i < pages; i++, p++) { 248 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 249 adev->gart.pages[p] = NULL; 250 #endif 251 page_base = adev->dummy_page.addr; 252 if (!adev->gart.ptr) 253 continue; 254 255 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { 256 amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, 257 t, page_base, flags); 258 page_base += AMDGPU_GPU_PAGE_SIZE; 259 } 260 } 261 mb(); 262 amdgpu_gart_flush_gpu_tlb(adev, 0); 263 return 0; 264 } 265 266 /** 267 * amdgpu_gart_map - map dma_addresses into GART entries 268 * 269 * @adev: amdgpu_device pointer 270 * @offset: offset into the GPU's gart aperture 271 * @pages: number of pages to bind 272 * @dma_addr: DMA addresses of pages 273 * 274 * Map the dma_addresses into GART entries (all asics). 275 * Returns 0 for success, -EINVAL for failure. 276 */ 277 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 278 int pages, dma_addr_t *dma_addr, uint64_t flags, 279 void *dst) 280 { 281 uint64_t page_base; 282 unsigned i, j, t; 283 284 if (!adev->gart.ready) { 285 WARN(1, "trying to bind memory to uninitialized GART !\n"); 286 return -EINVAL; 287 } 288 289 t = offset / AMDGPU_GPU_PAGE_SIZE; 290 291 for (i = 0; i < pages; i++) { 292 page_base = dma_addr[i]; 293 for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { 294 amdgpu_gart_set_pte_pde(adev, dst, t, page_base, flags); 295 page_base += AMDGPU_GPU_PAGE_SIZE; 296 } 297 } 298 return 0; 299 } 300 301 /** 302 * amdgpu_gart_bind - bind pages into the gart page table 303 * 304 * @adev: amdgpu_device pointer 305 * @offset: offset into the GPU's gart aperture 306 * @pages: number of pages to bind 307 * @pagelist: pages to bind 308 * @dma_addr: DMA addresses of pages 309 * 310 * Binds the requested pages to the gart page table 311 * (all asics). 312 * Returns 0 for success, -EINVAL for failure. 313 */ 314 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 315 int pages, struct page **pagelist, dma_addr_t *dma_addr, 316 uint64_t flags) 317 { 318 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 319 unsigned i,t,p; 320 #endif 321 int r; 322 323 if (!adev->gart.ready) { 324 WARN(1, "trying to bind memory to uninitialized GART !\n"); 325 return -EINVAL; 326 } 327 328 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 329 t = offset / AMDGPU_GPU_PAGE_SIZE; 330 p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 331 for (i = 0; i < pages; i++, p++) 332 adev->gart.pages[p] = pagelist[i]; 333 #endif 334 335 if (!adev->gart.ptr) 336 return 0; 337 338 r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 339 adev->gart.ptr); 340 if (r) 341 return r; 342 343 mb(); 344 amdgpu_gart_flush_gpu_tlb(adev, 0); 345 return 0; 346 } 347 348 /** 349 * amdgpu_gart_init - init the driver info for managing the gart 350 * 351 * @adev: amdgpu_device pointer 352 * 353 * Allocate the dummy page and init the gart driver info (all asics). 354 * Returns 0 for success, error for failure. 355 */ 356 int amdgpu_gart_init(struct amdgpu_device *adev) 357 { 358 int r; 359 360 if (adev->dummy_page.page) 361 return 0; 362 363 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 364 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 365 DRM_ERROR("Page size is smaller than GPU page size!\n"); 366 return -EINVAL; 367 } 368 r = amdgpu_dummy_page_init(adev); 369 if (r) 370 return r; 371 /* Compute table size */ 372 adev->gart.num_cpu_pages = adev->mc.gart_size / PAGE_SIZE; 373 adev->gart.num_gpu_pages = adev->mc.gart_size / AMDGPU_GPU_PAGE_SIZE; 374 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 375 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 376 377 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 378 /* Allocate pages table */ 379 adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); 380 if (adev->gart.pages == NULL) { 381 amdgpu_gart_fini(adev); 382 return -ENOMEM; 383 } 384 #endif 385 386 return 0; 387 } 388 389 /** 390 * amdgpu_gart_fini - tear down the driver info for managing the gart 391 * 392 * @adev: amdgpu_device pointer 393 * 394 * Tear down the gart driver info and free the dummy page (all asics). 395 */ 396 void amdgpu_gart_fini(struct amdgpu_device *adev) 397 { 398 if (adev->gart.ready) { 399 /* unbind pages */ 400 amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); 401 } 402 adev->gart.ready = false; 403 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 404 vfree(adev->gart.pages); 405 adev->gart.pages = NULL; 406 #endif 407 amdgpu_dummy_page_fini(adev); 408 } 409