1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/pci.h> 30 #include <linux/vmalloc.h> 31 32 #include <drm/amdgpu_drm.h> 33 #ifdef CONFIG_X86 34 #include <asm/set_memory.h> 35 #endif 36 #include "amdgpu.h" 37 #include <drm/drm_drv.h> 38 39 /* 40 * GART 41 * The GART (Graphics Aperture Remapping Table) is an aperture 42 * in the GPU's address space. System pages can be mapped into 43 * the aperture and look like contiguous pages from the GPU's 44 * perspective. A page table maps the pages in the aperture 45 * to the actual backing pages in system memory. 46 * 47 * Radeon GPUs support both an internal GART, as described above, 48 * and AGP. AGP works similarly, but the GART table is configured 49 * and maintained by the northbridge rather than the driver. 50 * Radeon hw has a separate AGP aperture that is programmed to 51 * point to the AGP aperture provided by the northbridge and the 52 * requests are passed through to the northbridge aperture. 53 * Both AGP and internal GART can be used at the same time, however 54 * that is not currently supported by the driver. 55 * 56 * This file handles the common internal GART management. 57 */ 58 59 /* 60 * Common GART table functions. 61 */ 62 63 /** 64 * amdgpu_gart_dummy_page_init - init dummy page used by the driver 65 * 66 * @adev: amdgpu_device pointer 67 * 68 * Allocate the dummy page used by the driver (all asics). 69 * This dummy page is used by the driver as a filler for gart entries 70 * when pages are taken out of the GART 71 * Returns 0 on sucess, -ENOMEM on failure. 72 */ 73 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) 74 { 75 struct page *dummy_page = ttm_glob.dummy_read_page; 76 77 if (adev->dummy_page_addr) 78 return 0; 79 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, 80 PAGE_SIZE, DMA_BIDIRECTIONAL); 81 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { 82 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 83 adev->dummy_page_addr = 0; 84 return -ENOMEM; 85 } 86 return 0; 87 } 88 89 /** 90 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver 91 * 92 * @adev: amdgpu_device pointer 93 * 94 * Frees the dummy page used by the driver (all asics). 95 */ 96 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) 97 { 98 if (!adev->dummy_page_addr) 99 return; 100 dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, 101 DMA_BIDIRECTIONAL); 102 adev->dummy_page_addr = 0; 103 } 104 105 /** 106 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table 107 * 108 * @adev: amdgpu_device pointer 109 * 110 * Allocate video memory for GART page table 111 * (pcie r4xx, r5xx+). These asics require the 112 * gart table to be in video memory. 113 * Returns 0 for success, error for failure. 114 */ 115 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev) 116 { 117 if (adev->gart.bo != NULL) 118 return 0; 119 120 return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE, 121 AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo, 122 NULL, (void *)&adev->gart.ptr); 123 } 124 125 /** 126 * amdgpu_gart_table_vram_free - free gart page table vram 127 * 128 * @adev: amdgpu_device pointer 129 * 130 * Free the video memory used for the GART page table 131 * (pcie r4xx, r5xx+). These asics require the gart table to 132 * be in video memory. 133 */ 134 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) 135 { 136 amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr); 137 } 138 139 /* 140 * Common gart functions. 141 */ 142 /** 143 * amdgpu_gart_unbind - unbind pages from the gart page table 144 * 145 * @adev: amdgpu_device pointer 146 * @offset: offset into the GPU's gart aperture 147 * @pages: number of pages to unbind 148 * 149 * Unbinds the requested pages from the gart page table and 150 * replaces them with the dummy page (all asics). 151 * Returns 0 for success, -EINVAL for failure. 152 */ 153 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 154 int pages) 155 { 156 unsigned t; 157 unsigned p; 158 int i, j; 159 u64 page_base; 160 /* Starting from VEGA10, system bit must be 0 to mean invalid. */ 161 uint64_t flags = 0; 162 int idx; 163 164 if (!adev->gart.ready) { 165 WARN(1, "trying to unbind memory from uninitialized GART !\n"); 166 return -EINVAL; 167 } 168 169 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 170 return 0; 171 172 t = offset / AMDGPU_GPU_PAGE_SIZE; 173 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE; 174 for (i = 0; i < pages; i++, p++) { 175 page_base = adev->dummy_page_addr; 176 if (!adev->gart.ptr) 177 continue; 178 179 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 180 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, 181 t, page_base, flags); 182 page_base += AMDGPU_GPU_PAGE_SIZE; 183 } 184 } 185 mb(); 186 amdgpu_device_flush_hdp(adev, NULL); 187 for (i = 0; i < adev->num_vmhubs; i++) 188 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 189 190 drm_dev_exit(idx); 191 return 0; 192 } 193 194 /** 195 * amdgpu_gart_map - map dma_addresses into GART entries 196 * 197 * @adev: amdgpu_device pointer 198 * @offset: offset into the GPU's gart aperture 199 * @pages: number of pages to bind 200 * @dma_addr: DMA addresses of pages 201 * @flags: page table entry flags 202 * @dst: CPU address of the gart table 203 * 204 * Map the dma_addresses into GART entries (all asics). 205 * Returns 0 for success, -EINVAL for failure. 206 */ 207 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 208 int pages, dma_addr_t *dma_addr, uint64_t flags, 209 void *dst) 210 { 211 uint64_t page_base; 212 unsigned i, j, t; 213 int idx; 214 215 if (!adev->gart.ready) { 216 WARN(1, "trying to bind memory to uninitialized GART !\n"); 217 return -EINVAL; 218 } 219 220 if (!drm_dev_enter(adev_to_drm(adev), &idx)) 221 return 0; 222 223 t = offset / AMDGPU_GPU_PAGE_SIZE; 224 225 for (i = 0; i < pages; i++) { 226 page_base = dma_addr[i]; 227 for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { 228 amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); 229 page_base += AMDGPU_GPU_PAGE_SIZE; 230 } 231 } 232 drm_dev_exit(idx); 233 return 0; 234 } 235 236 /** 237 * amdgpu_gart_bind - bind pages into the gart page table 238 * 239 * @adev: amdgpu_device pointer 240 * @offset: offset into the GPU's gart aperture 241 * @pages: number of pages to bind 242 * @dma_addr: DMA addresses of pages 243 * @flags: page table entry flags 244 * 245 * Binds the requested pages to the gart page table 246 * (all asics). 247 * Returns 0 for success, -EINVAL for failure. 248 */ 249 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 250 int pages, dma_addr_t *dma_addr, 251 uint64_t flags) 252 { 253 if (!adev->gart.ready) { 254 WARN(1, "trying to bind memory to uninitialized GART !\n"); 255 return -EINVAL; 256 } 257 258 if (!adev->gart.ptr) 259 return 0; 260 261 return amdgpu_gart_map(adev, offset, pages, dma_addr, flags, 262 adev->gart.ptr); 263 } 264 265 /** 266 * amdgpu_gart_invalidate_tlb - invalidate gart TLB 267 * 268 * @adev: amdgpu device driver pointer 269 * 270 * Invalidate gart TLB which can be use as a way to flush gart changes 271 * 272 */ 273 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) 274 { 275 int i; 276 277 mb(); 278 amdgpu_device_flush_hdp(adev, NULL); 279 for (i = 0; i < adev->num_vmhubs; i++) 280 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); 281 } 282 283 /** 284 * amdgpu_gart_init - init the driver info for managing the gart 285 * 286 * @adev: amdgpu_device pointer 287 * 288 * Allocate the dummy page and init the gart driver info (all asics). 289 * Returns 0 for success, error for failure. 290 */ 291 int amdgpu_gart_init(struct amdgpu_device *adev) 292 { 293 int r; 294 295 if (adev->dummy_page_addr) 296 return 0; 297 298 /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */ 299 if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) { 300 DRM_ERROR("Page size is smaller than GPU page size!\n"); 301 return -EINVAL; 302 } 303 r = amdgpu_gart_dummy_page_init(adev); 304 if (r) 305 return r; 306 /* Compute table size */ 307 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; 308 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; 309 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 310 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); 311 312 return 0; 313 } 314