1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Dave Airlie
30  */
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/kref.h>
35 #include <linux/slab.h>
36 #include <linux/firmware.h>
37 #include <drm/drmP.h>
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 
41 /*
42  * Fences
43  * Fences mark an event in the GPUs pipeline and are used
44  * for GPU/CPU synchronization.  When the fence is written,
45  * it is expected that all buffers associated with that fence
46  * are no longer in use by the associated ring on the GPU and
47  * that the the relevant GPU caches have been flushed.
48  */
49 
50 /**
51  * amdgpu_fence_write - write a fence value
52  *
53  * @ring: ring the fence is associated with
54  * @seq: sequence number to write
55  *
56  * Writes a fence value to memory (all asics).
57  */
58 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
59 {
60 	struct amdgpu_fence_driver *drv = &ring->fence_drv;
61 
62 	if (drv->cpu_addr)
63 		*drv->cpu_addr = cpu_to_le32(seq);
64 }
65 
66 /**
67  * amdgpu_fence_read - read a fence value
68  *
69  * @ring: ring the fence is associated with
70  *
71  * Reads a fence value from memory (all asics).
72  * Returns the value of the fence read from memory.
73  */
74 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
75 {
76 	struct amdgpu_fence_driver *drv = &ring->fence_drv;
77 	u32 seq = 0;
78 
79 	if (drv->cpu_addr)
80 		seq = le32_to_cpu(*drv->cpu_addr);
81 	else
82 		seq = lower_32_bits(atomic64_read(&drv->last_seq));
83 
84 	return seq;
85 }
86 
87 /**
88  * amdgpu_fence_schedule_check - schedule lockup check
89  *
90  * @ring: pointer to struct amdgpu_ring
91  *
92  * Queues a delayed work item to check for lockups.
93  */
94 static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring)
95 {
96 	/*
97 	 * Do not reset the timer here with mod_delayed_work,
98 	 * this can livelock in an interaction with TTM delayed destroy.
99 	 */
100 	queue_delayed_work(system_power_efficient_wq,
101 		&ring->fence_drv.lockup_work,
102 		AMDGPU_FENCE_JIFFIES_TIMEOUT);
103 }
104 
105 /**
106  * amdgpu_fence_emit - emit a fence on the requested ring
107  *
108  * @ring: ring the fence is associated with
109  * @owner: creator of the fence
110  * @fence: amdgpu fence object
111  *
112  * Emits a fence command on the requested ring (all asics).
113  * Returns 0 on success, -ENOMEM on failure.
114  */
115 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
116 		      struct amdgpu_fence **fence)
117 {
118 	struct amdgpu_device *adev = ring->adev;
119 
120 	/* we are protected by the ring emission mutex */
121 	*fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
122 	if ((*fence) == NULL) {
123 		return -ENOMEM;
124 	}
125 	(*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
126 	(*fence)->ring = ring;
127 	(*fence)->owner = owner;
128 	fence_init(&(*fence)->base, &amdgpu_fence_ops,
129 		&ring->fence_drv.fence_queue.lock,
130 		adev->fence_context + ring->idx,
131 		(*fence)->seq);
132 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
133 			       (*fence)->seq,
134 			       AMDGPU_FENCE_FLAG_INT);
135 	trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq);
136 	return 0;
137 }
138 
139 /**
140  * amdgpu_fence_check_signaled - callback from fence_queue
141  *
142  * this function is called with fence_queue lock held, which is also used
143  * for the fence locking itself, so unlocked variants are used for
144  * fence_signal, and remove_wait_queue.
145  */
146 static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
147 {
148 	struct amdgpu_fence *fence;
149 	struct amdgpu_device *adev;
150 	u64 seq;
151 	int ret;
152 
153 	fence = container_of(wait, struct amdgpu_fence, fence_wake);
154 	adev = fence->ring->adev;
155 
156 	/*
157 	 * We cannot use amdgpu_fence_process here because we're already
158 	 * in the waitqueue, in a call from wake_up_all.
159 	 */
160 	seq = atomic64_read(&fence->ring->fence_drv.last_seq);
161 	if (seq >= fence->seq) {
162 		ret = fence_signal_locked(&fence->base);
163 		if (!ret)
164 			FENCE_TRACE(&fence->base, "signaled from irq context\n");
165 		else
166 			FENCE_TRACE(&fence->base, "was already signaled\n");
167 
168 		__remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake);
169 		fence_put(&fence->base);
170 	} else
171 		FENCE_TRACE(&fence->base, "pending\n");
172 	return 0;
173 }
174 
175 /**
176  * amdgpu_fence_activity - check for fence activity
177  *
178  * @ring: pointer to struct amdgpu_ring
179  *
180  * Checks the current fence value and calculates the last
181  * signalled fence value. Returns true if activity occured
182  * on the ring, and the fence_queue should be waken up.
183  */
184 static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
185 {
186 	uint64_t seq, last_seq, last_emitted;
187 	unsigned count_loop = 0;
188 	bool wake = false;
189 
190 	/* Note there is a scenario here for an infinite loop but it's
191 	 * very unlikely to happen. For it to happen, the current polling
192 	 * process need to be interrupted by another process and another
193 	 * process needs to update the last_seq btw the atomic read and
194 	 * xchg of the current process.
195 	 *
196 	 * More over for this to go in infinite loop there need to be
197 	 * continuously new fence signaled ie amdgpu_fence_read needs
198 	 * to return a different value each time for both the currently
199 	 * polling process and the other process that xchg the last_seq
200 	 * btw atomic read and xchg of the current process. And the
201 	 * value the other process set as last seq must be higher than
202 	 * the seq value we just read. Which means that current process
203 	 * need to be interrupted after amdgpu_fence_read and before
204 	 * atomic xchg.
205 	 *
206 	 * To be even more safe we count the number of time we loop and
207 	 * we bail after 10 loop just accepting the fact that we might
208 	 * have temporarly set the last_seq not to the true real last
209 	 * seq but to an older one.
210 	 */
211 	last_seq = atomic64_read(&ring->fence_drv.last_seq);
212 	do {
213 		last_emitted = ring->fence_drv.sync_seq[ring->idx];
214 		seq = amdgpu_fence_read(ring);
215 		seq |= last_seq & 0xffffffff00000000LL;
216 		if (seq < last_seq) {
217 			seq &= 0xffffffff;
218 			seq |= last_emitted & 0xffffffff00000000LL;
219 		}
220 
221 		if (seq <= last_seq || seq > last_emitted) {
222 			break;
223 		}
224 		/* If we loop over we don't want to return without
225 		 * checking if a fence is signaled as it means that the
226 		 * seq we just read is different from the previous on.
227 		 */
228 		wake = true;
229 		last_seq = seq;
230 		if ((count_loop++) > 10) {
231 			/* We looped over too many time leave with the
232 			 * fact that we might have set an older fence
233 			 * seq then the current real last seq as signaled
234 			 * by the hw.
235 			 */
236 			break;
237 		}
238 	} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
239 
240 	if (seq < last_emitted)
241 		amdgpu_fence_schedule_check(ring);
242 
243 	return wake;
244 }
245 
246 /**
247  * amdgpu_fence_check_lockup - check for hardware lockup
248  *
249  * @work: delayed work item
250  *
251  * Checks for fence activity and if there is none probe
252  * the hardware if a lockup occured.
253  */
254 static void amdgpu_fence_check_lockup(struct work_struct *work)
255 {
256 	struct amdgpu_fence_driver *fence_drv;
257 	struct amdgpu_ring *ring;
258 
259 	fence_drv = container_of(work, struct amdgpu_fence_driver,
260 				lockup_work.work);
261 	ring = fence_drv->ring;
262 
263 	if (!down_read_trylock(&ring->adev->exclusive_lock)) {
264 		/* just reschedule the check if a reset is going on */
265 		amdgpu_fence_schedule_check(ring);
266 		return;
267 	}
268 
269 	if (amdgpu_fence_activity(ring)) {
270 		wake_up_all(&ring->fence_drv.fence_queue);
271 	}
272 	else if (amdgpu_ring_is_lockup(ring)) {
273 		/* good news we believe it's a lockup */
274 		dev_warn(ring->adev->dev, "GPU lockup (current fence id "
275 			"0x%016llx last fence id 0x%016llx on ring %d)\n",
276 			(uint64_t)atomic64_read(&fence_drv->last_seq),
277 			fence_drv->sync_seq[ring->idx], ring->idx);
278 
279 		/* remember that we need an reset */
280 		ring->adev->needs_reset = true;
281 		wake_up_all(&ring->fence_drv.fence_queue);
282 	}
283 	up_read(&ring->adev->exclusive_lock);
284 }
285 
286 /**
287  * amdgpu_fence_process - process a fence
288  *
289  * @adev: amdgpu_device pointer
290  * @ring: ring index the fence is associated with
291  *
292  * Checks the current fence value and wakes the fence queue
293  * if the sequence number has increased (all asics).
294  */
295 void amdgpu_fence_process(struct amdgpu_ring *ring)
296 {
297 	if (amdgpu_fence_activity(ring))
298 		wake_up_all(&ring->fence_drv.fence_queue);
299 }
300 
301 /**
302  * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
303  *
304  * @ring: ring the fence is associated with
305  * @seq: sequence number
306  *
307  * Check if the last signaled fence sequnce number is >= the requested
308  * sequence number (all asics).
309  * Returns true if the fence has signaled (current fence value
310  * is >= requested value) or false if it has not (current fence
311  * value is < the requested value.  Helper function for
312  * amdgpu_fence_signaled().
313  */
314 static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
315 {
316 	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
317 		return true;
318 
319 	/* poll new last sequence at least once */
320 	amdgpu_fence_process(ring);
321 	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
322 		return true;
323 
324 	return false;
325 }
326 
327 static bool amdgpu_fence_is_signaled(struct fence *f)
328 {
329 	struct amdgpu_fence *fence = to_amdgpu_fence(f);
330 	struct amdgpu_ring *ring = fence->ring;
331 	struct amdgpu_device *adev = ring->adev;
332 
333 	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
334 		return true;
335 
336 	if (down_read_trylock(&adev->exclusive_lock)) {
337 		amdgpu_fence_process(ring);
338 		up_read(&adev->exclusive_lock);
339 
340 		if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
341 			return true;
342 	}
343 	return false;
344 }
345 
346 /**
347  * amdgpu_fence_enable_signaling - enable signalling on fence
348  * @fence: fence
349  *
350  * This function is called with fence_queue lock held, and adds a callback
351  * to fence_queue that checks if this fence is signaled, and if so it
352  * signals the fence and removes itself.
353  */
354 static bool amdgpu_fence_enable_signaling(struct fence *f)
355 {
356 	struct amdgpu_fence *fence = to_amdgpu_fence(f);
357 	struct amdgpu_ring *ring = fence->ring;
358 
359 	if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
360 		return false;
361 
362 	fence->fence_wake.flags = 0;
363 	fence->fence_wake.private = NULL;
364 	fence->fence_wake.func = amdgpu_fence_check_signaled;
365 	__add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake);
366 	fence_get(f);
367 	FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
368 	return true;
369 }
370 
371 /*
372  * amdgpu_ring_wait_seq_timeout - wait for seq of the specific ring to signal
373  * @ring: ring to wait on for the seq number
374  * @seq: seq number wait for
375  *
376  * return value:
377  * 0: seq signaled, and gpu not hang
378  * -EDEADL: GPU hang detected
379  * -EINVAL: some paramter is not valid
380  */
381 static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
382 {
383 	struct amdgpu_device *adev = ring->adev;
384 	bool signaled = false;
385 
386 	BUG_ON(!ring);
387 	if (seq > ring->fence_drv.sync_seq[ring->idx])
388 		return -EINVAL;
389 
390 	if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
391 		return 0;
392 
393 	wait_event(ring->fence_drv.fence_queue, (
394 		   (signaled = amdgpu_fence_seq_signaled(ring, seq))
395 		   || adev->needs_reset));
396 
397 	if (signaled)
398 		return 0;
399 	else
400 		return -EDEADLK;
401 }
402 
403 /**
404  * amdgpu_fence_wait_next - wait for the next fence to signal
405  *
406  * @adev: amdgpu device pointer
407  * @ring: ring index the fence is associated with
408  *
409  * Wait for the next fence on the requested ring to signal (all asics).
410  * Returns 0 if the next fence has passed, error for all other cases.
411  * Caller must hold ring lock.
412  */
413 int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
414 {
415 	uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
416 
417 	if (seq >= ring->fence_drv.sync_seq[ring->idx])
418 		return -ENOENT;
419 
420 	return amdgpu_fence_ring_wait_seq(ring, seq);
421 }
422 
423 /**
424  * amdgpu_fence_wait_empty - wait for all fences to signal
425  *
426  * @adev: amdgpu device pointer
427  * @ring: ring index the fence is associated with
428  *
429  * Wait for all fences on the requested ring to signal (all asics).
430  * Returns 0 if the fences have passed, error for all other cases.
431  * Caller must hold ring lock.
432  */
433 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
434 {
435 	uint64_t seq = ring->fence_drv.sync_seq[ring->idx];
436 
437 	if (!seq)
438 		return 0;
439 
440 	return amdgpu_fence_ring_wait_seq(ring, seq);
441 }
442 
443 /**
444  * amdgpu_fence_ref - take a ref on a fence
445  *
446  * @fence: amdgpu fence object
447  *
448  * Take a reference on a fence (all asics).
449  * Returns the fence.
450  */
451 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence)
452 {
453 	fence_get(&fence->base);
454 	return fence;
455 }
456 
457 /**
458  * amdgpu_fence_unref - remove a ref on a fence
459  *
460  * @fence: amdgpu fence object
461  *
462  * Remove a reference on a fence (all asics).
463  */
464 void amdgpu_fence_unref(struct amdgpu_fence **fence)
465 {
466 	struct amdgpu_fence *tmp = *fence;
467 
468 	*fence = NULL;
469 	if (tmp)
470 		fence_put(&tmp->base);
471 }
472 
473 /**
474  * amdgpu_fence_count_emitted - get the count of emitted fences
475  *
476  * @ring: ring the fence is associated with
477  *
478  * Get the number of fences emitted on the requested ring (all asics).
479  * Returns the number of emitted fences on the ring.  Used by the
480  * dynpm code to ring track activity.
481  */
482 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
483 {
484 	uint64_t emitted;
485 
486 	/* We are not protected by ring lock when reading the last sequence
487 	 * but it's ok to report slightly wrong fence count here.
488 	 */
489 	amdgpu_fence_process(ring);
490 	emitted = ring->fence_drv.sync_seq[ring->idx]
491 		- atomic64_read(&ring->fence_drv.last_seq);
492 	/* to avoid 32bits warp around */
493 	if (emitted > 0x10000000)
494 		emitted = 0x10000000;
495 
496 	return (unsigned)emitted;
497 }
498 
499 /**
500  * amdgpu_fence_need_sync - do we need a semaphore
501  *
502  * @fence: amdgpu fence object
503  * @dst_ring: which ring to check against
504  *
505  * Check if the fence needs to be synced against another ring
506  * (all asics).  If so, we need to emit a semaphore.
507  * Returns true if we need to sync with another ring, false if
508  * not.
509  */
510 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
511 			    struct amdgpu_ring *dst_ring)
512 {
513 	struct amdgpu_fence_driver *fdrv;
514 
515 	if (!fence)
516 		return false;
517 
518 	if (fence->ring == dst_ring)
519 		return false;
520 
521 	/* we are protected by the ring mutex */
522 	fdrv = &dst_ring->fence_drv;
523 	if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
524 		return false;
525 
526 	return true;
527 }
528 
529 /**
530  * amdgpu_fence_note_sync - record the sync point
531  *
532  * @fence: amdgpu fence object
533  * @dst_ring: which ring to check against
534  *
535  * Note the sequence number at which point the fence will
536  * be synced with the requested ring (all asics).
537  */
538 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
539 			    struct amdgpu_ring *dst_ring)
540 {
541 	struct amdgpu_fence_driver *dst, *src;
542 	unsigned i;
543 
544 	if (!fence)
545 		return;
546 
547 	if (fence->ring == dst_ring)
548 		return;
549 
550 	/* we are protected by the ring mutex */
551 	src = &fence->ring->fence_drv;
552 	dst = &dst_ring->fence_drv;
553 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
554 		if (i == dst_ring->idx)
555 			continue;
556 
557 		dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
558 	}
559 }
560 
561 /**
562  * amdgpu_fence_driver_start_ring - make the fence driver
563  * ready for use on the requested ring.
564  *
565  * @ring: ring to start the fence driver on
566  * @irq_src: interrupt source to use for this ring
567  * @irq_type: interrupt type to use for this ring
568  *
569  * Make the fence driver ready for processing (all asics).
570  * Not all asics have all rings, so each asic will only
571  * start the fence driver on the rings it has.
572  * Returns 0 for success, errors for failure.
573  */
574 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
575 				   struct amdgpu_irq_src *irq_src,
576 				   unsigned irq_type)
577 {
578 	struct amdgpu_device *adev = ring->adev;
579 	uint64_t index;
580 
581 	if (ring != &adev->uvd.ring) {
582 		ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
583 		ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
584 	} else {
585 		/* put fence directly behind firmware */
586 		index = ALIGN(adev->uvd.fw->size, 8);
587 		ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
588 		ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
589 	}
590 	amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
591 	amdgpu_irq_get(adev, irq_src, irq_type);
592 
593 	ring->fence_drv.irq_src = irq_src;
594 	ring->fence_drv.irq_type = irq_type;
595 	ring->fence_drv.initialized = true;
596 
597 	dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
598 		 "cpu addr 0x%p\n", ring->idx,
599 		 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
600 	return 0;
601 }
602 
603 /**
604  * amdgpu_fence_driver_init_ring - init the fence driver
605  * for the requested ring.
606  *
607  * @ring: ring to init the fence driver on
608  *
609  * Init the fence driver for the requested ring (all asics).
610  * Helper function for amdgpu_fence_driver_init().
611  */
612 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
613 {
614 	int i;
615 
616 	ring->fence_drv.cpu_addr = NULL;
617 	ring->fence_drv.gpu_addr = 0;
618 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
619 		ring->fence_drv.sync_seq[i] = 0;
620 
621 	atomic64_set(&ring->fence_drv.last_seq, 0);
622 	ring->fence_drv.initialized = false;
623 
624 	INIT_DELAYED_WORK(&ring->fence_drv.lockup_work,
625 			amdgpu_fence_check_lockup);
626 	ring->fence_drv.ring = ring;
627 
628 	if (amdgpu_enable_scheduler) {
629 		ring->scheduler = amd_sched_create(&amdgpu_sched_ops,
630 						   ring->idx,
631 						   amdgpu_sched_hw_submission,
632 						   (void *)ring->adev);
633 		if (!ring->scheduler)
634 			DRM_ERROR("Failed to create scheduler on ring %d.\n",
635 				  ring->idx);
636 	}
637 }
638 
639 /**
640  * amdgpu_fence_driver_init - init the fence driver
641  * for all possible rings.
642  *
643  * @adev: amdgpu device pointer
644  *
645  * Init the fence driver for all possible rings (all asics).
646  * Not all asics have all rings, so each asic will only
647  * start the fence driver on the rings it has using
648  * amdgpu_fence_driver_start_ring().
649  * Returns 0 for success.
650  */
651 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
652 {
653 	if (amdgpu_debugfs_fence_init(adev))
654 		dev_err(adev->dev, "fence debugfs file creation failed\n");
655 
656 	return 0;
657 }
658 
659 /**
660  * amdgpu_fence_driver_fini - tear down the fence driver
661  * for all possible rings.
662  *
663  * @adev: amdgpu device pointer
664  *
665  * Tear down the fence driver for all possible rings (all asics).
666  */
667 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
668 {
669 	int i, r;
670 
671 	mutex_lock(&adev->ring_lock);
672 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
673 		struct amdgpu_ring *ring = adev->rings[i];
674 		if (!ring || !ring->fence_drv.initialized)
675 			continue;
676 		r = amdgpu_fence_wait_empty(ring);
677 		if (r) {
678 			/* no need to trigger GPU reset as we are unloading */
679 			amdgpu_fence_driver_force_completion(adev);
680 		}
681 		wake_up_all(&ring->fence_drv.fence_queue);
682 		amdgpu_irq_put(adev, ring->fence_drv.irq_src,
683 			       ring->fence_drv.irq_type);
684 		if (ring->scheduler)
685 			amd_sched_destroy(ring->scheduler);
686 		ring->fence_drv.initialized = false;
687 	}
688 	mutex_unlock(&adev->ring_lock);
689 }
690 
691 /**
692  * amdgpu_fence_driver_suspend - suspend the fence driver
693  * for all possible rings.
694  *
695  * @adev: amdgpu device pointer
696  *
697  * Suspend the fence driver for all possible rings (all asics).
698  */
699 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
700 {
701 	int i, r;
702 
703 	mutex_lock(&adev->ring_lock);
704 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
705 		struct amdgpu_ring *ring = adev->rings[i];
706 		if (!ring || !ring->fence_drv.initialized)
707 			continue;
708 
709 		/* wait for gpu to finish processing current batch */
710 		r = amdgpu_fence_wait_empty(ring);
711 		if (r) {
712 			/* delay GPU reset to resume */
713 			amdgpu_fence_driver_force_completion(adev);
714 		}
715 
716 		/* disable the interrupt */
717 		amdgpu_irq_put(adev, ring->fence_drv.irq_src,
718 			       ring->fence_drv.irq_type);
719 	}
720 	mutex_unlock(&adev->ring_lock);
721 }
722 
723 /**
724  * amdgpu_fence_driver_resume - resume the fence driver
725  * for all possible rings.
726  *
727  * @adev: amdgpu device pointer
728  *
729  * Resume the fence driver for all possible rings (all asics).
730  * Not all asics have all rings, so each asic will only
731  * start the fence driver on the rings it has using
732  * amdgpu_fence_driver_start_ring().
733  * Returns 0 for success.
734  */
735 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
736 {
737 	int i;
738 
739 	mutex_lock(&adev->ring_lock);
740 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
741 		struct amdgpu_ring *ring = adev->rings[i];
742 		if (!ring || !ring->fence_drv.initialized)
743 			continue;
744 
745 		/* enable the interrupt */
746 		amdgpu_irq_get(adev, ring->fence_drv.irq_src,
747 			       ring->fence_drv.irq_type);
748 	}
749 	mutex_unlock(&adev->ring_lock);
750 }
751 
752 /**
753  * amdgpu_fence_driver_force_completion - force all fence waiter to complete
754  *
755  * @adev: amdgpu device pointer
756  *
757  * In case of GPU reset failure make sure no process keep waiting on fence
758  * that will never complete.
759  */
760 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
761 {
762 	int i;
763 
764 	for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
765 		struct amdgpu_ring *ring = adev->rings[i];
766 		if (!ring || !ring->fence_drv.initialized)
767 			continue;
768 
769 		amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
770 	}
771 }
772 
773 
774 /*
775  * Fence debugfs
776  */
777 #if defined(CONFIG_DEBUG_FS)
778 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
779 {
780 	struct drm_info_node *node = (struct drm_info_node *)m->private;
781 	struct drm_device *dev = node->minor->dev;
782 	struct amdgpu_device *adev = dev->dev_private;
783 	int i, j;
784 
785 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
786 		struct amdgpu_ring *ring = adev->rings[i];
787 		if (!ring || !ring->fence_drv.initialized)
788 			continue;
789 
790 		amdgpu_fence_process(ring);
791 
792 		seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
793 		seq_printf(m, "Last signaled fence 0x%016llx\n",
794 			   (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
795 		seq_printf(m, "Last emitted        0x%016llx\n",
796 			   ring->fence_drv.sync_seq[i]);
797 
798 		for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
799 			struct amdgpu_ring *other = adev->rings[j];
800 			if (i != j && other && other->fence_drv.initialized &&
801 			    ring->fence_drv.sync_seq[j])
802 				seq_printf(m, "Last sync to ring %d 0x%016llx\n",
803 					   j, ring->fence_drv.sync_seq[j]);
804 		}
805 	}
806 	return 0;
807 }
808 
809 static struct drm_info_list amdgpu_debugfs_fence_list[] = {
810 	{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
811 };
812 #endif
813 
814 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
815 {
816 #if defined(CONFIG_DEBUG_FS)
817 	return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1);
818 #else
819 	return 0;
820 #endif
821 }
822 
823 static const char *amdgpu_fence_get_driver_name(struct fence *fence)
824 {
825 	return "amdgpu";
826 }
827 
828 static const char *amdgpu_fence_get_timeline_name(struct fence *f)
829 {
830 	struct amdgpu_fence *fence = to_amdgpu_fence(f);
831 	return (const char *)fence->ring->name;
832 }
833 
834 static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence)
835 {
836 	return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
837 }
838 
839 static bool amdgpu_test_signaled_any(struct fence **fences, uint32_t count)
840 {
841 	int idx;
842 	struct fence *fence;
843 
844 	for (idx = 0; idx < count; ++idx) {
845 		fence = fences[idx];
846 		if (fence) {
847 			if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
848 				return true;
849 		}
850 	}
851 	return false;
852 }
853 
854 static bool amdgpu_test_signaled_all(struct fence **fences, uint32_t count)
855 {
856 	int idx;
857 	struct fence *fence;
858 
859 	for (idx = 0; idx < count; ++idx) {
860 		fence = fences[idx];
861 		if (fence) {
862 			if (!test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
863 				return false;
864 		}
865 	}
866 
867 	return true;
868 }
869 
870 struct amdgpu_wait_cb {
871 	struct fence_cb base;
872 	struct task_struct *task;
873 };
874 
875 static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
876 {
877 	struct amdgpu_wait_cb *wait =
878 		container_of(cb, struct amdgpu_wait_cb, base);
879 	wake_up_process(wait->task);
880 }
881 
882 static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
883 					     signed long t)
884 {
885 	struct amdgpu_fence *fence = to_amdgpu_fence(f);
886 	struct amdgpu_device *adev = fence->ring->adev;
887 
888 	return amdgpu_fence_wait_multiple(adev, &f, 1, false, intr, t);
889 }
890 
891 /**
892  * Wait the fence array with timeout
893  *
894  * @adev:     amdgpu device
895  * @array:    the fence array with amdgpu fence pointer
896  * @count:    the number of the fence array
897  * @wait_all: the flag of wait all(true) or wait any(false)
898  * @intr:     when sleep, set the current task interruptable or not
899  * @t:        timeout to wait
900  *
901  * If wait_all is true, it will return when all fences are signaled or timeout.
902  * If wait_all is false, it will return when any fence is signaled or timeout.
903  */
904 signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev,
905 				       struct fence **array,
906 				       uint32_t count,
907 				       bool wait_all,
908 				       bool intr,
909 				       signed long t)
910 {
911 	long idx = 0;
912 	struct amdgpu_wait_cb *cb;
913 	struct fence *fence;
914 
915 	BUG_ON(!array);
916 
917 	cb = kcalloc(count, sizeof(struct amdgpu_wait_cb), GFP_KERNEL);
918 	if (cb == NULL) {
919 		t = -ENOMEM;
920 		goto err_free_cb;
921 	}
922 
923 	for (idx = 0; idx < count; ++idx) {
924 		fence = array[idx];
925 		if (fence) {
926 			cb[idx].task = current;
927 			if (fence_add_callback(fence,
928 					&cb[idx].base, amdgpu_fence_wait_cb)) {
929 				/* The fence is already signaled */
930 				if (wait_all)
931 					continue;
932 				else
933 					goto fence_rm_cb;
934 			}
935 		}
936 	}
937 
938 	while (t > 0) {
939 		if (intr)
940 			set_current_state(TASK_INTERRUPTIBLE);
941 		else
942 			set_current_state(TASK_UNINTERRUPTIBLE);
943 
944 		/*
945 		 * amdgpu_test_signaled_any must be called after
946 		 * set_current_state to prevent a race with wake_up_process
947 		 */
948 		if (!wait_all && amdgpu_test_signaled_any(array, count))
949 			break;
950 		if (wait_all && amdgpu_test_signaled_all(array, count))
951 			break;
952 
953 		if (adev->needs_reset) {
954 			t = -EDEADLK;
955 			break;
956 		}
957 
958 		t = schedule_timeout(t);
959 
960 		if (t > 0 && intr && signal_pending(current))
961 			t = -ERESTARTSYS;
962 	}
963 
964 	__set_current_state(TASK_RUNNING);
965 
966 fence_rm_cb:
967 	for (idx = 0; idx < count; ++idx) {
968 		fence = array[idx];
969 		if (fence && cb[idx].base.func)
970 			fence_remove_callback(fence, &cb[idx].base);
971 	}
972 
973 err_free_cb:
974 	kfree(cb);
975 
976 	return t;
977 }
978 
979 const struct fence_ops amdgpu_fence_ops = {
980 	.get_driver_name = amdgpu_fence_get_driver_name,
981 	.get_timeline_name = amdgpu_fence_get_timeline_name,
982 	.enable_signaling = amdgpu_fence_enable_signaling,
983 	.signaled = amdgpu_fence_is_signaled,
984 	.wait = amdgpu_fence_default_wait,
985 	.release = NULL,
986 };
987