1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Dave Airlie 30 */ 31 #include <linux/seq_file.h> 32 #include <linux/atomic.h> 33 #include <linux/wait.h> 34 #include <linux/kref.h> 35 #include <linux/slab.h> 36 #include <linux/firmware.h> 37 #include <linux/pm_runtime.h> 38 39 #include <drm/drm_debugfs.h> 40 41 #include "amdgpu.h" 42 #include "amdgpu_trace.h" 43 44 /* 45 * Fences 46 * Fences mark an event in the GPUs pipeline and are used 47 * for GPU/CPU synchronization. When the fence is written, 48 * it is expected that all buffers associated with that fence 49 * are no longer in use by the associated ring on the GPU and 50 * that the the relevant GPU caches have been flushed. 51 */ 52 53 struct amdgpu_fence { 54 struct dma_fence base; 55 56 /* RB, DMA, etc. */ 57 struct amdgpu_ring *ring; 58 }; 59 60 static struct kmem_cache *amdgpu_fence_slab; 61 62 int amdgpu_fence_slab_init(void) 63 { 64 amdgpu_fence_slab = kmem_cache_create( 65 "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 66 SLAB_HWCACHE_ALIGN, NULL); 67 if (!amdgpu_fence_slab) 68 return -ENOMEM; 69 return 0; 70 } 71 72 void amdgpu_fence_slab_fini(void) 73 { 74 rcu_barrier(); 75 kmem_cache_destroy(amdgpu_fence_slab); 76 } 77 /* 78 * Cast helper 79 */ 80 static const struct dma_fence_ops amdgpu_fence_ops; 81 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 82 { 83 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 84 85 if (__f->base.ops == &amdgpu_fence_ops) 86 return __f; 87 88 return NULL; 89 } 90 91 /** 92 * amdgpu_fence_write - write a fence value 93 * 94 * @ring: ring the fence is associated with 95 * @seq: sequence number to write 96 * 97 * Writes a fence value to memory (all asics). 98 */ 99 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 100 { 101 struct amdgpu_fence_driver *drv = &ring->fence_drv; 102 103 if (drv->cpu_addr) 104 *drv->cpu_addr = cpu_to_le32(seq); 105 } 106 107 /** 108 * amdgpu_fence_read - read a fence value 109 * 110 * @ring: ring the fence is associated with 111 * 112 * Reads a fence value from memory (all asics). 113 * Returns the value of the fence read from memory. 114 */ 115 static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 116 { 117 struct amdgpu_fence_driver *drv = &ring->fence_drv; 118 u32 seq = 0; 119 120 if (drv->cpu_addr) 121 seq = le32_to_cpu(*drv->cpu_addr); 122 else 123 seq = atomic_read(&drv->last_seq); 124 125 return seq; 126 } 127 128 /** 129 * amdgpu_fence_emit - emit a fence on the requested ring 130 * 131 * @ring: ring the fence is associated with 132 * @f: resulting fence object 133 * @flags: flags to pass into the subordinate .emit_fence() call 134 * 135 * Emits a fence command on the requested ring (all asics). 136 * Returns 0 on success, -ENOMEM on failure. 137 */ 138 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 139 unsigned flags) 140 { 141 struct amdgpu_device *adev = ring->adev; 142 struct amdgpu_fence *fence; 143 struct dma_fence __rcu **ptr; 144 uint32_t seq; 145 int r; 146 147 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 148 if (fence == NULL) 149 return -ENOMEM; 150 151 seq = ++ring->fence_drv.sync_seq; 152 fence->ring = ring; 153 dma_fence_init(&fence->base, &amdgpu_fence_ops, 154 &ring->fence_drv.lock, 155 adev->fence_context + ring->idx, 156 seq); 157 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 158 seq, flags | AMDGPU_FENCE_FLAG_INT); 159 pm_runtime_get_noresume(adev_to_drm(adev)->dev); 160 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 161 if (unlikely(rcu_dereference_protected(*ptr, 1))) { 162 struct dma_fence *old; 163 164 rcu_read_lock(); 165 old = dma_fence_get_rcu_safe(ptr); 166 rcu_read_unlock(); 167 168 if (old) { 169 r = dma_fence_wait(old, false); 170 dma_fence_put(old); 171 if (r) 172 return r; 173 } 174 } 175 176 /* This function can't be called concurrently anyway, otherwise 177 * emitting the fence would mess up the hardware ring buffer. 178 */ 179 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 180 181 *f = &fence->base; 182 183 return 0; 184 } 185 186 /** 187 * amdgpu_fence_emit_polling - emit a fence on the requeste ring 188 * 189 * @ring: ring the fence is associated with 190 * @s: resulting sequence number 191 * @timeout: the timeout for waiting in usecs 192 * 193 * Emits a fence command on the requested ring (all asics). 194 * Used For polling fence. 195 * Returns 0 on success, -ENOMEM on failure. 196 */ 197 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 198 uint32_t timeout) 199 { 200 uint32_t seq; 201 signed long r; 202 203 if (!s) 204 return -EINVAL; 205 206 seq = ++ring->fence_drv.sync_seq; 207 r = amdgpu_fence_wait_polling(ring, 208 seq - ring->fence_drv.num_fences_mask, 209 timeout); 210 if (r < 1) 211 return -ETIMEDOUT; 212 213 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 214 seq, 0); 215 216 *s = seq; 217 218 return 0; 219 } 220 221 /** 222 * amdgpu_fence_schedule_fallback - schedule fallback check 223 * 224 * @ring: pointer to struct amdgpu_ring 225 * 226 * Start a timer as fallback to our interrupts. 227 */ 228 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 229 { 230 mod_timer(&ring->fence_drv.fallback_timer, 231 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 232 } 233 234 /** 235 * amdgpu_fence_process - check for fence activity 236 * 237 * @ring: pointer to struct amdgpu_ring 238 * 239 * Checks the current fence value and calculates the last 240 * signalled fence value. Wakes the fence queue if the 241 * sequence number has increased. 242 * 243 * Returns true if fence was processed 244 */ 245 bool amdgpu_fence_process(struct amdgpu_ring *ring) 246 { 247 struct amdgpu_fence_driver *drv = &ring->fence_drv; 248 struct amdgpu_device *adev = ring->adev; 249 uint32_t seq, last_seq; 250 int r; 251 252 do { 253 last_seq = atomic_read(&ring->fence_drv.last_seq); 254 seq = amdgpu_fence_read(ring); 255 256 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 257 258 if (del_timer(&ring->fence_drv.fallback_timer) && 259 seq != ring->fence_drv.sync_seq) 260 amdgpu_fence_schedule_fallback(ring); 261 262 if (unlikely(seq == last_seq)) 263 return false; 264 265 last_seq &= drv->num_fences_mask; 266 seq &= drv->num_fences_mask; 267 268 do { 269 struct dma_fence *fence, **ptr; 270 271 ++last_seq; 272 last_seq &= drv->num_fences_mask; 273 ptr = &drv->fences[last_seq]; 274 275 /* There is always exactly one thread signaling this fence slot */ 276 fence = rcu_dereference_protected(*ptr, 1); 277 RCU_INIT_POINTER(*ptr, NULL); 278 279 if (!fence) 280 continue; 281 282 r = dma_fence_signal(fence); 283 if (!r) 284 DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 285 else 286 BUG(); 287 288 dma_fence_put(fence); 289 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 290 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 291 } while (last_seq != seq); 292 293 return true; 294 } 295 296 /** 297 * amdgpu_fence_fallback - fallback for hardware interrupts 298 * 299 * @t: timer context used to obtain the pointer to ring structure 300 * 301 * Checks for fence activity. 302 */ 303 static void amdgpu_fence_fallback(struct timer_list *t) 304 { 305 struct amdgpu_ring *ring = from_timer(ring, t, 306 fence_drv.fallback_timer); 307 308 if (amdgpu_fence_process(ring)) 309 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); 310 } 311 312 /** 313 * amdgpu_fence_wait_empty - wait for all fences to signal 314 * 315 * @ring: ring index the fence is associated with 316 * 317 * Wait for all fences on the requested ring to signal (all asics). 318 * Returns 0 if the fences have passed, error for all other cases. 319 */ 320 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 321 { 322 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 323 struct dma_fence *fence, **ptr; 324 int r; 325 326 if (!seq) 327 return 0; 328 329 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 330 rcu_read_lock(); 331 fence = rcu_dereference(*ptr); 332 if (!fence || !dma_fence_get_rcu(fence)) { 333 rcu_read_unlock(); 334 return 0; 335 } 336 rcu_read_unlock(); 337 338 r = dma_fence_wait(fence, false); 339 dma_fence_put(fence); 340 return r; 341 } 342 343 /** 344 * amdgpu_fence_wait_polling - busy wait for givn sequence number 345 * 346 * @ring: ring index the fence is associated with 347 * @wait_seq: sequence number to wait 348 * @timeout: the timeout for waiting in usecs 349 * 350 * Wait for all fences on the requested ring to signal (all asics). 351 * Returns left time if no timeout, 0 or minus if timeout. 352 */ 353 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 354 uint32_t wait_seq, 355 signed long timeout) 356 { 357 uint32_t seq; 358 359 do { 360 seq = amdgpu_fence_read(ring); 361 udelay(5); 362 timeout -= 5; 363 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 364 365 return timeout > 0 ? timeout : 0; 366 } 367 /** 368 * amdgpu_fence_count_emitted - get the count of emitted fences 369 * 370 * @ring: ring the fence is associated with 371 * 372 * Get the number of fences emitted on the requested ring (all asics). 373 * Returns the number of emitted fences on the ring. Used by the 374 * dynpm code to ring track activity. 375 */ 376 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 377 { 378 uint64_t emitted; 379 380 /* We are not protected by ring lock when reading the last sequence 381 * but it's ok to report slightly wrong fence count here. 382 */ 383 amdgpu_fence_process(ring); 384 emitted = 0x100000000ull; 385 emitted -= atomic_read(&ring->fence_drv.last_seq); 386 emitted += READ_ONCE(ring->fence_drv.sync_seq); 387 return lower_32_bits(emitted); 388 } 389 390 /** 391 * amdgpu_fence_driver_start_ring - make the fence driver 392 * ready for use on the requested ring. 393 * 394 * @ring: ring to start the fence driver on 395 * @irq_src: interrupt source to use for this ring 396 * @irq_type: interrupt type to use for this ring 397 * 398 * Make the fence driver ready for processing (all asics). 399 * Not all asics have all rings, so each asic will only 400 * start the fence driver on the rings it has. 401 * Returns 0 for success, errors for failure. 402 */ 403 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 404 struct amdgpu_irq_src *irq_src, 405 unsigned irq_type) 406 { 407 struct amdgpu_device *adev = ring->adev; 408 uint64_t index; 409 410 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 411 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 412 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 413 } else { 414 /* put fence directly behind firmware */ 415 index = ALIGN(adev->uvd.fw->size, 8); 416 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 417 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 418 } 419 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 420 421 if (irq_src) 422 amdgpu_irq_get(adev, irq_src, irq_type); 423 424 ring->fence_drv.irq_src = irq_src; 425 ring->fence_drv.irq_type = irq_type; 426 ring->fence_drv.initialized = true; 427 428 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n", 429 ring->name, ring->fence_drv.gpu_addr); 430 return 0; 431 } 432 433 /** 434 * amdgpu_fence_driver_init_ring - init the fence driver 435 * for the requested ring. 436 * 437 * @ring: ring to init the fence driver on 438 * @num_hw_submission: number of entries on the hardware queue 439 * 440 * Init the fence driver for the requested ring (all asics). 441 * Helper function for amdgpu_fence_driver_init(). 442 */ 443 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 444 unsigned num_hw_submission) 445 { 446 struct amdgpu_device *adev = ring->adev; 447 long timeout; 448 int r; 449 450 if (!adev) 451 return -EINVAL; 452 453 if (!is_power_of_2(num_hw_submission)) 454 return -EINVAL; 455 456 ring->fence_drv.cpu_addr = NULL; 457 ring->fence_drv.gpu_addr = 0; 458 ring->fence_drv.sync_seq = 0; 459 atomic_set(&ring->fence_drv.last_seq, 0); 460 ring->fence_drv.initialized = false; 461 462 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 463 464 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 465 spin_lock_init(&ring->fence_drv.lock); 466 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 467 GFP_KERNEL); 468 if (!ring->fence_drv.fences) 469 return -ENOMEM; 470 471 /* No need to setup the GPU scheduler for rings that don't need it */ 472 if (!ring->no_scheduler) { 473 switch (ring->funcs->type) { 474 case AMDGPU_RING_TYPE_GFX: 475 timeout = adev->gfx_timeout; 476 break; 477 case AMDGPU_RING_TYPE_COMPUTE: 478 timeout = adev->compute_timeout; 479 break; 480 case AMDGPU_RING_TYPE_SDMA: 481 timeout = adev->sdma_timeout; 482 break; 483 default: 484 timeout = adev->video_timeout; 485 break; 486 } 487 488 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 489 num_hw_submission, amdgpu_job_hang_limit, 490 timeout, ring->name); 491 if (r) { 492 DRM_ERROR("Failed to create scheduler on ring %s.\n", 493 ring->name); 494 return r; 495 } 496 } 497 498 return 0; 499 } 500 501 /** 502 * amdgpu_fence_driver_init - init the fence driver 503 * for all possible rings. 504 * 505 * @adev: amdgpu device pointer 506 * 507 * Init the fence driver for all possible rings (all asics). 508 * Not all asics have all rings, so each asic will only 509 * start the fence driver on the rings it has using 510 * amdgpu_fence_driver_start_ring(). 511 * Returns 0 for success. 512 */ 513 int amdgpu_fence_driver_init(struct amdgpu_device *adev) 514 { 515 return 0; 516 } 517 518 /** 519 * amdgpu_fence_driver_fini - tear down the fence driver 520 * for all possible rings. 521 * 522 * @adev: amdgpu device pointer 523 * 524 * Tear down the fence driver for all possible rings (all asics). 525 */ 526 void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 527 { 528 unsigned i, j; 529 int r; 530 531 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 532 struct amdgpu_ring *ring = adev->rings[i]; 533 534 if (!ring || !ring->fence_drv.initialized) 535 continue; 536 r = amdgpu_fence_wait_empty(ring); 537 if (r) { 538 /* no need to trigger GPU reset as we are unloading */ 539 amdgpu_fence_driver_force_completion(ring); 540 } 541 if (ring->fence_drv.irq_src) 542 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 543 ring->fence_drv.irq_type); 544 if (!ring->no_scheduler) 545 drm_sched_fini(&ring->sched); 546 del_timer_sync(&ring->fence_drv.fallback_timer); 547 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 548 dma_fence_put(ring->fence_drv.fences[j]); 549 kfree(ring->fence_drv.fences); 550 ring->fence_drv.fences = NULL; 551 ring->fence_drv.initialized = false; 552 } 553 } 554 555 /** 556 * amdgpu_fence_driver_suspend - suspend the fence driver 557 * for all possible rings. 558 * 559 * @adev: amdgpu device pointer 560 * 561 * Suspend the fence driver for all possible rings (all asics). 562 */ 563 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 564 { 565 int i, r; 566 567 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 568 struct amdgpu_ring *ring = adev->rings[i]; 569 if (!ring || !ring->fence_drv.initialized) 570 continue; 571 572 /* wait for gpu to finish processing current batch */ 573 r = amdgpu_fence_wait_empty(ring); 574 if (r) { 575 /* delay GPU reset to resume */ 576 amdgpu_fence_driver_force_completion(ring); 577 } 578 579 /* disable the interrupt */ 580 if (ring->fence_drv.irq_src) 581 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 582 ring->fence_drv.irq_type); 583 } 584 } 585 586 /** 587 * amdgpu_fence_driver_resume - resume the fence driver 588 * for all possible rings. 589 * 590 * @adev: amdgpu device pointer 591 * 592 * Resume the fence driver for all possible rings (all asics). 593 * Not all asics have all rings, so each asic will only 594 * start the fence driver on the rings it has using 595 * amdgpu_fence_driver_start_ring(). 596 * Returns 0 for success. 597 */ 598 void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 599 { 600 int i; 601 602 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 603 struct amdgpu_ring *ring = adev->rings[i]; 604 if (!ring || !ring->fence_drv.initialized) 605 continue; 606 607 /* enable the interrupt */ 608 if (ring->fence_drv.irq_src) 609 amdgpu_irq_get(adev, ring->fence_drv.irq_src, 610 ring->fence_drv.irq_type); 611 } 612 } 613 614 /** 615 * amdgpu_fence_driver_force_completion - force signal latest fence of ring 616 * 617 * @ring: fence of the ring to signal 618 * 619 */ 620 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 621 { 622 amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 623 amdgpu_fence_process(ring); 624 } 625 626 /* 627 * Common fence implementation 628 */ 629 630 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 631 { 632 return "amdgpu"; 633 } 634 635 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 636 { 637 struct amdgpu_fence *fence = to_amdgpu_fence(f); 638 return (const char *)fence->ring->name; 639 } 640 641 /** 642 * amdgpu_fence_enable_signaling - enable signalling on fence 643 * @f: fence 644 * 645 * This function is called with fence_queue lock held, and adds a callback 646 * to fence_queue that checks if this fence is signaled, and if so it 647 * signals the fence and removes itself. 648 */ 649 static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 650 { 651 struct amdgpu_fence *fence = to_amdgpu_fence(f); 652 struct amdgpu_ring *ring = fence->ring; 653 654 if (!timer_pending(&ring->fence_drv.fallback_timer)) 655 amdgpu_fence_schedule_fallback(ring); 656 657 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 658 659 return true; 660 } 661 662 /** 663 * amdgpu_fence_free - free up the fence memory 664 * 665 * @rcu: RCU callback head 666 * 667 * Free up the fence memory after the RCU grace period. 668 */ 669 static void amdgpu_fence_free(struct rcu_head *rcu) 670 { 671 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 672 struct amdgpu_fence *fence = to_amdgpu_fence(f); 673 kmem_cache_free(amdgpu_fence_slab, fence); 674 } 675 676 /** 677 * amdgpu_fence_release - callback that fence can be freed 678 * 679 * @f: fence 680 * 681 * This function is called when the reference count becomes zero. 682 * It just RCU schedules freeing up the fence. 683 */ 684 static void amdgpu_fence_release(struct dma_fence *f) 685 { 686 call_rcu(&f->rcu, amdgpu_fence_free); 687 } 688 689 static const struct dma_fence_ops amdgpu_fence_ops = { 690 .get_driver_name = amdgpu_fence_get_driver_name, 691 .get_timeline_name = amdgpu_fence_get_timeline_name, 692 .enable_signaling = amdgpu_fence_enable_signaling, 693 .release = amdgpu_fence_release, 694 }; 695 696 /* 697 * Fence debugfs 698 */ 699 #if defined(CONFIG_DEBUG_FS) 700 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 701 { 702 struct drm_info_node *node = (struct drm_info_node *)m->private; 703 struct drm_device *dev = node->minor->dev; 704 struct amdgpu_device *adev = drm_to_adev(dev); 705 int i; 706 707 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 708 struct amdgpu_ring *ring = adev->rings[i]; 709 if (!ring || !ring->fence_drv.initialized) 710 continue; 711 712 amdgpu_fence_process(ring); 713 714 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 715 seq_printf(m, "Last signaled fence 0x%08x\n", 716 atomic_read(&ring->fence_drv.last_seq)); 717 seq_printf(m, "Last emitted 0x%08x\n", 718 ring->fence_drv.sync_seq); 719 720 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX || 721 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) { 722 seq_printf(m, "Last signaled trailing fence 0x%08x\n", 723 le32_to_cpu(*ring->trail_fence_cpu_addr)); 724 seq_printf(m, "Last emitted 0x%08x\n", 725 ring->trail_seq); 726 } 727 728 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 729 continue; 730 731 /* set in CP_VMID_PREEMPT and preemption occurred */ 732 seq_printf(m, "Last preempted 0x%08x\n", 733 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 734 /* set in CP_VMID_RESET and reset occurred */ 735 seq_printf(m, "Last reset 0x%08x\n", 736 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 737 /* Both preemption and reset occurred */ 738 seq_printf(m, "Last both 0x%08x\n", 739 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 740 } 741 return 0; 742 } 743 744 /* 745 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 746 * 747 * Manually trigger a gpu reset at the next fence wait. 748 */ 749 static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) 750 { 751 struct drm_info_node *node = (struct drm_info_node *) m->private; 752 struct drm_device *dev = node->minor->dev; 753 struct amdgpu_device *adev = drm_to_adev(dev); 754 int r; 755 756 r = pm_runtime_get_sync(dev->dev); 757 if (r < 0) { 758 pm_runtime_put_autosuspend(dev->dev); 759 return 0; 760 } 761 762 seq_printf(m, "gpu recover\n"); 763 amdgpu_device_gpu_recover(adev, NULL); 764 765 pm_runtime_mark_last_busy(dev->dev); 766 pm_runtime_put_autosuspend(dev->dev); 767 768 return 0; 769 } 770 771 static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 772 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 773 {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} 774 }; 775 776 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { 777 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 778 }; 779 #endif 780 781 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 782 { 783 #if defined(CONFIG_DEBUG_FS) 784 if (amdgpu_sriov_vf(adev)) 785 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 786 ARRAY_SIZE(amdgpu_debugfs_fence_list_sriov)); 787 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 788 ARRAY_SIZE(amdgpu_debugfs_fence_list)); 789 #else 790 return 0; 791 #endif 792 } 793 794