1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Dave Airlie 30 */ 31 #include <linux/seq_file.h> 32 #include <linux/atomic.h> 33 #include <linux/wait.h> 34 #include <linux/kref.h> 35 #include <linux/slab.h> 36 #include <linux/firmware.h> 37 #include <linux/pm_runtime.h> 38 39 #include <drm/drm_drv.h> 40 #include "amdgpu.h" 41 #include "amdgpu_trace.h" 42 43 /* 44 * Fences 45 * Fences mark an event in the GPUs pipeline and are used 46 * for GPU/CPU synchronization. When the fence is written, 47 * it is expected that all buffers associated with that fence 48 * are no longer in use by the associated ring on the GPU and 49 * that the the relevant GPU caches have been flushed. 50 */ 51 52 struct amdgpu_fence { 53 struct dma_fence base; 54 55 /* RB, DMA, etc. */ 56 struct amdgpu_ring *ring; 57 }; 58 59 static struct kmem_cache *amdgpu_fence_slab; 60 61 int amdgpu_fence_slab_init(void) 62 { 63 amdgpu_fence_slab = kmem_cache_create( 64 "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 65 SLAB_HWCACHE_ALIGN, NULL); 66 if (!amdgpu_fence_slab) 67 return -ENOMEM; 68 return 0; 69 } 70 71 void amdgpu_fence_slab_fini(void) 72 { 73 rcu_barrier(); 74 kmem_cache_destroy(amdgpu_fence_slab); 75 } 76 /* 77 * Cast helper 78 */ 79 static const struct dma_fence_ops amdgpu_fence_ops; 80 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 81 { 82 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 83 84 if (__f->base.ops == &amdgpu_fence_ops) 85 return __f; 86 87 return NULL; 88 } 89 90 /** 91 * amdgpu_fence_write - write a fence value 92 * 93 * @ring: ring the fence is associated with 94 * @seq: sequence number to write 95 * 96 * Writes a fence value to memory (all asics). 97 */ 98 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 99 { 100 struct amdgpu_fence_driver *drv = &ring->fence_drv; 101 102 if (drv->cpu_addr) 103 *drv->cpu_addr = cpu_to_le32(seq); 104 } 105 106 /** 107 * amdgpu_fence_read - read a fence value 108 * 109 * @ring: ring the fence is associated with 110 * 111 * Reads a fence value from memory (all asics). 112 * Returns the value of the fence read from memory. 113 */ 114 static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 115 { 116 struct amdgpu_fence_driver *drv = &ring->fence_drv; 117 u32 seq = 0; 118 119 if (drv->cpu_addr) 120 seq = le32_to_cpu(*drv->cpu_addr); 121 else 122 seq = atomic_read(&drv->last_seq); 123 124 return seq; 125 } 126 127 /** 128 * amdgpu_fence_emit - emit a fence on the requested ring 129 * 130 * @ring: ring the fence is associated with 131 * @f: resulting fence object 132 * @flags: flags to pass into the subordinate .emit_fence() call 133 * 134 * Emits a fence command on the requested ring (all asics). 135 * Returns 0 on success, -ENOMEM on failure. 136 */ 137 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 138 unsigned flags) 139 { 140 struct amdgpu_device *adev = ring->adev; 141 struct amdgpu_fence *fence; 142 struct dma_fence __rcu **ptr; 143 uint32_t seq; 144 int r; 145 146 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 147 if (fence == NULL) 148 return -ENOMEM; 149 150 seq = ++ring->fence_drv.sync_seq; 151 fence->ring = ring; 152 dma_fence_init(&fence->base, &amdgpu_fence_ops, 153 &ring->fence_drv.lock, 154 adev->fence_context + ring->idx, 155 seq); 156 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 157 seq, flags | AMDGPU_FENCE_FLAG_INT); 158 pm_runtime_get_noresume(adev_to_drm(adev)->dev); 159 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 160 if (unlikely(rcu_dereference_protected(*ptr, 1))) { 161 struct dma_fence *old; 162 163 rcu_read_lock(); 164 old = dma_fence_get_rcu_safe(ptr); 165 rcu_read_unlock(); 166 167 if (old) { 168 r = dma_fence_wait(old, false); 169 dma_fence_put(old); 170 if (r) 171 return r; 172 } 173 } 174 175 /* This function can't be called concurrently anyway, otherwise 176 * emitting the fence would mess up the hardware ring buffer. 177 */ 178 rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 179 180 *f = &fence->base; 181 182 return 0; 183 } 184 185 /** 186 * amdgpu_fence_emit_polling - emit a fence on the requeste ring 187 * 188 * @ring: ring the fence is associated with 189 * @s: resulting sequence number 190 * @timeout: the timeout for waiting in usecs 191 * 192 * Emits a fence command on the requested ring (all asics). 193 * Used For polling fence. 194 * Returns 0 on success, -ENOMEM on failure. 195 */ 196 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 197 uint32_t timeout) 198 { 199 uint32_t seq; 200 signed long r; 201 202 if (!s) 203 return -EINVAL; 204 205 seq = ++ring->fence_drv.sync_seq; 206 r = amdgpu_fence_wait_polling(ring, 207 seq - ring->fence_drv.num_fences_mask, 208 timeout); 209 if (r < 1) 210 return -ETIMEDOUT; 211 212 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 213 seq, 0); 214 215 *s = seq; 216 217 return 0; 218 } 219 220 /** 221 * amdgpu_fence_schedule_fallback - schedule fallback check 222 * 223 * @ring: pointer to struct amdgpu_ring 224 * 225 * Start a timer as fallback to our interrupts. 226 */ 227 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 228 { 229 mod_timer(&ring->fence_drv.fallback_timer, 230 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 231 } 232 233 /** 234 * amdgpu_fence_process - check for fence activity 235 * 236 * @ring: pointer to struct amdgpu_ring 237 * 238 * Checks the current fence value and calculates the last 239 * signalled fence value. Wakes the fence queue if the 240 * sequence number has increased. 241 * 242 * Returns true if fence was processed 243 */ 244 bool amdgpu_fence_process(struct amdgpu_ring *ring) 245 { 246 struct amdgpu_fence_driver *drv = &ring->fence_drv; 247 struct amdgpu_device *adev = ring->adev; 248 uint32_t seq, last_seq; 249 int r; 250 251 do { 252 last_seq = atomic_read(&ring->fence_drv.last_seq); 253 seq = amdgpu_fence_read(ring); 254 255 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 256 257 if (del_timer(&ring->fence_drv.fallback_timer) && 258 seq != ring->fence_drv.sync_seq) 259 amdgpu_fence_schedule_fallback(ring); 260 261 if (unlikely(seq == last_seq)) 262 return false; 263 264 last_seq &= drv->num_fences_mask; 265 seq &= drv->num_fences_mask; 266 267 do { 268 struct dma_fence *fence, **ptr; 269 270 ++last_seq; 271 last_seq &= drv->num_fences_mask; 272 ptr = &drv->fences[last_seq]; 273 274 /* There is always exactly one thread signaling this fence slot */ 275 fence = rcu_dereference_protected(*ptr, 1); 276 RCU_INIT_POINTER(*ptr, NULL); 277 278 if (!fence) 279 continue; 280 281 r = dma_fence_signal(fence); 282 if (!r) 283 DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 284 else 285 BUG(); 286 287 dma_fence_put(fence); 288 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 289 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 290 } while (last_seq != seq); 291 292 return true; 293 } 294 295 /** 296 * amdgpu_fence_fallback - fallback for hardware interrupts 297 * 298 * @t: timer context used to obtain the pointer to ring structure 299 * 300 * Checks for fence activity. 301 */ 302 static void amdgpu_fence_fallback(struct timer_list *t) 303 { 304 struct amdgpu_ring *ring = from_timer(ring, t, 305 fence_drv.fallback_timer); 306 307 if (amdgpu_fence_process(ring)) 308 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); 309 } 310 311 /** 312 * amdgpu_fence_wait_empty - wait for all fences to signal 313 * 314 * @ring: ring index the fence is associated with 315 * 316 * Wait for all fences on the requested ring to signal (all asics). 317 * Returns 0 if the fences have passed, error for all other cases. 318 */ 319 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 320 { 321 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 322 struct dma_fence *fence, **ptr; 323 int r; 324 325 if (!seq) 326 return 0; 327 328 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 329 rcu_read_lock(); 330 fence = rcu_dereference(*ptr); 331 if (!fence || !dma_fence_get_rcu(fence)) { 332 rcu_read_unlock(); 333 return 0; 334 } 335 rcu_read_unlock(); 336 337 r = dma_fence_wait(fence, false); 338 dma_fence_put(fence); 339 return r; 340 } 341 342 /** 343 * amdgpu_fence_wait_polling - busy wait for givn sequence number 344 * 345 * @ring: ring index the fence is associated with 346 * @wait_seq: sequence number to wait 347 * @timeout: the timeout for waiting in usecs 348 * 349 * Wait for all fences on the requested ring to signal (all asics). 350 * Returns left time if no timeout, 0 or minus if timeout. 351 */ 352 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 353 uint32_t wait_seq, 354 signed long timeout) 355 { 356 uint32_t seq; 357 358 do { 359 seq = amdgpu_fence_read(ring); 360 udelay(5); 361 timeout -= 5; 362 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 363 364 return timeout > 0 ? timeout : 0; 365 } 366 /** 367 * amdgpu_fence_count_emitted - get the count of emitted fences 368 * 369 * @ring: ring the fence is associated with 370 * 371 * Get the number of fences emitted on the requested ring (all asics). 372 * Returns the number of emitted fences on the ring. Used by the 373 * dynpm code to ring track activity. 374 */ 375 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 376 { 377 uint64_t emitted; 378 379 /* We are not protected by ring lock when reading the last sequence 380 * but it's ok to report slightly wrong fence count here. 381 */ 382 amdgpu_fence_process(ring); 383 emitted = 0x100000000ull; 384 emitted -= atomic_read(&ring->fence_drv.last_seq); 385 emitted += READ_ONCE(ring->fence_drv.sync_seq); 386 return lower_32_bits(emitted); 387 } 388 389 /** 390 * amdgpu_fence_driver_start_ring - make the fence driver 391 * ready for use on the requested ring. 392 * 393 * @ring: ring to start the fence driver on 394 * @irq_src: interrupt source to use for this ring 395 * @irq_type: interrupt type to use for this ring 396 * 397 * Make the fence driver ready for processing (all asics). 398 * Not all asics have all rings, so each asic will only 399 * start the fence driver on the rings it has. 400 * Returns 0 for success, errors for failure. 401 */ 402 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 403 struct amdgpu_irq_src *irq_src, 404 unsigned irq_type) 405 { 406 struct amdgpu_device *adev = ring->adev; 407 uint64_t index; 408 409 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 410 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 411 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 412 } else { 413 /* put fence directly behind firmware */ 414 index = ALIGN(adev->uvd.fw->size, 8); 415 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 416 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 417 } 418 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 419 420 if (irq_src) 421 amdgpu_irq_get(adev, irq_src, irq_type); 422 423 ring->fence_drv.irq_src = irq_src; 424 ring->fence_drv.irq_type = irq_type; 425 ring->fence_drv.initialized = true; 426 427 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n", 428 ring->name, ring->fence_drv.gpu_addr); 429 return 0; 430 } 431 432 /** 433 * amdgpu_fence_driver_init_ring - init the fence driver 434 * for the requested ring. 435 * 436 * @ring: ring to init the fence driver on 437 * @num_hw_submission: number of entries on the hardware queue 438 * @sched_score: optional score atomic shared with other schedulers 439 * 440 * Init the fence driver for the requested ring (all asics). 441 * Helper function for amdgpu_fence_driver_init(). 442 */ 443 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 444 unsigned num_hw_submission, 445 atomic_t *sched_score) 446 { 447 struct amdgpu_device *adev = ring->adev; 448 long timeout; 449 int r; 450 451 if (!adev) 452 return -EINVAL; 453 454 if (!is_power_of_2(num_hw_submission)) 455 return -EINVAL; 456 457 ring->fence_drv.cpu_addr = NULL; 458 ring->fence_drv.gpu_addr = 0; 459 ring->fence_drv.sync_seq = 0; 460 atomic_set(&ring->fence_drv.last_seq, 0); 461 ring->fence_drv.initialized = false; 462 463 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 464 465 ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 466 spin_lock_init(&ring->fence_drv.lock); 467 ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 468 GFP_KERNEL); 469 if (!ring->fence_drv.fences) 470 return -ENOMEM; 471 472 /* No need to setup the GPU scheduler for rings that don't need it */ 473 if (ring->no_scheduler) 474 return 0; 475 476 switch (ring->funcs->type) { 477 case AMDGPU_RING_TYPE_GFX: 478 timeout = adev->gfx_timeout; 479 break; 480 case AMDGPU_RING_TYPE_COMPUTE: 481 timeout = adev->compute_timeout; 482 break; 483 case AMDGPU_RING_TYPE_SDMA: 484 timeout = adev->sdma_timeout; 485 break; 486 default: 487 timeout = adev->video_timeout; 488 break; 489 } 490 491 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 492 num_hw_submission, amdgpu_job_hang_limit, 493 timeout, sched_score, ring->name); 494 if (r) { 495 DRM_ERROR("Failed to create scheduler on ring %s.\n", 496 ring->name); 497 return r; 498 } 499 500 return 0; 501 } 502 503 /** 504 * amdgpu_fence_driver_init - init the fence driver 505 * for all possible rings. 506 * 507 * @adev: amdgpu device pointer 508 * 509 * Init the fence driver for all possible rings (all asics). 510 * Not all asics have all rings, so each asic will only 511 * start the fence driver on the rings it has using 512 * amdgpu_fence_driver_start_ring(). 513 * Returns 0 for success. 514 */ 515 int amdgpu_fence_driver_init(struct amdgpu_device *adev) 516 { 517 return 0; 518 } 519 520 /** 521 * amdgpu_fence_driver_fini - tear down the fence driver 522 * for all possible rings. 523 * 524 * @adev: amdgpu device pointer 525 * 526 * Tear down the fence driver for all possible rings (all asics). 527 */ 528 void amdgpu_fence_driver_fini_hw(struct amdgpu_device *adev) 529 { 530 int i, r; 531 532 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 533 struct amdgpu_ring *ring = adev->rings[i]; 534 535 if (!ring || !ring->fence_drv.initialized) 536 continue; 537 if (!ring->no_scheduler) 538 drm_sched_fini(&ring->sched); 539 /* You can't wait for HW to signal if it's gone */ 540 if (!drm_dev_is_unplugged(&adev->ddev)) 541 r = amdgpu_fence_wait_empty(ring); 542 else 543 r = -ENODEV; 544 /* no need to trigger GPU reset as we are unloading */ 545 if (r) 546 amdgpu_fence_driver_force_completion(ring); 547 548 if (ring->fence_drv.irq_src) 549 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 550 ring->fence_drv.irq_type); 551 552 del_timer_sync(&ring->fence_drv.fallback_timer); 553 } 554 } 555 556 void amdgpu_fence_driver_fini_sw(struct amdgpu_device *adev) 557 { 558 unsigned int i, j; 559 560 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 561 struct amdgpu_ring *ring = adev->rings[i]; 562 563 if (!ring || !ring->fence_drv.initialized) 564 continue; 565 566 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 567 dma_fence_put(ring->fence_drv.fences[j]); 568 kfree(ring->fence_drv.fences); 569 ring->fence_drv.fences = NULL; 570 ring->fence_drv.initialized = false; 571 } 572 } 573 574 /** 575 * amdgpu_fence_driver_suspend - suspend the fence driver 576 * for all possible rings. 577 * 578 * @adev: amdgpu device pointer 579 * 580 * Suspend the fence driver for all possible rings (all asics). 581 */ 582 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 583 { 584 int i, r; 585 586 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 587 struct amdgpu_ring *ring = adev->rings[i]; 588 if (!ring || !ring->fence_drv.initialized) 589 continue; 590 591 /* wait for gpu to finish processing current batch */ 592 r = amdgpu_fence_wait_empty(ring); 593 if (r) { 594 /* delay GPU reset to resume */ 595 amdgpu_fence_driver_force_completion(ring); 596 } 597 598 /* disable the interrupt */ 599 if (ring->fence_drv.irq_src) 600 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 601 ring->fence_drv.irq_type); 602 } 603 } 604 605 /** 606 * amdgpu_fence_driver_resume - resume the fence driver 607 * for all possible rings. 608 * 609 * @adev: amdgpu device pointer 610 * 611 * Resume the fence driver for all possible rings (all asics). 612 * Not all asics have all rings, so each asic will only 613 * start the fence driver on the rings it has using 614 * amdgpu_fence_driver_start_ring(). 615 * Returns 0 for success. 616 */ 617 void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 618 { 619 int i; 620 621 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 622 struct amdgpu_ring *ring = adev->rings[i]; 623 if (!ring || !ring->fence_drv.initialized) 624 continue; 625 626 /* enable the interrupt */ 627 if (ring->fence_drv.irq_src) 628 amdgpu_irq_get(adev, ring->fence_drv.irq_src, 629 ring->fence_drv.irq_type); 630 } 631 } 632 633 /** 634 * amdgpu_fence_driver_force_completion - force signal latest fence of ring 635 * 636 * @ring: fence of the ring to signal 637 * 638 */ 639 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 640 { 641 amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 642 amdgpu_fence_process(ring); 643 } 644 645 /* 646 * Common fence implementation 647 */ 648 649 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 650 { 651 return "amdgpu"; 652 } 653 654 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 655 { 656 struct amdgpu_fence *fence = to_amdgpu_fence(f); 657 return (const char *)fence->ring->name; 658 } 659 660 /** 661 * amdgpu_fence_enable_signaling - enable signalling on fence 662 * @f: fence 663 * 664 * This function is called with fence_queue lock held, and adds a callback 665 * to fence_queue that checks if this fence is signaled, and if so it 666 * signals the fence and removes itself. 667 */ 668 static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 669 { 670 struct amdgpu_fence *fence = to_amdgpu_fence(f); 671 struct amdgpu_ring *ring = fence->ring; 672 673 if (!timer_pending(&ring->fence_drv.fallback_timer)) 674 amdgpu_fence_schedule_fallback(ring); 675 676 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 677 678 return true; 679 } 680 681 /** 682 * amdgpu_fence_free - free up the fence memory 683 * 684 * @rcu: RCU callback head 685 * 686 * Free up the fence memory after the RCU grace period. 687 */ 688 static void amdgpu_fence_free(struct rcu_head *rcu) 689 { 690 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 691 struct amdgpu_fence *fence = to_amdgpu_fence(f); 692 kmem_cache_free(amdgpu_fence_slab, fence); 693 } 694 695 /** 696 * amdgpu_fence_release - callback that fence can be freed 697 * 698 * @f: fence 699 * 700 * This function is called when the reference count becomes zero. 701 * It just RCU schedules freeing up the fence. 702 */ 703 static void amdgpu_fence_release(struct dma_fence *f) 704 { 705 call_rcu(&f->rcu, amdgpu_fence_free); 706 } 707 708 static const struct dma_fence_ops amdgpu_fence_ops = { 709 .get_driver_name = amdgpu_fence_get_driver_name, 710 .get_timeline_name = amdgpu_fence_get_timeline_name, 711 .enable_signaling = amdgpu_fence_enable_signaling, 712 .release = amdgpu_fence_release, 713 }; 714 715 /* 716 * Fence debugfs 717 */ 718 #if defined(CONFIG_DEBUG_FS) 719 static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused) 720 { 721 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 722 int i; 723 724 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 725 struct amdgpu_ring *ring = adev->rings[i]; 726 if (!ring || !ring->fence_drv.initialized) 727 continue; 728 729 amdgpu_fence_process(ring); 730 731 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 732 seq_printf(m, "Last signaled fence 0x%08x\n", 733 atomic_read(&ring->fence_drv.last_seq)); 734 seq_printf(m, "Last emitted 0x%08x\n", 735 ring->fence_drv.sync_seq); 736 737 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX || 738 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) { 739 seq_printf(m, "Last signaled trailing fence 0x%08x\n", 740 le32_to_cpu(*ring->trail_fence_cpu_addr)); 741 seq_printf(m, "Last emitted 0x%08x\n", 742 ring->trail_seq); 743 } 744 745 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 746 continue; 747 748 /* set in CP_VMID_PREEMPT and preemption occurred */ 749 seq_printf(m, "Last preempted 0x%08x\n", 750 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 751 /* set in CP_VMID_RESET and reset occurred */ 752 seq_printf(m, "Last reset 0x%08x\n", 753 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 754 /* Both preemption and reset occurred */ 755 seq_printf(m, "Last both 0x%08x\n", 756 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 757 } 758 return 0; 759 } 760 761 /* 762 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 763 * 764 * Manually trigger a gpu reset at the next fence wait. 765 */ 766 static int gpu_recover_get(void *data, u64 *val) 767 { 768 struct amdgpu_device *adev = (struct amdgpu_device *)data; 769 struct drm_device *dev = adev_to_drm(adev); 770 int r; 771 772 r = pm_runtime_get_sync(dev->dev); 773 if (r < 0) { 774 pm_runtime_put_autosuspend(dev->dev); 775 return 0; 776 } 777 778 *val = amdgpu_device_gpu_recover(adev, NULL); 779 780 pm_runtime_mark_last_busy(dev->dev); 781 pm_runtime_put_autosuspend(dev->dev); 782 783 return 0; 784 } 785 786 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); 787 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, 788 "%lld\n"); 789 790 #endif 791 792 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 793 { 794 #if defined(CONFIG_DEBUG_FS) 795 struct drm_minor *minor = adev_to_drm(adev)->primary; 796 struct dentry *root = minor->debugfs_root; 797 798 debugfs_create_file("amdgpu_fence_info", 0444, root, adev, 799 &amdgpu_debugfs_fence_info_fops); 800 801 if (!amdgpu_sriov_vf(adev)) 802 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev, 803 &amdgpu_debugfs_gpu_recover_fops); 804 #endif 805 } 806 807