1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 5022e5a2f4SChristian König struct amdgpu_fence { 51f54d1867SChris Wilson struct dma_fence base; 5222e5a2f4SChristian König 5322e5a2f4SChristian König /* RB, DMA, etc. */ 5422e5a2f4SChristian König struct amdgpu_ring *ring; 5522e5a2f4SChristian König }; 5622e5a2f4SChristian König 57b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 58b49c84a5SChunming Zhou 59d573de2dSRex Zhu int amdgpu_fence_slab_init(void) 60d573de2dSRex Zhu { 61d573de2dSRex Zhu amdgpu_fence_slab = kmem_cache_create( 62d573de2dSRex Zhu "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 63d573de2dSRex Zhu SLAB_HWCACHE_ALIGN, NULL); 64d573de2dSRex Zhu if (!amdgpu_fence_slab) 65d573de2dSRex Zhu return -ENOMEM; 66d573de2dSRex Zhu return 0; 67d573de2dSRex Zhu } 68d573de2dSRex Zhu 69d573de2dSRex Zhu void amdgpu_fence_slab_fini(void) 70d573de2dSRex Zhu { 71d573de2dSRex Zhu kmem_cache_destroy(amdgpu_fence_slab); 72d573de2dSRex Zhu } 7322e5a2f4SChristian König /* 7422e5a2f4SChristian König * Cast helper 7522e5a2f4SChristian König */ 76f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops; 77f54d1867SChris Wilson static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 7822e5a2f4SChristian König { 7922e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 8022e5a2f4SChristian König 8122e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 8222e5a2f4SChristian König return __f; 8322e5a2f4SChristian König 8422e5a2f4SChristian König return NULL; 8522e5a2f4SChristian König } 8622e5a2f4SChristian König 87d38ceaf9SAlex Deucher /** 88d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 89d38ceaf9SAlex Deucher * 90d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 91d38ceaf9SAlex Deucher * @seq: sequence number to write 92d38ceaf9SAlex Deucher * 93d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 94d38ceaf9SAlex Deucher */ 95d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 96d38ceaf9SAlex Deucher { 97d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 98d38ceaf9SAlex Deucher 99d38ceaf9SAlex Deucher if (drv->cpu_addr) 100d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 101d38ceaf9SAlex Deucher } 102d38ceaf9SAlex Deucher 103d38ceaf9SAlex Deucher /** 104d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 105d38ceaf9SAlex Deucher * 106d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 107d38ceaf9SAlex Deucher * 108d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 109d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 110d38ceaf9SAlex Deucher */ 111d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 112d38ceaf9SAlex Deucher { 113d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 114d38ceaf9SAlex Deucher u32 seq = 0; 115d38ceaf9SAlex Deucher 116d38ceaf9SAlex Deucher if (drv->cpu_addr) 117d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 118d38ceaf9SAlex Deucher else 119742c085fSChristian König seq = atomic_read(&drv->last_seq); 120d38ceaf9SAlex Deucher 121d38ceaf9SAlex Deucher return seq; 122d38ceaf9SAlex Deucher } 123d38ceaf9SAlex Deucher 124d38ceaf9SAlex Deucher /** 125d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 126d38ceaf9SAlex Deucher * 127d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 128364beb2cSChristian König * @f: resulting fence object 129d38ceaf9SAlex Deucher * 130d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 131d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 132d38ceaf9SAlex Deucher */ 133f54d1867SChris Wilson int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f) 134d38ceaf9SAlex Deucher { 135d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 136364beb2cSChristian König struct amdgpu_fence *fence; 137f54d1867SChris Wilson struct dma_fence *old, **ptr; 138742c085fSChristian König uint32_t seq; 139d38ceaf9SAlex Deucher 140364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 141364beb2cSChristian König if (fence == NULL) 142d38ceaf9SAlex Deucher return -ENOMEM; 143364beb2cSChristian König 144742c085fSChristian König seq = ++ring->fence_drv.sync_seq; 145364beb2cSChristian König fence->ring = ring; 146f54d1867SChris Wilson dma_fence_init(&fence->base, &amdgpu_fence_ops, 1474a7d74f1SChristian König &ring->fence_drv.lock, 1487f06c236Smonk.liu adev->fence_context + ring->idx, 149742c085fSChristian König seq); 150890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 151742c085fSChristian König seq, AMDGPU_FENCE_FLAG_INT); 152c89377d1SChristian König 153742c085fSChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 154c89377d1SChristian König /* This function can't be called concurrently anyway, otherwise 155c89377d1SChristian König * emitting the fence would mess up the hardware ring buffer. 156c89377d1SChristian König */ 157fc387a0bSChunming Zhou old = rcu_dereference_protected(*ptr, 1); 158f54d1867SChris Wilson if (old && !dma_fence_is_signaled(old)) { 159fc387a0bSChunming Zhou DRM_INFO("rcu slot is busy\n"); 160f54d1867SChris Wilson dma_fence_wait(old, false); 161fc387a0bSChunming Zhou } 162c89377d1SChristian König 163f54d1867SChris Wilson rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 164c89377d1SChristian König 165364beb2cSChristian König *f = &fence->base; 166c89377d1SChristian König 167d38ceaf9SAlex Deucher return 0; 168d38ceaf9SAlex Deucher } 169d38ceaf9SAlex Deucher 170d38ceaf9SAlex Deucher /** 171c2776afeSChristian König * amdgpu_fence_schedule_fallback - schedule fallback check 172c2776afeSChristian König * 173c2776afeSChristian König * @ring: pointer to struct amdgpu_ring 174c2776afeSChristian König * 175c2776afeSChristian König * Start a timer as fallback to our interrupts. 176c2776afeSChristian König */ 177c2776afeSChristian König static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 178c2776afeSChristian König { 179c2776afeSChristian König mod_timer(&ring->fence_drv.fallback_timer, 180c2776afeSChristian König jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 181c2776afeSChristian König } 182c2776afeSChristian König 183c2776afeSChristian König /** 184ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 185d38ceaf9SAlex Deucher * 186d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 187d38ceaf9SAlex Deucher * 188d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 189ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 190ca08e04dSChristian König * sequence number has increased. 191d38ceaf9SAlex Deucher */ 192ca08e04dSChristian König void amdgpu_fence_process(struct amdgpu_ring *ring) 193d38ceaf9SAlex Deucher { 1944a7d74f1SChristian König struct amdgpu_fence_driver *drv = &ring->fence_drv; 195742c085fSChristian König uint32_t seq, last_seq; 1964a7d74f1SChristian König int r; 197d38ceaf9SAlex Deucher 198d38ceaf9SAlex Deucher do { 199742c085fSChristian König last_seq = atomic_read(&ring->fence_drv.last_seq); 200d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 201d38ceaf9SAlex Deucher 202742c085fSChristian König } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 203d38ceaf9SAlex Deucher 204742c085fSChristian König if (seq != ring->fence_drv.sync_seq) 205c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 206d38ceaf9SAlex Deucher 2072ef004d9SChristian König if (unlikely(seq == last_seq)) 2082ef004d9SChristian König return; 2092ef004d9SChristian König 2104f399a08SChristian König last_seq &= drv->num_fences_mask; 2114f399a08SChristian König seq &= drv->num_fences_mask; 2124f399a08SChristian König 2132ef004d9SChristian König do { 214f54d1867SChris Wilson struct dma_fence *fence, **ptr; 2154a7d74f1SChristian König 2164f399a08SChristian König ++last_seq; 2174f399a08SChristian König last_seq &= drv->num_fences_mask; 2184f399a08SChristian König ptr = &drv->fences[last_seq]; 2194a7d74f1SChristian König 2204a7d74f1SChristian König /* There is always exactly one thread signaling this fence slot */ 2214a7d74f1SChristian König fence = rcu_dereference_protected(*ptr, 1); 22284fae133SMuhammad Falak R Wani RCU_INIT_POINTER(*ptr, NULL); 2234a7d74f1SChristian König 2244f399a08SChristian König if (!fence) 2254f399a08SChristian König continue; 2264a7d74f1SChristian König 227f54d1867SChris Wilson r = dma_fence_signal(fence); 2284a7d74f1SChristian König if (!r) 229f54d1867SChris Wilson DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 2304a7d74f1SChristian König else 2314a7d74f1SChristian König BUG(); 2324a7d74f1SChristian König 233f54d1867SChris Wilson dma_fence_put(fence); 2342ef004d9SChristian König } while (last_seq != seq); 235e0d8f3c3SChunming Zhou } 236d38ceaf9SAlex Deucher 237d38ceaf9SAlex Deucher /** 238c2776afeSChristian König * amdgpu_fence_fallback - fallback for hardware interrupts 239c2776afeSChristian König * 240c2776afeSChristian König * @work: delayed work item 241c2776afeSChristian König * 242c2776afeSChristian König * Checks for fence activity. 243c2776afeSChristian König */ 244c2776afeSChristian König static void amdgpu_fence_fallback(unsigned long arg) 245c2776afeSChristian König { 246c2776afeSChristian König struct amdgpu_ring *ring = (void *)arg; 247c2776afeSChristian König 248c2776afeSChristian König amdgpu_fence_process(ring); 249c2776afeSChristian König } 250c2776afeSChristian König 251c2776afeSChristian König /** 252d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 253d38ceaf9SAlex Deucher * 254d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 255d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 256d38ceaf9SAlex Deucher * 257d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 258d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 259d38ceaf9SAlex Deucher */ 260d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 261d38ceaf9SAlex Deucher { 262f09c2be4SChristian König uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq); 263f54d1867SChris Wilson struct dma_fence *fence, **ptr; 264f09c2be4SChristian König int r; 26500d2a2b2SChristian König 2667f06c236Smonk.liu if (!seq) 267d38ceaf9SAlex Deucher return 0; 268d38ceaf9SAlex Deucher 269f09c2be4SChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 270f09c2be4SChristian König rcu_read_lock(); 271f09c2be4SChristian König fence = rcu_dereference(*ptr); 272f54d1867SChris Wilson if (!fence || !dma_fence_get_rcu(fence)) { 273f09c2be4SChristian König rcu_read_unlock(); 274f09c2be4SChristian König return 0; 275f09c2be4SChristian König } 276f09c2be4SChristian König rcu_read_unlock(); 277f09c2be4SChristian König 278f54d1867SChris Wilson r = dma_fence_wait(fence, false); 279f54d1867SChris Wilson dma_fence_put(fence); 280f09c2be4SChristian König return r; 281d38ceaf9SAlex Deucher } 282d38ceaf9SAlex Deucher 283d38ceaf9SAlex Deucher /** 284d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 285d38ceaf9SAlex Deucher * 286d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 287d38ceaf9SAlex Deucher * 288d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 289d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 290d38ceaf9SAlex Deucher * dynpm code to ring track activity. 291d38ceaf9SAlex Deucher */ 292d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 293d38ceaf9SAlex Deucher { 294d38ceaf9SAlex Deucher uint64_t emitted; 295d38ceaf9SAlex Deucher 296d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 297d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 298d38ceaf9SAlex Deucher */ 299d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 300742c085fSChristian König emitted = 0x100000000ull; 301742c085fSChristian König emitted -= atomic_read(&ring->fence_drv.last_seq); 302742c085fSChristian König emitted += ACCESS_ONCE(ring->fence_drv.sync_seq); 303742c085fSChristian König return lower_32_bits(emitted); 304d38ceaf9SAlex Deucher } 305d38ceaf9SAlex Deucher 306d38ceaf9SAlex Deucher /** 307d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 308d38ceaf9SAlex Deucher * ready for use on the requested ring. 309d38ceaf9SAlex Deucher * 310d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 311d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 312d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 313d38ceaf9SAlex Deucher * 314d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 315d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 316d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 317d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 318d38ceaf9SAlex Deucher */ 319d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 320d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 321d38ceaf9SAlex Deucher unsigned irq_type) 322d38ceaf9SAlex Deucher { 323d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 324d38ceaf9SAlex Deucher uint64_t index; 325d38ceaf9SAlex Deucher 326d38ceaf9SAlex Deucher if (ring != &adev->uvd.ring) { 327d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 328d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 329d38ceaf9SAlex Deucher } else { 330d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 331d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 332d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; 333d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; 334d38ceaf9SAlex Deucher } 335742c085fSChristian König amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 336c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 337c6a4079bSChunming Zhou 338d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 339d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 340c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 341c6a4079bSChunming Zhou 342d38ceaf9SAlex Deucher dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " 343d38ceaf9SAlex Deucher "cpu addr 0x%p\n", ring->idx, 344d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 345d38ceaf9SAlex Deucher return 0; 346d38ceaf9SAlex Deucher } 347d38ceaf9SAlex Deucher 348d38ceaf9SAlex Deucher /** 349d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 350d38ceaf9SAlex Deucher * for the requested ring. 351d38ceaf9SAlex Deucher * 352d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 353e6151a08SChristian König * @num_hw_submission: number of entries on the hardware queue 354d38ceaf9SAlex Deucher * 355d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 356d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 357d38ceaf9SAlex Deucher */ 358e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 359e6151a08SChristian König unsigned num_hw_submission) 360d38ceaf9SAlex Deucher { 361cadf97b1SChunming Zhou long timeout; 3625907a0d8SChristian König int r; 363d38ceaf9SAlex Deucher 364e6151a08SChristian König /* Check that num_hw_submission is a power of two */ 365e6151a08SChristian König if ((num_hw_submission & (num_hw_submission - 1)) != 0) 366e6151a08SChristian König return -EINVAL; 367e6151a08SChristian König 368d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 369d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 3705907a0d8SChristian König ring->fence_drv.sync_seq = 0; 371742c085fSChristian König atomic_set(&ring->fence_drv.last_seq, 0); 372d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 373d38ceaf9SAlex Deucher 374c2776afeSChristian König setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 375c2776afeSChristian König (unsigned long)ring); 376b80d8475SAlex Deucher 37766067ad7SChunming Zhou ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 3784a7d74f1SChristian König spin_lock_init(&ring->fence_drv.lock); 37966067ad7SChunming Zhou ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 380c89377d1SChristian König GFP_KERNEL); 381c89377d1SChristian König if (!ring->fence_drv.fences) 382c89377d1SChristian König return -ENOMEM; 3835ec92a76SChristian König 384cadf97b1SChunming Zhou timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 3852440ff2cSJunwei Zhang if (timeout == 0) { 3862440ff2cSJunwei Zhang /* 3872440ff2cSJunwei Zhang * FIXME: 3882440ff2cSJunwei Zhang * Delayed workqueue cannot use it directly, 3892440ff2cSJunwei Zhang * so the scheduler will not use delayed workqueue if 3902440ff2cSJunwei Zhang * MAX_SCHEDULE_TIMEOUT is set. 3912440ff2cSJunwei Zhang * Currently keep it simple and silly. 3922440ff2cSJunwei Zhang */ 3932440ff2cSJunwei Zhang timeout = MAX_SCHEDULE_TIMEOUT; 3942440ff2cSJunwei Zhang } 3954f839a24SChristian König r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 396e6151a08SChristian König num_hw_submission, 3972440ff2cSJunwei Zhang timeout, ring->name); 3984f839a24SChristian König if (r) { 3994f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 4004f839a24SChristian König ring->name); 4014f839a24SChristian König return r; 402b80d8475SAlex Deucher } 403d38ceaf9SAlex Deucher 4044f839a24SChristian König return 0; 4054f839a24SChristian König } 4064f839a24SChristian König 407d38ceaf9SAlex Deucher /** 408d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 409d38ceaf9SAlex Deucher * for all possible rings. 410d38ceaf9SAlex Deucher * 411d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 412d38ceaf9SAlex Deucher * 413d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 414d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 415d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 416d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 417d38ceaf9SAlex Deucher * Returns 0 for success. 418d38ceaf9SAlex Deucher */ 419d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 420d38ceaf9SAlex Deucher { 421d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 422d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 423d38ceaf9SAlex Deucher 424d38ceaf9SAlex Deucher return 0; 425d38ceaf9SAlex Deucher } 426d38ceaf9SAlex Deucher 427d38ceaf9SAlex Deucher /** 428d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 429d38ceaf9SAlex Deucher * for all possible rings. 430d38ceaf9SAlex Deucher * 431d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 432d38ceaf9SAlex Deucher * 433d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 434d38ceaf9SAlex Deucher */ 435d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 436d38ceaf9SAlex Deucher { 437c89377d1SChristian König unsigned i, j; 438c89377d1SChristian König int r; 439d38ceaf9SAlex Deucher 440d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 441d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 442c2776afeSChristian König 443d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 444d38ceaf9SAlex Deucher continue; 445d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 446d38ceaf9SAlex Deucher if (r) { 447d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 448d38ceaf9SAlex Deucher amdgpu_fence_driver_force_completion(adev); 449d38ceaf9SAlex Deucher } 450c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 451c6a4079bSChunming Zhou ring->fence_drv.irq_type); 4524f839a24SChristian König amd_sched_fini(&ring->sched); 453c2776afeSChristian König del_timer_sync(&ring->fence_drv.fallback_timer); 454c89377d1SChristian König for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 455f54d1867SChris Wilson dma_fence_put(ring->fence_drv.fences[j]); 456c89377d1SChristian König kfree(ring->fence_drv.fences); 45754ddf3a6SGrazvydas Ignotas ring->fence_drv.fences = NULL; 458d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 459d38ceaf9SAlex Deucher } 460d38ceaf9SAlex Deucher } 461d38ceaf9SAlex Deucher 462d38ceaf9SAlex Deucher /** 4635ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 4645ceb54c6SAlex Deucher * for all possible rings. 4655ceb54c6SAlex Deucher * 4665ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4675ceb54c6SAlex Deucher * 4685ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 4695ceb54c6SAlex Deucher */ 4705ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 4715ceb54c6SAlex Deucher { 4725ceb54c6SAlex Deucher int i, r; 4735ceb54c6SAlex Deucher 4745ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 4755ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 4765ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 4775ceb54c6SAlex Deucher continue; 4785ceb54c6SAlex Deucher 4795ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 4805ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 4815ceb54c6SAlex Deucher if (r) { 4825ceb54c6SAlex Deucher /* delay GPU reset to resume */ 4835ceb54c6SAlex Deucher amdgpu_fence_driver_force_completion(adev); 4845ceb54c6SAlex Deucher } 4855ceb54c6SAlex Deucher 4865ceb54c6SAlex Deucher /* disable the interrupt */ 4875ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 4885ceb54c6SAlex Deucher ring->fence_drv.irq_type); 4895ceb54c6SAlex Deucher } 4905ceb54c6SAlex Deucher } 4915ceb54c6SAlex Deucher 4925ceb54c6SAlex Deucher /** 4935ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 4945ceb54c6SAlex Deucher * for all possible rings. 4955ceb54c6SAlex Deucher * 4965ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4975ceb54c6SAlex Deucher * 4985ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 4995ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 5005ceb54c6SAlex Deucher * start the fence driver on the rings it has using 5015ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 5025ceb54c6SAlex Deucher * Returns 0 for success. 5035ceb54c6SAlex Deucher */ 5045ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 5055ceb54c6SAlex Deucher { 5065ceb54c6SAlex Deucher int i; 5075ceb54c6SAlex Deucher 5085ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5095ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5105ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5115ceb54c6SAlex Deucher continue; 5125ceb54c6SAlex Deucher 5135ceb54c6SAlex Deucher /* enable the interrupt */ 5145ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 5155ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5165ceb54c6SAlex Deucher } 5175ceb54c6SAlex Deucher } 5185ceb54c6SAlex Deucher 5195ceb54c6SAlex Deucher /** 520d38ceaf9SAlex Deucher * amdgpu_fence_driver_force_completion - force all fence waiter to complete 521d38ceaf9SAlex Deucher * 522d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 523d38ceaf9SAlex Deucher * 524d38ceaf9SAlex Deucher * In case of GPU reset failure make sure no process keep waiting on fence 525d38ceaf9SAlex Deucher * that will never complete. 526d38ceaf9SAlex Deucher */ 527d38ceaf9SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) 528d38ceaf9SAlex Deucher { 529d38ceaf9SAlex Deucher int i; 530d38ceaf9SAlex Deucher 531d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 532d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 533d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 534d38ceaf9SAlex Deucher continue; 535d38ceaf9SAlex Deucher 5365907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 537d38ceaf9SAlex Deucher } 538d38ceaf9SAlex Deucher } 539d38ceaf9SAlex Deucher 540a95e2642SChristian König /* 541a95e2642SChristian König * Common fence implementation 542a95e2642SChristian König */ 543a95e2642SChristian König 544f54d1867SChris Wilson static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 545a95e2642SChristian König { 546a95e2642SChristian König return "amdgpu"; 547a95e2642SChristian König } 548a95e2642SChristian König 549f54d1867SChris Wilson static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 550a95e2642SChristian König { 551a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 552a95e2642SChristian König return (const char *)fence->ring->name; 553a95e2642SChristian König } 554a95e2642SChristian König 555a95e2642SChristian König /** 556a95e2642SChristian König * amdgpu_fence_enable_signaling - enable signalling on fence 557a95e2642SChristian König * @fence: fence 558a95e2642SChristian König * 559a95e2642SChristian König * This function is called with fence_queue lock held, and adds a callback 560a95e2642SChristian König * to fence_queue that checks if this fence is signaled, and if so it 561a95e2642SChristian König * signals the fence and removes itself. 562a95e2642SChristian König */ 563f54d1867SChris Wilson static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 564a95e2642SChristian König { 565a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 566a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 567a95e2642SChristian König 568c2776afeSChristian König if (!timer_pending(&ring->fence_drv.fallback_timer)) 569c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 5704a7d74f1SChristian König 571f54d1867SChris Wilson DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 5724a7d74f1SChristian König 573a95e2642SChristian König return true; 574a95e2642SChristian König } 575a95e2642SChristian König 576b4413535SChristian König /** 577b4413535SChristian König * amdgpu_fence_free - free up the fence memory 578b4413535SChristian König * 579b4413535SChristian König * @rcu: RCU callback head 580b4413535SChristian König * 581b4413535SChristian König * Free up the fence memory after the RCU grace period. 582b4413535SChristian König */ 583b4413535SChristian König static void amdgpu_fence_free(struct rcu_head *rcu) 584b49c84a5SChunming Zhou { 585f54d1867SChris Wilson struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 586b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 587b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 588b49c84a5SChunming Zhou } 589b49c84a5SChunming Zhou 590b4413535SChristian König /** 591b4413535SChristian König * amdgpu_fence_release - callback that fence can be freed 592b4413535SChristian König * 593b4413535SChristian König * @fence: fence 594b4413535SChristian König * 595b4413535SChristian König * This function is called when the reference count becomes zero. 596b4413535SChristian König * It just RCU schedules freeing up the fence. 597b4413535SChristian König */ 598f54d1867SChris Wilson static void amdgpu_fence_release(struct dma_fence *f) 599b4413535SChristian König { 600b4413535SChristian König call_rcu(&f->rcu, amdgpu_fence_free); 601b4413535SChristian König } 602b4413535SChristian König 603f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops = { 604a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 605a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 606a95e2642SChristian König .enable_signaling = amdgpu_fence_enable_signaling, 607f54d1867SChris Wilson .wait = dma_fence_default_wait, 608b49c84a5SChunming Zhou .release = amdgpu_fence_release, 609a95e2642SChristian König }; 610d38ceaf9SAlex Deucher 611d38ceaf9SAlex Deucher /* 612d38ceaf9SAlex Deucher * Fence debugfs 613d38ceaf9SAlex Deucher */ 614d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 615d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 616d38ceaf9SAlex Deucher { 617d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 618d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 619d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 6205907a0d8SChristian König int i; 621d38ceaf9SAlex Deucher 622d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 623d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 624d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 625d38ceaf9SAlex Deucher continue; 626d38ceaf9SAlex Deucher 627d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 628d38ceaf9SAlex Deucher 629344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 630742c085fSChristian König seq_printf(m, "Last signaled fence 0x%08x\n", 631742c085fSChristian König atomic_read(&ring->fence_drv.last_seq)); 632742c085fSChristian König seq_printf(m, "Last emitted 0x%08x\n", 6335907a0d8SChristian König ring->fence_drv.sync_seq); 634d38ceaf9SAlex Deucher } 635d38ceaf9SAlex Deucher return 0; 636d38ceaf9SAlex Deucher } 637d38ceaf9SAlex Deucher 63818db89b4SAlex Deucher /** 63918db89b4SAlex Deucher * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset 64018db89b4SAlex Deucher * 64118db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 64218db89b4SAlex Deucher */ 64318db89b4SAlex Deucher static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) 64418db89b4SAlex Deucher { 64518db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 64618db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 64718db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 64818db89b4SAlex Deucher 64918db89b4SAlex Deucher seq_printf(m, "gpu reset\n"); 65018db89b4SAlex Deucher amdgpu_gpu_reset(adev); 65118db89b4SAlex Deucher 65218db89b4SAlex Deucher return 0; 65318db89b4SAlex Deucher } 65418db89b4SAlex Deucher 65506ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 656d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 65718db89b4SAlex Deucher {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} 658d38ceaf9SAlex Deucher }; 659d38ceaf9SAlex Deucher #endif 660d38ceaf9SAlex Deucher 661d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 662d38ceaf9SAlex Deucher { 663d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 66418db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 665d38ceaf9SAlex Deucher #else 666d38ceaf9SAlex Deucher return 0; 667d38ceaf9SAlex Deucher #endif 668d38ceaf9SAlex Deucher } 669d38ceaf9SAlex Deucher 670