1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 5022e5a2f4SChristian König struct amdgpu_fence { 51f54d1867SChris Wilson struct dma_fence base; 5222e5a2f4SChristian König 5322e5a2f4SChristian König /* RB, DMA, etc. */ 5422e5a2f4SChristian König struct amdgpu_ring *ring; 5522e5a2f4SChristian König }; 5622e5a2f4SChristian König 57b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 58b49c84a5SChunming Zhou 59d573de2dSRex Zhu int amdgpu_fence_slab_init(void) 60d573de2dSRex Zhu { 61d573de2dSRex Zhu amdgpu_fence_slab = kmem_cache_create( 62d573de2dSRex Zhu "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 63d573de2dSRex Zhu SLAB_HWCACHE_ALIGN, NULL); 64d573de2dSRex Zhu if (!amdgpu_fence_slab) 65d573de2dSRex Zhu return -ENOMEM; 66d573de2dSRex Zhu return 0; 67d573de2dSRex Zhu } 68d573de2dSRex Zhu 69d573de2dSRex Zhu void amdgpu_fence_slab_fini(void) 70d573de2dSRex Zhu { 710f10425eSGrazvydas Ignotas rcu_barrier(); 72d573de2dSRex Zhu kmem_cache_destroy(amdgpu_fence_slab); 73d573de2dSRex Zhu } 7422e5a2f4SChristian König /* 7522e5a2f4SChristian König * Cast helper 7622e5a2f4SChristian König */ 77f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops; 78f54d1867SChris Wilson static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 7922e5a2f4SChristian König { 8022e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 8122e5a2f4SChristian König 8222e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 8322e5a2f4SChristian König return __f; 8422e5a2f4SChristian König 8522e5a2f4SChristian König return NULL; 8622e5a2f4SChristian König } 8722e5a2f4SChristian König 88d38ceaf9SAlex Deucher /** 89d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 90d38ceaf9SAlex Deucher * 91d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 92d38ceaf9SAlex Deucher * @seq: sequence number to write 93d38ceaf9SAlex Deucher * 94d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 95d38ceaf9SAlex Deucher */ 96d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 97d38ceaf9SAlex Deucher { 98d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher if (drv->cpu_addr) 101d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 102d38ceaf9SAlex Deucher } 103d38ceaf9SAlex Deucher 104d38ceaf9SAlex Deucher /** 105d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 106d38ceaf9SAlex Deucher * 107d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 108d38ceaf9SAlex Deucher * 109d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 110d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 111d38ceaf9SAlex Deucher */ 112d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 113d38ceaf9SAlex Deucher { 114d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 115d38ceaf9SAlex Deucher u32 seq = 0; 116d38ceaf9SAlex Deucher 117d38ceaf9SAlex Deucher if (drv->cpu_addr) 118d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 119d38ceaf9SAlex Deucher else 120742c085fSChristian König seq = atomic_read(&drv->last_seq); 121d38ceaf9SAlex Deucher 122d38ceaf9SAlex Deucher return seq; 123d38ceaf9SAlex Deucher } 124d38ceaf9SAlex Deucher 125d38ceaf9SAlex Deucher /** 126d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 127d38ceaf9SAlex Deucher * 128d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 129364beb2cSChristian König * @f: resulting fence object 130d38ceaf9SAlex Deucher * 131d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 132d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 133d38ceaf9SAlex Deucher */ 134d240cd9eSMarek Olšák int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 135d240cd9eSMarek Olšák unsigned flags) 136d38ceaf9SAlex Deucher { 137d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 138364beb2cSChristian König struct amdgpu_fence *fence; 1393d2aca8cSChristian König struct dma_fence __rcu **ptr; 140742c085fSChristian König uint32_t seq; 1413d2aca8cSChristian König int r; 142d38ceaf9SAlex Deucher 143364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 144364beb2cSChristian König if (fence == NULL) 145d38ceaf9SAlex Deucher return -ENOMEM; 146364beb2cSChristian König 147742c085fSChristian König seq = ++ring->fence_drv.sync_seq; 148364beb2cSChristian König fence->ring = ring; 149f54d1867SChris Wilson dma_fence_init(&fence->base, &amdgpu_fence_ops, 1504a7d74f1SChristian König &ring->fence_drv.lock, 1517f06c236Smonk.liu adev->fence_context + ring->idx, 152742c085fSChristian König seq); 153890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 154d240cd9eSMarek Olšák seq, flags | AMDGPU_FENCE_FLAG_INT); 155c89377d1SChristian König 156742c085fSChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 1573d2aca8cSChristian König if (unlikely(rcu_dereference_protected(*ptr, 1))) { 1583d2aca8cSChristian König struct dma_fence *old; 1593d2aca8cSChristian König 1603d2aca8cSChristian König rcu_read_lock(); 1613d2aca8cSChristian König old = dma_fence_get_rcu_safe(ptr); 1623d2aca8cSChristian König rcu_read_unlock(); 1633d2aca8cSChristian König 1643d2aca8cSChristian König if (old) { 1653d2aca8cSChristian König r = dma_fence_wait(old, false); 1663d2aca8cSChristian König dma_fence_put(old); 1673d2aca8cSChristian König if (r) 1683d2aca8cSChristian König return r; 1693d2aca8cSChristian König } 1703d2aca8cSChristian König } 1713d2aca8cSChristian König 172c89377d1SChristian König /* This function can't be called concurrently anyway, otherwise 173c89377d1SChristian König * emitting the fence would mess up the hardware ring buffer. 174c89377d1SChristian König */ 175f54d1867SChris Wilson rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 176c89377d1SChristian König 177364beb2cSChristian König *f = &fence->base; 178c89377d1SChristian König 179d38ceaf9SAlex Deucher return 0; 180d38ceaf9SAlex Deucher } 181d38ceaf9SAlex Deucher 182d38ceaf9SAlex Deucher /** 18343ca8efaSpding * amdgpu_fence_emit_polling - emit a fence on the requeste ring 18443ca8efaSpding * 18543ca8efaSpding * @ring: ring the fence is associated with 18643ca8efaSpding * @s: resulting sequence number 18743ca8efaSpding * 18843ca8efaSpding * Emits a fence command on the requested ring (all asics). 18943ca8efaSpding * Used For polling fence. 19043ca8efaSpding * Returns 0 on success, -ENOMEM on failure. 19143ca8efaSpding */ 19243ca8efaSpding int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) 19343ca8efaSpding { 19443ca8efaSpding uint32_t seq; 19543ca8efaSpding 19643ca8efaSpding if (!s) 19743ca8efaSpding return -EINVAL; 19843ca8efaSpding 19943ca8efaSpding seq = ++ring->fence_drv.sync_seq; 20043ca8efaSpding amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 201d118a621SMonk Liu seq, 0); 20243ca8efaSpding 20343ca8efaSpding *s = seq; 20443ca8efaSpding 20543ca8efaSpding return 0; 20643ca8efaSpding } 20743ca8efaSpding 20843ca8efaSpding /** 2098c5e13ecSAndrey Grodzovsky * amdgpu_fence_schedule_fallback - schedule fallback check 2108c5e13ecSAndrey Grodzovsky * 2118c5e13ecSAndrey Grodzovsky * @ring: pointer to struct amdgpu_ring 2128c5e13ecSAndrey Grodzovsky * 2138c5e13ecSAndrey Grodzovsky * Start a timer as fallback to our interrupts. 2148c5e13ecSAndrey Grodzovsky */ 2158c5e13ecSAndrey Grodzovsky static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 2168c5e13ecSAndrey Grodzovsky { 2178c5e13ecSAndrey Grodzovsky mod_timer(&ring->fence_drv.fallback_timer, 2188c5e13ecSAndrey Grodzovsky jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 2198c5e13ecSAndrey Grodzovsky } 2208c5e13ecSAndrey Grodzovsky 2218c5e13ecSAndrey Grodzovsky /** 222ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 223d38ceaf9SAlex Deucher * 224d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 225d38ceaf9SAlex Deucher * 226d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 227ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 228ca08e04dSChristian König * sequence number has increased. 22995d7fc4aSAndrey Grodzovsky * 23095d7fc4aSAndrey Grodzovsky * Returns true if fence was processed 231d38ceaf9SAlex Deucher */ 23295d7fc4aSAndrey Grodzovsky bool amdgpu_fence_process(struct amdgpu_ring *ring) 233d38ceaf9SAlex Deucher { 2344a7d74f1SChristian König struct amdgpu_fence_driver *drv = &ring->fence_drv; 235742c085fSChristian König uint32_t seq, last_seq; 2364a7d74f1SChristian König int r; 237d38ceaf9SAlex Deucher 238d38ceaf9SAlex Deucher do { 239742c085fSChristian König last_seq = atomic_read(&ring->fence_drv.last_seq); 240d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 241d38ceaf9SAlex Deucher 242742c085fSChristian König } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 243d38ceaf9SAlex Deucher 2443547e3cfSAndrey Grodzovsky if (del_timer(&ring->fence_drv.fallback_timer) && 2453547e3cfSAndrey Grodzovsky seq != ring->fence_drv.sync_seq) 2468c5e13ecSAndrey Grodzovsky amdgpu_fence_schedule_fallback(ring); 2478c5e13ecSAndrey Grodzovsky 2482ef004d9SChristian König if (unlikely(seq == last_seq)) 24995d7fc4aSAndrey Grodzovsky return false; 2502ef004d9SChristian König 2514f399a08SChristian König last_seq &= drv->num_fences_mask; 2524f399a08SChristian König seq &= drv->num_fences_mask; 2534f399a08SChristian König 2542ef004d9SChristian König do { 255f54d1867SChris Wilson struct dma_fence *fence, **ptr; 2564a7d74f1SChristian König 2574f399a08SChristian König ++last_seq; 2584f399a08SChristian König last_seq &= drv->num_fences_mask; 2594f399a08SChristian König ptr = &drv->fences[last_seq]; 2604a7d74f1SChristian König 2614a7d74f1SChristian König /* There is always exactly one thread signaling this fence slot */ 2624a7d74f1SChristian König fence = rcu_dereference_protected(*ptr, 1); 26384fae133SMuhammad Falak R Wani RCU_INIT_POINTER(*ptr, NULL); 2644a7d74f1SChristian König 2654f399a08SChristian König if (!fence) 2664f399a08SChristian König continue; 2674a7d74f1SChristian König 268f54d1867SChris Wilson r = dma_fence_signal(fence); 2694a7d74f1SChristian König if (!r) 270f54d1867SChris Wilson DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 2714a7d74f1SChristian König else 2724a7d74f1SChristian König BUG(); 2734a7d74f1SChristian König 274f54d1867SChris Wilson dma_fence_put(fence); 2752ef004d9SChristian König } while (last_seq != seq); 27695d7fc4aSAndrey Grodzovsky 27795d7fc4aSAndrey Grodzovsky return true; 278e0d8f3c3SChunming Zhou } 279d38ceaf9SAlex Deucher 280d38ceaf9SAlex Deucher /** 2818c5e13ecSAndrey Grodzovsky * amdgpu_fence_fallback - fallback for hardware interrupts 2828c5e13ecSAndrey Grodzovsky * 2838c5e13ecSAndrey Grodzovsky * @work: delayed work item 2848c5e13ecSAndrey Grodzovsky * 2858c5e13ecSAndrey Grodzovsky * Checks for fence activity. 2868c5e13ecSAndrey Grodzovsky */ 2878c5e13ecSAndrey Grodzovsky static void amdgpu_fence_fallback(struct timer_list *t) 2888c5e13ecSAndrey Grodzovsky { 2898c5e13ecSAndrey Grodzovsky struct amdgpu_ring *ring = from_timer(ring, t, 2908c5e13ecSAndrey Grodzovsky fence_drv.fallback_timer); 2918c5e13ecSAndrey Grodzovsky 29295d7fc4aSAndrey Grodzovsky if (amdgpu_fence_process(ring)) 2933547e3cfSAndrey Grodzovsky DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); 2948c5e13ecSAndrey Grodzovsky } 2958c5e13ecSAndrey Grodzovsky 2968c5e13ecSAndrey Grodzovsky /** 297d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 298d38ceaf9SAlex Deucher * 299d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 300d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 301d38ceaf9SAlex Deucher * 302d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 303d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 304d38ceaf9SAlex Deucher */ 305d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 306d38ceaf9SAlex Deucher { 3076aa7de05SMark Rutland uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 308f54d1867SChris Wilson struct dma_fence *fence, **ptr; 309f09c2be4SChristian König int r; 31000d2a2b2SChristian König 3117f06c236Smonk.liu if (!seq) 312d38ceaf9SAlex Deucher return 0; 313d38ceaf9SAlex Deucher 314f09c2be4SChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 315f09c2be4SChristian König rcu_read_lock(); 316f09c2be4SChristian König fence = rcu_dereference(*ptr); 317f54d1867SChris Wilson if (!fence || !dma_fence_get_rcu(fence)) { 318f09c2be4SChristian König rcu_read_unlock(); 319f09c2be4SChristian König return 0; 320f09c2be4SChristian König } 321f09c2be4SChristian König rcu_read_unlock(); 322f09c2be4SChristian König 323f54d1867SChris Wilson r = dma_fence_wait(fence, false); 324f54d1867SChris Wilson dma_fence_put(fence); 325f09c2be4SChristian König return r; 326d38ceaf9SAlex Deucher } 327d38ceaf9SAlex Deucher 328d38ceaf9SAlex Deucher /** 32943ca8efaSpding * amdgpu_fence_wait_polling - busy wait for givn sequence number 33043ca8efaSpding * 33143ca8efaSpding * @ring: ring index the fence is associated with 33243ca8efaSpding * @wait_seq: sequence number to wait 33343ca8efaSpding * @timeout: the timeout for waiting in usecs 33443ca8efaSpding * 33543ca8efaSpding * Wait for all fences on the requested ring to signal (all asics). 33643ca8efaSpding * Returns left time if no timeout, 0 or minus if timeout. 33743ca8efaSpding */ 33843ca8efaSpding signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 33943ca8efaSpding uint32_t wait_seq, 34043ca8efaSpding signed long timeout) 34143ca8efaSpding { 34243ca8efaSpding uint32_t seq; 34343ca8efaSpding 34443ca8efaSpding do { 34543ca8efaSpding seq = amdgpu_fence_read(ring); 34643ca8efaSpding udelay(5); 34743ca8efaSpding timeout -= 5; 34843ca8efaSpding } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 34943ca8efaSpding 35043ca8efaSpding return timeout > 0 ? timeout : 0; 35143ca8efaSpding } 35243ca8efaSpding /** 353d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 354d38ceaf9SAlex Deucher * 355d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 356d38ceaf9SAlex Deucher * 357d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 358d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 359d38ceaf9SAlex Deucher * dynpm code to ring track activity. 360d38ceaf9SAlex Deucher */ 361d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 362d38ceaf9SAlex Deucher { 363d38ceaf9SAlex Deucher uint64_t emitted; 364d38ceaf9SAlex Deucher 365d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 366d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 367d38ceaf9SAlex Deucher */ 368d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 369742c085fSChristian König emitted = 0x100000000ull; 370742c085fSChristian König emitted -= atomic_read(&ring->fence_drv.last_seq); 3716aa7de05SMark Rutland emitted += READ_ONCE(ring->fence_drv.sync_seq); 372742c085fSChristian König return lower_32_bits(emitted); 373d38ceaf9SAlex Deucher } 374d38ceaf9SAlex Deucher 375d38ceaf9SAlex Deucher /** 376d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 377d38ceaf9SAlex Deucher * ready for use on the requested ring. 378d38ceaf9SAlex Deucher * 379d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 380d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 381d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 382d38ceaf9SAlex Deucher * 383d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 384d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 385d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 386d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 387d38ceaf9SAlex Deucher */ 388d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 389d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 390d38ceaf9SAlex Deucher unsigned irq_type) 391d38ceaf9SAlex Deucher { 392d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 393d38ceaf9SAlex Deucher uint64_t index; 394d38ceaf9SAlex Deucher 395d9e98ee2SLeo Liu if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 396d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 397d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 398d38ceaf9SAlex Deucher } else { 399d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 400d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 40110dd74eaSJames Zhu ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 40210dd74eaSJames Zhu ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 403d38ceaf9SAlex Deucher } 404742c085fSChristian König amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 405c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 406c6a4079bSChunming Zhou 407d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 408d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 409c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 410c6a4079bSChunming Zhou 4116e82c6e0SChristian König DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr " 4126e82c6e0SChristian König "0x%016llx, cpu addr 0x%p\n", ring->name, 413d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 414d38ceaf9SAlex Deucher return 0; 415d38ceaf9SAlex Deucher } 416d38ceaf9SAlex Deucher 417d38ceaf9SAlex Deucher /** 418d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 419d38ceaf9SAlex Deucher * for the requested ring. 420d38ceaf9SAlex Deucher * 421d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 422e6151a08SChristian König * @num_hw_submission: number of entries on the hardware queue 423d38ceaf9SAlex Deucher * 424d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 425d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 426d38ceaf9SAlex Deucher */ 427e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 428e6151a08SChristian König unsigned num_hw_submission) 429d38ceaf9SAlex Deucher { 430912dfc84SEvan Quan struct amdgpu_device *adev = ring->adev; 431687c1c2eSEvan Quan long timeout; 4325907a0d8SChristian König int r; 433d38ceaf9SAlex Deucher 434912dfc84SEvan Quan if (!adev) 435912dfc84SEvan Quan return -EINVAL; 436912dfc84SEvan Quan 437e6151a08SChristian König /* Check that num_hw_submission is a power of two */ 438e6151a08SChristian König if ((num_hw_submission & (num_hw_submission - 1)) != 0) 439e6151a08SChristian König return -EINVAL; 440e6151a08SChristian König 441d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 442d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 4435907a0d8SChristian König ring->fence_drv.sync_seq = 0; 444742c085fSChristian König atomic_set(&ring->fence_drv.last_seq, 0); 445d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 446d38ceaf9SAlex Deucher 4478c5e13ecSAndrey Grodzovsky timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 4488c5e13ecSAndrey Grodzovsky 44966067ad7SChunming Zhou ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 4504a7d74f1SChristian König spin_lock_init(&ring->fence_drv.lock); 45166067ad7SChunming Zhou ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 452c89377d1SChristian König GFP_KERNEL); 453c89377d1SChristian König if (!ring->fence_drv.fences) 454c89377d1SChristian König return -ENOMEM; 4555ec92a76SChristian König 456e2250442STrigger Huang /* No need to setup the GPU scheduler for KIQ ring */ 457e2250442STrigger Huang if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { 458912dfc84SEvan Quan switch (ring->funcs->type) { 459912dfc84SEvan Quan case AMDGPU_RING_TYPE_GFX: 460912dfc84SEvan Quan timeout = adev->gfx_timeout; 461912dfc84SEvan Quan break; 462912dfc84SEvan Quan case AMDGPU_RING_TYPE_COMPUTE: 463912dfc84SEvan Quan /* 464912dfc84SEvan Quan * For non-sriov case, no timeout enforce 465912dfc84SEvan Quan * on compute ring by default. Unless user 466912dfc84SEvan Quan * specifies a timeout for compute ring. 467912dfc84SEvan Quan * 468912dfc84SEvan Quan * For sriov case, always use the timeout 469912dfc84SEvan Quan * as gfx ring 470912dfc84SEvan Quan */ 471912dfc84SEvan Quan if (!amdgpu_sriov_vf(ring->adev)) 472912dfc84SEvan Quan timeout = adev->compute_timeout; 473687c1c2eSEvan Quan else 474912dfc84SEvan Quan timeout = adev->gfx_timeout; 475912dfc84SEvan Quan break; 476912dfc84SEvan Quan case AMDGPU_RING_TYPE_SDMA: 477912dfc84SEvan Quan timeout = adev->sdma_timeout; 478912dfc84SEvan Quan break; 479912dfc84SEvan Quan default: 480912dfc84SEvan Quan timeout = adev->video_timeout; 481912dfc84SEvan Quan break; 482912dfc84SEvan Quan } 483687c1c2eSEvan Quan 4841b1f42d8SLucas Stach r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 48595aa9b1dSMonk Liu num_hw_submission, amdgpu_job_hang_limit, 486687c1c2eSEvan Quan timeout, ring->name); 4874f839a24SChristian König if (r) { 4884f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 4894f839a24SChristian König ring->name); 4904f839a24SChristian König return r; 491b80d8475SAlex Deucher } 492e2250442STrigger Huang } 493d38ceaf9SAlex Deucher 4944f839a24SChristian König return 0; 4954f839a24SChristian König } 4964f839a24SChristian König 497d38ceaf9SAlex Deucher /** 498d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 499d38ceaf9SAlex Deucher * for all possible rings. 500d38ceaf9SAlex Deucher * 501d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 502d38ceaf9SAlex Deucher * 503d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 504d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 505d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 506d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 507d38ceaf9SAlex Deucher * Returns 0 for success. 508d38ceaf9SAlex Deucher */ 509d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 510d38ceaf9SAlex Deucher { 511d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 512d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 513d38ceaf9SAlex Deucher 514d38ceaf9SAlex Deucher return 0; 515d38ceaf9SAlex Deucher } 516d38ceaf9SAlex Deucher 517d38ceaf9SAlex Deucher /** 518d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 519d38ceaf9SAlex Deucher * for all possible rings. 520d38ceaf9SAlex Deucher * 521d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 522d38ceaf9SAlex Deucher * 523d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 524d38ceaf9SAlex Deucher */ 525d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 526d38ceaf9SAlex Deucher { 527c89377d1SChristian König unsigned i, j; 528c89377d1SChristian König int r; 529d38ceaf9SAlex Deucher 530d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 531d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 532c2776afeSChristian König 533d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 534d38ceaf9SAlex Deucher continue; 535d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 536d38ceaf9SAlex Deucher if (r) { 537d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 5382f9d4084SMonk Liu amdgpu_fence_driver_force_completion(ring); 539d38ceaf9SAlex Deucher } 540c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 541c6a4079bSChunming Zhou ring->fence_drv.irq_type); 5421b1f42d8SLucas Stach drm_sched_fini(&ring->sched); 5438c5e13ecSAndrey Grodzovsky del_timer_sync(&ring->fence_drv.fallback_timer); 544c89377d1SChristian König for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 545f54d1867SChris Wilson dma_fence_put(ring->fence_drv.fences[j]); 546c89377d1SChristian König kfree(ring->fence_drv.fences); 54754ddf3a6SGrazvydas Ignotas ring->fence_drv.fences = NULL; 548d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 549d38ceaf9SAlex Deucher } 550d38ceaf9SAlex Deucher } 551d38ceaf9SAlex Deucher 552d38ceaf9SAlex Deucher /** 5535ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 5545ceb54c6SAlex Deucher * for all possible rings. 5555ceb54c6SAlex Deucher * 5565ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5575ceb54c6SAlex Deucher * 5585ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 5595ceb54c6SAlex Deucher */ 5605ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 5615ceb54c6SAlex Deucher { 5625ceb54c6SAlex Deucher int i, r; 5635ceb54c6SAlex Deucher 5645ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5655ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5665ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5675ceb54c6SAlex Deucher continue; 5685ceb54c6SAlex Deucher 5695ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 5705ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 5715ceb54c6SAlex Deucher if (r) { 5725ceb54c6SAlex Deucher /* delay GPU reset to resume */ 5732f9d4084SMonk Liu amdgpu_fence_driver_force_completion(ring); 5745ceb54c6SAlex Deucher } 5755ceb54c6SAlex Deucher 5765ceb54c6SAlex Deucher /* disable the interrupt */ 5775ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 5785ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5795ceb54c6SAlex Deucher } 5805ceb54c6SAlex Deucher } 5815ceb54c6SAlex Deucher 5825ceb54c6SAlex Deucher /** 5835ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 5845ceb54c6SAlex Deucher * for all possible rings. 5855ceb54c6SAlex Deucher * 5865ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5875ceb54c6SAlex Deucher * 5885ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 5895ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 5905ceb54c6SAlex Deucher * start the fence driver on the rings it has using 5915ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 5925ceb54c6SAlex Deucher * Returns 0 for success. 5935ceb54c6SAlex Deucher */ 5945ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 5955ceb54c6SAlex Deucher { 5965ceb54c6SAlex Deucher int i; 5975ceb54c6SAlex Deucher 5985ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5995ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 6005ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 6015ceb54c6SAlex Deucher continue; 6025ceb54c6SAlex Deucher 6035ceb54c6SAlex Deucher /* enable the interrupt */ 6045ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 6055ceb54c6SAlex Deucher ring->fence_drv.irq_type); 6065ceb54c6SAlex Deucher } 6075ceb54c6SAlex Deucher } 6085ceb54c6SAlex Deucher 6095ceb54c6SAlex Deucher /** 6102f9d4084SMonk Liu * amdgpu_fence_driver_force_completion - force signal latest fence of ring 611d38ceaf9SAlex Deucher * 6122f9d4084SMonk Liu * @ring: fence of the ring to signal 613d38ceaf9SAlex Deucher * 614d38ceaf9SAlex Deucher */ 6152f9d4084SMonk Liu void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 616d38ceaf9SAlex Deucher { 6175907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 6182f9d4084SMonk Liu amdgpu_fence_process(ring); 61965781c78SMonk Liu } 62065781c78SMonk Liu 621a95e2642SChristian König /* 622a95e2642SChristian König * Common fence implementation 623a95e2642SChristian König */ 624a95e2642SChristian König 625f54d1867SChris Wilson static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 626a95e2642SChristian König { 627a95e2642SChristian König return "amdgpu"; 628a95e2642SChristian König } 629a95e2642SChristian König 630f54d1867SChris Wilson static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 631a95e2642SChristian König { 632a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 633a95e2642SChristian König return (const char *)fence->ring->name; 634a95e2642SChristian König } 635a95e2642SChristian König 636a95e2642SChristian König /** 6378c5e13ecSAndrey Grodzovsky * amdgpu_fence_enable_signaling - enable signalling on fence 6388c5e13ecSAndrey Grodzovsky * @fence: fence 6398c5e13ecSAndrey Grodzovsky * 6408c5e13ecSAndrey Grodzovsky * This function is called with fence_queue lock held, and adds a callback 6418c5e13ecSAndrey Grodzovsky * to fence_queue that checks if this fence is signaled, and if so it 6428c5e13ecSAndrey Grodzovsky * signals the fence and removes itself. 6438c5e13ecSAndrey Grodzovsky */ 6448c5e13ecSAndrey Grodzovsky static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 6458c5e13ecSAndrey Grodzovsky { 6468c5e13ecSAndrey Grodzovsky struct amdgpu_fence *fence = to_amdgpu_fence(f); 6478c5e13ecSAndrey Grodzovsky struct amdgpu_ring *ring = fence->ring; 6488c5e13ecSAndrey Grodzovsky 6498c5e13ecSAndrey Grodzovsky if (!timer_pending(&ring->fence_drv.fallback_timer)) 6508c5e13ecSAndrey Grodzovsky amdgpu_fence_schedule_fallback(ring); 6518c5e13ecSAndrey Grodzovsky 6528c5e13ecSAndrey Grodzovsky DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 6538c5e13ecSAndrey Grodzovsky 6548c5e13ecSAndrey Grodzovsky return true; 6558c5e13ecSAndrey Grodzovsky } 6568c5e13ecSAndrey Grodzovsky 6578c5e13ecSAndrey Grodzovsky /** 658b4413535SChristian König * amdgpu_fence_free - free up the fence memory 659b4413535SChristian König * 660b4413535SChristian König * @rcu: RCU callback head 661b4413535SChristian König * 662b4413535SChristian König * Free up the fence memory after the RCU grace period. 663b4413535SChristian König */ 664b4413535SChristian König static void amdgpu_fence_free(struct rcu_head *rcu) 665b49c84a5SChunming Zhou { 666f54d1867SChris Wilson struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 667b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 668b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 669b49c84a5SChunming Zhou } 670b49c84a5SChunming Zhou 671b4413535SChristian König /** 672b4413535SChristian König * amdgpu_fence_release - callback that fence can be freed 673b4413535SChristian König * 674b4413535SChristian König * @fence: fence 675b4413535SChristian König * 676b4413535SChristian König * This function is called when the reference count becomes zero. 677b4413535SChristian König * It just RCU schedules freeing up the fence. 678b4413535SChristian König */ 679f54d1867SChris Wilson static void amdgpu_fence_release(struct dma_fence *f) 680b4413535SChristian König { 681b4413535SChristian König call_rcu(&f->rcu, amdgpu_fence_free); 682b4413535SChristian König } 683b4413535SChristian König 684f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops = { 685a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 686a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 6878c5e13ecSAndrey Grodzovsky .enable_signaling = amdgpu_fence_enable_signaling, 688b49c84a5SChunming Zhou .release = amdgpu_fence_release, 689a95e2642SChristian König }; 690d38ceaf9SAlex Deucher 691d38ceaf9SAlex Deucher /* 692d38ceaf9SAlex Deucher * Fence debugfs 693d38ceaf9SAlex Deucher */ 694d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 695d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 696d38ceaf9SAlex Deucher { 697d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 698d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 699d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 7005907a0d8SChristian König int i; 701d38ceaf9SAlex Deucher 702d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 703d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 704d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 705d38ceaf9SAlex Deucher continue; 706d38ceaf9SAlex Deucher 707d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 708d38ceaf9SAlex Deucher 709344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 710742c085fSChristian König seq_printf(m, "Last signaled fence 0x%08x\n", 711742c085fSChristian König atomic_read(&ring->fence_drv.last_seq)); 712742c085fSChristian König seq_printf(m, "Last emitted 0x%08x\n", 7135907a0d8SChristian König ring->fence_drv.sync_seq); 714e71de076Spding 715ef3e1323SJack Xiao if (ring->funcs->type == AMDGPU_RING_TYPE_GFX || 716ef3e1323SJack Xiao ring->funcs->type == AMDGPU_RING_TYPE_SDMA) { 717ef3e1323SJack Xiao seq_printf(m, "Last signaled trailing fence 0x%08x\n", 718ef3e1323SJack Xiao le32_to_cpu(*ring->trail_fence_cpu_addr)); 719ef3e1323SJack Xiao seq_printf(m, "Last emitted 0x%08x\n", 720ef3e1323SJack Xiao ring->trail_seq); 721ef3e1323SJack Xiao } 722ef3e1323SJack Xiao 723e71de076Spding if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 724e71de076Spding continue; 725e71de076Spding 726e71de076Spding /* set in CP_VMID_PREEMPT and preemption occurred */ 727e71de076Spding seq_printf(m, "Last preempted 0x%08x\n", 728e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 729e71de076Spding /* set in CP_VMID_RESET and reset occurred */ 730e71de076Spding seq_printf(m, "Last reset 0x%08x\n", 731e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 732e71de076Spding /* Both preemption and reset occurred */ 733e71de076Spding seq_printf(m, "Last both 0x%08x\n", 734e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 735d38ceaf9SAlex Deucher } 736d38ceaf9SAlex Deucher return 0; 737d38ceaf9SAlex Deucher } 738d38ceaf9SAlex Deucher 73918db89b4SAlex Deucher /** 7405740682eSMonk Liu * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 74118db89b4SAlex Deucher * 74218db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 74318db89b4SAlex Deucher */ 7445740682eSMonk Liu static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) 74518db89b4SAlex Deucher { 74618db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 74718db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 74818db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 74918db89b4SAlex Deucher 7505740682eSMonk Liu seq_printf(m, "gpu recover\n"); 75112938fadSChristian König amdgpu_device_gpu_recover(adev, NULL); 75218db89b4SAlex Deucher 75318db89b4SAlex Deucher return 0; 75418db89b4SAlex Deucher } 75518db89b4SAlex Deucher 75606ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 757d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 7585740682eSMonk Liu {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} 759d38ceaf9SAlex Deucher }; 7604fbf87e2SMonk Liu 7614fbf87e2SMonk Liu static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { 7624fbf87e2SMonk Liu {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 7634fbf87e2SMonk Liu }; 764d38ceaf9SAlex Deucher #endif 765d38ceaf9SAlex Deucher 766d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 767d38ceaf9SAlex Deucher { 768d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 7694fbf87e2SMonk Liu if (amdgpu_sriov_vf(adev)) 7704fbf87e2SMonk Liu return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1); 77118db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 772d38ceaf9SAlex Deucher #else 773d38ceaf9SAlex Deucher return 0; 774d38ceaf9SAlex Deucher #endif 775d38ceaf9SAlex Deucher } 776d38ceaf9SAlex Deucher 777