1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 5022e5a2f4SChristian König struct amdgpu_fence { 51f54d1867SChris Wilson struct dma_fence base; 5222e5a2f4SChristian König 5322e5a2f4SChristian König /* RB, DMA, etc. */ 5422e5a2f4SChristian König struct amdgpu_ring *ring; 5522e5a2f4SChristian König }; 5622e5a2f4SChristian König 57b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 58b49c84a5SChunming Zhou 59d573de2dSRex Zhu int amdgpu_fence_slab_init(void) 60d573de2dSRex Zhu { 61d573de2dSRex Zhu amdgpu_fence_slab = kmem_cache_create( 62d573de2dSRex Zhu "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 63d573de2dSRex Zhu SLAB_HWCACHE_ALIGN, NULL); 64d573de2dSRex Zhu if (!amdgpu_fence_slab) 65d573de2dSRex Zhu return -ENOMEM; 66d573de2dSRex Zhu return 0; 67d573de2dSRex Zhu } 68d573de2dSRex Zhu 69d573de2dSRex Zhu void amdgpu_fence_slab_fini(void) 70d573de2dSRex Zhu { 710f10425eSGrazvydas Ignotas rcu_barrier(); 72d573de2dSRex Zhu kmem_cache_destroy(amdgpu_fence_slab); 73d573de2dSRex Zhu } 7422e5a2f4SChristian König /* 7522e5a2f4SChristian König * Cast helper 7622e5a2f4SChristian König */ 77f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops; 78f54d1867SChris Wilson static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 7922e5a2f4SChristian König { 8022e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 8122e5a2f4SChristian König 8222e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 8322e5a2f4SChristian König return __f; 8422e5a2f4SChristian König 8522e5a2f4SChristian König return NULL; 8622e5a2f4SChristian König } 8722e5a2f4SChristian König 88d38ceaf9SAlex Deucher /** 89d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 90d38ceaf9SAlex Deucher * 91d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 92d38ceaf9SAlex Deucher * @seq: sequence number to write 93d38ceaf9SAlex Deucher * 94d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 95d38ceaf9SAlex Deucher */ 96d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 97d38ceaf9SAlex Deucher { 98d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher if (drv->cpu_addr) 101d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 102d38ceaf9SAlex Deucher } 103d38ceaf9SAlex Deucher 104d38ceaf9SAlex Deucher /** 105d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 106d38ceaf9SAlex Deucher * 107d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 108d38ceaf9SAlex Deucher * 109d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 110d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 111d38ceaf9SAlex Deucher */ 112d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 113d38ceaf9SAlex Deucher { 114d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 115d38ceaf9SAlex Deucher u32 seq = 0; 116d38ceaf9SAlex Deucher 117d38ceaf9SAlex Deucher if (drv->cpu_addr) 118d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 119d38ceaf9SAlex Deucher else 120742c085fSChristian König seq = atomic_read(&drv->last_seq); 121d38ceaf9SAlex Deucher 122d38ceaf9SAlex Deucher return seq; 123d38ceaf9SAlex Deucher } 124d38ceaf9SAlex Deucher 125d38ceaf9SAlex Deucher /** 126d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 127d38ceaf9SAlex Deucher * 128d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 129364beb2cSChristian König * @f: resulting fence object 130d38ceaf9SAlex Deucher * 131d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 132d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 133d38ceaf9SAlex Deucher */ 134f54d1867SChris Wilson int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f) 135d38ceaf9SAlex Deucher { 136d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 137364beb2cSChristian König struct amdgpu_fence *fence; 138f54d1867SChris Wilson struct dma_fence *old, **ptr; 139742c085fSChristian König uint32_t seq; 140d38ceaf9SAlex Deucher 141364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 142364beb2cSChristian König if (fence == NULL) 143d38ceaf9SAlex Deucher return -ENOMEM; 144364beb2cSChristian König 145742c085fSChristian König seq = ++ring->fence_drv.sync_seq; 146364beb2cSChristian König fence->ring = ring; 147f54d1867SChris Wilson dma_fence_init(&fence->base, &amdgpu_fence_ops, 1484a7d74f1SChristian König &ring->fence_drv.lock, 1497f06c236Smonk.liu adev->fence_context + ring->idx, 150742c085fSChristian König seq); 151890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 152742c085fSChristian König seq, AMDGPU_FENCE_FLAG_INT); 153c89377d1SChristian König 154742c085fSChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 155c89377d1SChristian König /* This function can't be called concurrently anyway, otherwise 156c89377d1SChristian König * emitting the fence would mess up the hardware ring buffer. 157c89377d1SChristian König */ 158fc387a0bSChunming Zhou old = rcu_dereference_protected(*ptr, 1); 159f54d1867SChris Wilson if (old && !dma_fence_is_signaled(old)) { 160fc387a0bSChunming Zhou DRM_INFO("rcu slot is busy\n"); 161f54d1867SChris Wilson dma_fence_wait(old, false); 162fc387a0bSChunming Zhou } 163c89377d1SChristian König 164f54d1867SChris Wilson rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 165c89377d1SChristian König 166364beb2cSChristian König *f = &fence->base; 167c89377d1SChristian König 168d38ceaf9SAlex Deucher return 0; 169d38ceaf9SAlex Deucher } 170d38ceaf9SAlex Deucher 171d38ceaf9SAlex Deucher /** 172c2776afeSChristian König * amdgpu_fence_schedule_fallback - schedule fallback check 173c2776afeSChristian König * 174c2776afeSChristian König * @ring: pointer to struct amdgpu_ring 175c2776afeSChristian König * 176c2776afeSChristian König * Start a timer as fallback to our interrupts. 177c2776afeSChristian König */ 178c2776afeSChristian König static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 179c2776afeSChristian König { 180c2776afeSChristian König mod_timer(&ring->fence_drv.fallback_timer, 181c2776afeSChristian König jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 182c2776afeSChristian König } 183c2776afeSChristian König 184c2776afeSChristian König /** 185ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 186d38ceaf9SAlex Deucher * 187d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 188d38ceaf9SAlex Deucher * 189d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 190ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 191ca08e04dSChristian König * sequence number has increased. 192d38ceaf9SAlex Deucher */ 193ca08e04dSChristian König void amdgpu_fence_process(struct amdgpu_ring *ring) 194d38ceaf9SAlex Deucher { 1954a7d74f1SChristian König struct amdgpu_fence_driver *drv = &ring->fence_drv; 196742c085fSChristian König uint32_t seq, last_seq; 1974a7d74f1SChristian König int r; 198d38ceaf9SAlex Deucher 199d38ceaf9SAlex Deucher do { 200742c085fSChristian König last_seq = atomic_read(&ring->fence_drv.last_seq); 201d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 202d38ceaf9SAlex Deucher 203742c085fSChristian König } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 204d38ceaf9SAlex Deucher 205742c085fSChristian König if (seq != ring->fence_drv.sync_seq) 206c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 207d38ceaf9SAlex Deucher 2082ef004d9SChristian König if (unlikely(seq == last_seq)) 2092ef004d9SChristian König return; 2102ef004d9SChristian König 2114f399a08SChristian König last_seq &= drv->num_fences_mask; 2124f399a08SChristian König seq &= drv->num_fences_mask; 2134f399a08SChristian König 2142ef004d9SChristian König do { 215f54d1867SChris Wilson struct dma_fence *fence, **ptr; 2164a7d74f1SChristian König 2174f399a08SChristian König ++last_seq; 2184f399a08SChristian König last_seq &= drv->num_fences_mask; 2194f399a08SChristian König ptr = &drv->fences[last_seq]; 2204a7d74f1SChristian König 2214a7d74f1SChristian König /* There is always exactly one thread signaling this fence slot */ 2224a7d74f1SChristian König fence = rcu_dereference_protected(*ptr, 1); 22384fae133SMuhammad Falak R Wani RCU_INIT_POINTER(*ptr, NULL); 2244a7d74f1SChristian König 2254f399a08SChristian König if (!fence) 2264f399a08SChristian König continue; 2274a7d74f1SChristian König 228f54d1867SChris Wilson r = dma_fence_signal(fence); 2294a7d74f1SChristian König if (!r) 230f54d1867SChris Wilson DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 2314a7d74f1SChristian König else 2324a7d74f1SChristian König BUG(); 2334a7d74f1SChristian König 234f54d1867SChris Wilson dma_fence_put(fence); 2352ef004d9SChristian König } while (last_seq != seq); 236e0d8f3c3SChunming Zhou } 237d38ceaf9SAlex Deucher 238d38ceaf9SAlex Deucher /** 239c2776afeSChristian König * amdgpu_fence_fallback - fallback for hardware interrupts 240c2776afeSChristian König * 241c2776afeSChristian König * @work: delayed work item 242c2776afeSChristian König * 243c2776afeSChristian König * Checks for fence activity. 244c2776afeSChristian König */ 245c2776afeSChristian König static void amdgpu_fence_fallback(unsigned long arg) 246c2776afeSChristian König { 247c2776afeSChristian König struct amdgpu_ring *ring = (void *)arg; 248c2776afeSChristian König 249c2776afeSChristian König amdgpu_fence_process(ring); 250c2776afeSChristian König } 251c2776afeSChristian König 252c2776afeSChristian König /** 253d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 254d38ceaf9SAlex Deucher * 255d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 256d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 257d38ceaf9SAlex Deucher * 258d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 259d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 260d38ceaf9SAlex Deucher */ 261d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 262d38ceaf9SAlex Deucher { 263f09c2be4SChristian König uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq); 264f54d1867SChris Wilson struct dma_fence *fence, **ptr; 265f09c2be4SChristian König int r; 26600d2a2b2SChristian König 2677f06c236Smonk.liu if (!seq) 268d38ceaf9SAlex Deucher return 0; 269d38ceaf9SAlex Deucher 270f09c2be4SChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 271f09c2be4SChristian König rcu_read_lock(); 272f09c2be4SChristian König fence = rcu_dereference(*ptr); 273f54d1867SChris Wilson if (!fence || !dma_fence_get_rcu(fence)) { 274f09c2be4SChristian König rcu_read_unlock(); 275f09c2be4SChristian König return 0; 276f09c2be4SChristian König } 277f09c2be4SChristian König rcu_read_unlock(); 278f09c2be4SChristian König 279f54d1867SChris Wilson r = dma_fence_wait(fence, false); 280f54d1867SChris Wilson dma_fence_put(fence); 281f09c2be4SChristian König return r; 282d38ceaf9SAlex Deucher } 283d38ceaf9SAlex Deucher 284d38ceaf9SAlex Deucher /** 285d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 286d38ceaf9SAlex Deucher * 287d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 288d38ceaf9SAlex Deucher * 289d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 290d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 291d38ceaf9SAlex Deucher * dynpm code to ring track activity. 292d38ceaf9SAlex Deucher */ 293d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 294d38ceaf9SAlex Deucher { 295d38ceaf9SAlex Deucher uint64_t emitted; 296d38ceaf9SAlex Deucher 297d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 298d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 299d38ceaf9SAlex Deucher */ 300d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 301742c085fSChristian König emitted = 0x100000000ull; 302742c085fSChristian König emitted -= atomic_read(&ring->fence_drv.last_seq); 303742c085fSChristian König emitted += ACCESS_ONCE(ring->fence_drv.sync_seq); 304742c085fSChristian König return lower_32_bits(emitted); 305d38ceaf9SAlex Deucher } 306d38ceaf9SAlex Deucher 307d38ceaf9SAlex Deucher /** 308d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 309d38ceaf9SAlex Deucher * ready for use on the requested ring. 310d38ceaf9SAlex Deucher * 311d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 312d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 313d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 314d38ceaf9SAlex Deucher * 315d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 316d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 317d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 318d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 319d38ceaf9SAlex Deucher */ 320d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 321d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 322d38ceaf9SAlex Deucher unsigned irq_type) 323d38ceaf9SAlex Deucher { 324d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 325d38ceaf9SAlex Deucher uint64_t index; 326d38ceaf9SAlex Deucher 327d38ceaf9SAlex Deucher if (ring != &adev->uvd.ring) { 328d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 329d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 330d38ceaf9SAlex Deucher } else { 331d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 332d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 333d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; 334d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; 335d38ceaf9SAlex Deucher } 336742c085fSChristian König amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 337c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 338c6a4079bSChunming Zhou 339d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 340d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 341c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 342c6a4079bSChunming Zhou 343d38ceaf9SAlex Deucher dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " 344d38ceaf9SAlex Deucher "cpu addr 0x%p\n", ring->idx, 345d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 346d38ceaf9SAlex Deucher return 0; 347d38ceaf9SAlex Deucher } 348d38ceaf9SAlex Deucher 349d38ceaf9SAlex Deucher /** 350d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 351d38ceaf9SAlex Deucher * for the requested ring. 352d38ceaf9SAlex Deucher * 353d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 354e6151a08SChristian König * @num_hw_submission: number of entries on the hardware queue 355d38ceaf9SAlex Deucher * 356d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 357d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 358d38ceaf9SAlex Deucher */ 359e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 360e6151a08SChristian König unsigned num_hw_submission) 361d38ceaf9SAlex Deucher { 362cadf97b1SChunming Zhou long timeout; 3635907a0d8SChristian König int r; 364d38ceaf9SAlex Deucher 365e6151a08SChristian König /* Check that num_hw_submission is a power of two */ 366e6151a08SChristian König if ((num_hw_submission & (num_hw_submission - 1)) != 0) 367e6151a08SChristian König return -EINVAL; 368e6151a08SChristian König 369d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 370d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 3715907a0d8SChristian König ring->fence_drv.sync_seq = 0; 372742c085fSChristian König atomic_set(&ring->fence_drv.last_seq, 0); 373d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 374d38ceaf9SAlex Deucher 375c2776afeSChristian König setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 376c2776afeSChristian König (unsigned long)ring); 377b80d8475SAlex Deucher 37866067ad7SChunming Zhou ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 3794a7d74f1SChristian König spin_lock_init(&ring->fence_drv.lock); 38066067ad7SChunming Zhou ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 381c89377d1SChristian König GFP_KERNEL); 382c89377d1SChristian König if (!ring->fence_drv.fences) 383c89377d1SChristian König return -ENOMEM; 3845ec92a76SChristian König 385e2250442STrigger Huang /* No need to setup the GPU scheduler for KIQ ring */ 386e2250442STrigger Huang if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { 387cadf97b1SChunming Zhou timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 3882440ff2cSJunwei Zhang if (timeout == 0) { 3892440ff2cSJunwei Zhang /* 3902440ff2cSJunwei Zhang * FIXME: 3912440ff2cSJunwei Zhang * Delayed workqueue cannot use it directly, 3922440ff2cSJunwei Zhang * so the scheduler will not use delayed workqueue if 3932440ff2cSJunwei Zhang * MAX_SCHEDULE_TIMEOUT is set. 3942440ff2cSJunwei Zhang * Currently keep it simple and silly. 3952440ff2cSJunwei Zhang */ 3962440ff2cSJunwei Zhang timeout = MAX_SCHEDULE_TIMEOUT; 3972440ff2cSJunwei Zhang } 3984f839a24SChristian König r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 399e6151a08SChristian König num_hw_submission, 4002440ff2cSJunwei Zhang timeout, ring->name); 4014f839a24SChristian König if (r) { 4024f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 4034f839a24SChristian König ring->name); 4044f839a24SChristian König return r; 405b80d8475SAlex Deucher } 406e2250442STrigger Huang } 407d38ceaf9SAlex Deucher 4084f839a24SChristian König return 0; 4094f839a24SChristian König } 4104f839a24SChristian König 411d38ceaf9SAlex Deucher /** 412d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 413d38ceaf9SAlex Deucher * for all possible rings. 414d38ceaf9SAlex Deucher * 415d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 416d38ceaf9SAlex Deucher * 417d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 418d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 419d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 420d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 421d38ceaf9SAlex Deucher * Returns 0 for success. 422d38ceaf9SAlex Deucher */ 423d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 424d38ceaf9SAlex Deucher { 425d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 426d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 427d38ceaf9SAlex Deucher 428d38ceaf9SAlex Deucher return 0; 429d38ceaf9SAlex Deucher } 430d38ceaf9SAlex Deucher 431d38ceaf9SAlex Deucher /** 432d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 433d38ceaf9SAlex Deucher * for all possible rings. 434d38ceaf9SAlex Deucher * 435d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 436d38ceaf9SAlex Deucher * 437d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 438d38ceaf9SAlex Deucher */ 439d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 440d38ceaf9SAlex Deucher { 441c89377d1SChristian König unsigned i, j; 442c89377d1SChristian König int r; 443d38ceaf9SAlex Deucher 444d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 445d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 446c2776afeSChristian König 447d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 448d38ceaf9SAlex Deucher continue; 449d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 450d38ceaf9SAlex Deucher if (r) { 451d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 452d38ceaf9SAlex Deucher amdgpu_fence_driver_force_completion(adev); 453d38ceaf9SAlex Deucher } 454c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 455c6a4079bSChunming Zhou ring->fence_drv.irq_type); 4564f839a24SChristian König amd_sched_fini(&ring->sched); 457c2776afeSChristian König del_timer_sync(&ring->fence_drv.fallback_timer); 458c89377d1SChristian König for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 459f54d1867SChris Wilson dma_fence_put(ring->fence_drv.fences[j]); 460c89377d1SChristian König kfree(ring->fence_drv.fences); 46154ddf3a6SGrazvydas Ignotas ring->fence_drv.fences = NULL; 462d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 463d38ceaf9SAlex Deucher } 464d38ceaf9SAlex Deucher } 465d38ceaf9SAlex Deucher 466d38ceaf9SAlex Deucher /** 4675ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 4685ceb54c6SAlex Deucher * for all possible rings. 4695ceb54c6SAlex Deucher * 4705ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4715ceb54c6SAlex Deucher * 4725ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 4735ceb54c6SAlex Deucher */ 4745ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 4755ceb54c6SAlex Deucher { 4765ceb54c6SAlex Deucher int i, r; 4775ceb54c6SAlex Deucher 4785ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 4795ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 4805ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 4815ceb54c6SAlex Deucher continue; 4825ceb54c6SAlex Deucher 4835ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 4845ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 4855ceb54c6SAlex Deucher if (r) { 4865ceb54c6SAlex Deucher /* delay GPU reset to resume */ 4875ceb54c6SAlex Deucher amdgpu_fence_driver_force_completion(adev); 4885ceb54c6SAlex Deucher } 4895ceb54c6SAlex Deucher 4905ceb54c6SAlex Deucher /* disable the interrupt */ 4915ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 4925ceb54c6SAlex Deucher ring->fence_drv.irq_type); 4935ceb54c6SAlex Deucher } 4945ceb54c6SAlex Deucher } 4955ceb54c6SAlex Deucher 4965ceb54c6SAlex Deucher /** 4975ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 4985ceb54c6SAlex Deucher * for all possible rings. 4995ceb54c6SAlex Deucher * 5005ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5015ceb54c6SAlex Deucher * 5025ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 5035ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 5045ceb54c6SAlex Deucher * start the fence driver on the rings it has using 5055ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 5065ceb54c6SAlex Deucher * Returns 0 for success. 5075ceb54c6SAlex Deucher */ 5085ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 5095ceb54c6SAlex Deucher { 5105ceb54c6SAlex Deucher int i; 5115ceb54c6SAlex Deucher 5125ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5135ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5145ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5155ceb54c6SAlex Deucher continue; 5165ceb54c6SAlex Deucher 5175ceb54c6SAlex Deucher /* enable the interrupt */ 5185ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 5195ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5205ceb54c6SAlex Deucher } 5215ceb54c6SAlex Deucher } 5225ceb54c6SAlex Deucher 5235ceb54c6SAlex Deucher /** 524d38ceaf9SAlex Deucher * amdgpu_fence_driver_force_completion - force all fence waiter to complete 525d38ceaf9SAlex Deucher * 526d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 527d38ceaf9SAlex Deucher * 528d38ceaf9SAlex Deucher * In case of GPU reset failure make sure no process keep waiting on fence 529d38ceaf9SAlex Deucher * that will never complete. 530d38ceaf9SAlex Deucher */ 531d38ceaf9SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) 532d38ceaf9SAlex Deucher { 533d38ceaf9SAlex Deucher int i; 534d38ceaf9SAlex Deucher 535d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 536d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 537d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 538d38ceaf9SAlex Deucher continue; 539d38ceaf9SAlex Deucher 5405907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 541d38ceaf9SAlex Deucher } 542d38ceaf9SAlex Deucher } 543d38ceaf9SAlex Deucher 544a95e2642SChristian König /* 545a95e2642SChristian König * Common fence implementation 546a95e2642SChristian König */ 547a95e2642SChristian König 548f54d1867SChris Wilson static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 549a95e2642SChristian König { 550a95e2642SChristian König return "amdgpu"; 551a95e2642SChristian König } 552a95e2642SChristian König 553f54d1867SChris Wilson static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 554a95e2642SChristian König { 555a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 556a95e2642SChristian König return (const char *)fence->ring->name; 557a95e2642SChristian König } 558a95e2642SChristian König 559a95e2642SChristian König /** 560a95e2642SChristian König * amdgpu_fence_enable_signaling - enable signalling on fence 561a95e2642SChristian König * @fence: fence 562a95e2642SChristian König * 563a95e2642SChristian König * This function is called with fence_queue lock held, and adds a callback 564a95e2642SChristian König * to fence_queue that checks if this fence is signaled, and if so it 565a95e2642SChristian König * signals the fence and removes itself. 566a95e2642SChristian König */ 567f54d1867SChris Wilson static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 568a95e2642SChristian König { 569a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 570a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 571a95e2642SChristian König 572c2776afeSChristian König if (!timer_pending(&ring->fence_drv.fallback_timer)) 573c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 5744a7d74f1SChristian König 575f54d1867SChris Wilson DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 5764a7d74f1SChristian König 577a95e2642SChristian König return true; 578a95e2642SChristian König } 579a95e2642SChristian König 580b4413535SChristian König /** 581b4413535SChristian König * amdgpu_fence_free - free up the fence memory 582b4413535SChristian König * 583b4413535SChristian König * @rcu: RCU callback head 584b4413535SChristian König * 585b4413535SChristian König * Free up the fence memory after the RCU grace period. 586b4413535SChristian König */ 587b4413535SChristian König static void amdgpu_fence_free(struct rcu_head *rcu) 588b49c84a5SChunming Zhou { 589f54d1867SChris Wilson struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 590b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 591b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 592b49c84a5SChunming Zhou } 593b49c84a5SChunming Zhou 594b4413535SChristian König /** 595b4413535SChristian König * amdgpu_fence_release - callback that fence can be freed 596b4413535SChristian König * 597b4413535SChristian König * @fence: fence 598b4413535SChristian König * 599b4413535SChristian König * This function is called when the reference count becomes zero. 600b4413535SChristian König * It just RCU schedules freeing up the fence. 601b4413535SChristian König */ 602f54d1867SChris Wilson static void amdgpu_fence_release(struct dma_fence *f) 603b4413535SChristian König { 604b4413535SChristian König call_rcu(&f->rcu, amdgpu_fence_free); 605b4413535SChristian König } 606b4413535SChristian König 607f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops = { 608a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 609a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 610a95e2642SChristian König .enable_signaling = amdgpu_fence_enable_signaling, 611f54d1867SChris Wilson .wait = dma_fence_default_wait, 612b49c84a5SChunming Zhou .release = amdgpu_fence_release, 613a95e2642SChristian König }; 614d38ceaf9SAlex Deucher 615d38ceaf9SAlex Deucher /* 616d38ceaf9SAlex Deucher * Fence debugfs 617d38ceaf9SAlex Deucher */ 618d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 619d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 620d38ceaf9SAlex Deucher { 621d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 622d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 623d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 6245907a0d8SChristian König int i; 625d38ceaf9SAlex Deucher 626d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 627d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 628d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 629d38ceaf9SAlex Deucher continue; 630d38ceaf9SAlex Deucher 631d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 632d38ceaf9SAlex Deucher 633344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 634742c085fSChristian König seq_printf(m, "Last signaled fence 0x%08x\n", 635742c085fSChristian König atomic_read(&ring->fence_drv.last_seq)); 636742c085fSChristian König seq_printf(m, "Last emitted 0x%08x\n", 6375907a0d8SChristian König ring->fence_drv.sync_seq); 638d38ceaf9SAlex Deucher } 639d38ceaf9SAlex Deucher return 0; 640d38ceaf9SAlex Deucher } 641d38ceaf9SAlex Deucher 64218db89b4SAlex Deucher /** 64318db89b4SAlex Deucher * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset 64418db89b4SAlex Deucher * 64518db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 64618db89b4SAlex Deucher */ 64718db89b4SAlex Deucher static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) 64818db89b4SAlex Deucher { 64918db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 65018db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 65118db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 65218db89b4SAlex Deucher 65318db89b4SAlex Deucher seq_printf(m, "gpu reset\n"); 65418db89b4SAlex Deucher amdgpu_gpu_reset(adev); 65518db89b4SAlex Deucher 65618db89b4SAlex Deucher return 0; 65718db89b4SAlex Deucher } 65818db89b4SAlex Deucher 65906ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 660d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 66118db89b4SAlex Deucher {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} 662d38ceaf9SAlex Deucher }; 663d38ceaf9SAlex Deucher #endif 664d38ceaf9SAlex Deucher 665d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 666d38ceaf9SAlex Deucher { 667d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 66818db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 669d38ceaf9SAlex Deucher #else 670d38ceaf9SAlex Deucher return 0; 671d38ceaf9SAlex Deucher #endif 672d38ceaf9SAlex Deucher } 673d38ceaf9SAlex Deucher 674