1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 50b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 51b49c84a5SChunming Zhou static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0); 52b49c84a5SChunming Zhou 53d38ceaf9SAlex Deucher /** 54d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 55d38ceaf9SAlex Deucher * 56d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 57d38ceaf9SAlex Deucher * @seq: sequence number to write 58d38ceaf9SAlex Deucher * 59d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 60d38ceaf9SAlex Deucher */ 61d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 62d38ceaf9SAlex Deucher { 63d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 64d38ceaf9SAlex Deucher 65d38ceaf9SAlex Deucher if (drv->cpu_addr) 66d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 67d38ceaf9SAlex Deucher } 68d38ceaf9SAlex Deucher 69d38ceaf9SAlex Deucher /** 70d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 71d38ceaf9SAlex Deucher * 72d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 73d38ceaf9SAlex Deucher * 74d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 75d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 76d38ceaf9SAlex Deucher */ 77d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 78d38ceaf9SAlex Deucher { 79d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 80d38ceaf9SAlex Deucher u32 seq = 0; 81d38ceaf9SAlex Deucher 82d38ceaf9SAlex Deucher if (drv->cpu_addr) 83d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 84d38ceaf9SAlex Deucher else 85d38ceaf9SAlex Deucher seq = lower_32_bits(atomic64_read(&drv->last_seq)); 86d38ceaf9SAlex Deucher 87d38ceaf9SAlex Deucher return seq; 88d38ceaf9SAlex Deucher } 89d38ceaf9SAlex Deucher 90d38ceaf9SAlex Deucher /** 91d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 92d38ceaf9SAlex Deucher * 93d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 94d38ceaf9SAlex Deucher * @owner: creator of the fence 95d38ceaf9SAlex Deucher * @fence: amdgpu fence object 96d38ceaf9SAlex Deucher * 97d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 98d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 99d38ceaf9SAlex Deucher */ 100d38ceaf9SAlex Deucher int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 101d38ceaf9SAlex Deucher struct amdgpu_fence **fence) 102d38ceaf9SAlex Deucher { 103d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 104d38ceaf9SAlex Deucher 105d38ceaf9SAlex Deucher /* we are protected by the ring emission mutex */ 106b49c84a5SChunming Zhou *fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 107d38ceaf9SAlex Deucher if ((*fence) == NULL) { 108d38ceaf9SAlex Deucher return -ENOMEM; 109d38ceaf9SAlex Deucher } 110d38ceaf9SAlex Deucher (*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx]; 111d38ceaf9SAlex Deucher (*fence)->ring = ring; 112d38ceaf9SAlex Deucher (*fence)->owner = owner; 113d38ceaf9SAlex Deucher fence_init(&(*fence)->base, &amdgpu_fence_ops, 1147f06c236Smonk.liu &ring->fence_drv.fence_queue.lock, 1157f06c236Smonk.liu adev->fence_context + ring->idx, 116d38ceaf9SAlex Deucher (*fence)->seq); 117890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 118890ee23fSChunming Zhou (*fence)->seq, 119890ee23fSChunming Zhou AMDGPU_FENCE_FLAG_INT); 120d38ceaf9SAlex Deucher return 0; 121d38ceaf9SAlex Deucher } 122d38ceaf9SAlex Deucher 123d38ceaf9SAlex Deucher /** 124c2776afeSChristian König * amdgpu_fence_schedule_fallback - schedule fallback check 125c2776afeSChristian König * 126c2776afeSChristian König * @ring: pointer to struct amdgpu_ring 127c2776afeSChristian König * 128c2776afeSChristian König * Start a timer as fallback to our interrupts. 129c2776afeSChristian König */ 130c2776afeSChristian König static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 131c2776afeSChristian König { 132c2776afeSChristian König mod_timer(&ring->fence_drv.fallback_timer, 133c2776afeSChristian König jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 134c2776afeSChristian König } 135c2776afeSChristian König 136c2776afeSChristian König /** 137d38ceaf9SAlex Deucher * amdgpu_fence_activity - check for fence activity 138d38ceaf9SAlex Deucher * 139d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 140d38ceaf9SAlex Deucher * 141d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 142d38ceaf9SAlex Deucher * signalled fence value. Returns true if activity occured 143d38ceaf9SAlex Deucher * on the ring, and the fence_queue should be waken up. 144d38ceaf9SAlex Deucher */ 145d38ceaf9SAlex Deucher static bool amdgpu_fence_activity(struct amdgpu_ring *ring) 146d38ceaf9SAlex Deucher { 147d38ceaf9SAlex Deucher uint64_t seq, last_seq, last_emitted; 148d38ceaf9SAlex Deucher unsigned count_loop = 0; 149d38ceaf9SAlex Deucher bool wake = false; 150d38ceaf9SAlex Deucher 151d38ceaf9SAlex Deucher /* Note there is a scenario here for an infinite loop but it's 152d38ceaf9SAlex Deucher * very unlikely to happen. For it to happen, the current polling 153d38ceaf9SAlex Deucher * process need to be interrupted by another process and another 154d38ceaf9SAlex Deucher * process needs to update the last_seq btw the atomic read and 155d38ceaf9SAlex Deucher * xchg of the current process. 156d38ceaf9SAlex Deucher * 157d38ceaf9SAlex Deucher * More over for this to go in infinite loop there need to be 15886c2b790SJammy Zhou * continuously new fence signaled ie amdgpu_fence_read needs 159d38ceaf9SAlex Deucher * to return a different value each time for both the currently 160d38ceaf9SAlex Deucher * polling process and the other process that xchg the last_seq 161d38ceaf9SAlex Deucher * btw atomic read and xchg of the current process. And the 162d38ceaf9SAlex Deucher * value the other process set as last seq must be higher than 163d38ceaf9SAlex Deucher * the seq value we just read. Which means that current process 16486c2b790SJammy Zhou * need to be interrupted after amdgpu_fence_read and before 165d38ceaf9SAlex Deucher * atomic xchg. 166d38ceaf9SAlex Deucher * 167d38ceaf9SAlex Deucher * To be even more safe we count the number of time we loop and 168d38ceaf9SAlex Deucher * we bail after 10 loop just accepting the fact that we might 169d38ceaf9SAlex Deucher * have temporarly set the last_seq not to the true real last 170d38ceaf9SAlex Deucher * seq but to an older one. 171d38ceaf9SAlex Deucher */ 172d38ceaf9SAlex Deucher last_seq = atomic64_read(&ring->fence_drv.last_seq); 173d38ceaf9SAlex Deucher do { 174d38ceaf9SAlex Deucher last_emitted = ring->fence_drv.sync_seq[ring->idx]; 175d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 176d38ceaf9SAlex Deucher seq |= last_seq & 0xffffffff00000000LL; 177d38ceaf9SAlex Deucher if (seq < last_seq) { 178d38ceaf9SAlex Deucher seq &= 0xffffffff; 179d38ceaf9SAlex Deucher seq |= last_emitted & 0xffffffff00000000LL; 180d38ceaf9SAlex Deucher } 181d38ceaf9SAlex Deucher 182d38ceaf9SAlex Deucher if (seq <= last_seq || seq > last_emitted) { 183d38ceaf9SAlex Deucher break; 184d38ceaf9SAlex Deucher } 185d38ceaf9SAlex Deucher /* If we loop over we don't want to return without 186d38ceaf9SAlex Deucher * checking if a fence is signaled as it means that the 187d38ceaf9SAlex Deucher * seq we just read is different from the previous on. 188d38ceaf9SAlex Deucher */ 189d38ceaf9SAlex Deucher wake = true; 190d38ceaf9SAlex Deucher last_seq = seq; 191d38ceaf9SAlex Deucher if ((count_loop++) > 10) { 192d38ceaf9SAlex Deucher /* We looped over too many time leave with the 193d38ceaf9SAlex Deucher * fact that we might have set an older fence 194d38ceaf9SAlex Deucher * seq then the current real last seq as signaled 195d38ceaf9SAlex Deucher * by the hw. 196d38ceaf9SAlex Deucher */ 197d38ceaf9SAlex Deucher break; 198d38ceaf9SAlex Deucher } 199d38ceaf9SAlex Deucher } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq); 200d38ceaf9SAlex Deucher 201d38ceaf9SAlex Deucher if (seq < last_emitted) 202c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 203d38ceaf9SAlex Deucher 204d38ceaf9SAlex Deucher return wake; 205d38ceaf9SAlex Deucher } 206d38ceaf9SAlex Deucher 207d38ceaf9SAlex Deucher /** 208d38ceaf9SAlex Deucher * amdgpu_fence_process - process a fence 209d38ceaf9SAlex Deucher * 210d38ceaf9SAlex Deucher * @adev: amdgpu_device pointer 211d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 212d38ceaf9SAlex Deucher * 213d38ceaf9SAlex Deucher * Checks the current fence value and wakes the fence queue 214d38ceaf9SAlex Deucher * if the sequence number has increased (all asics). 215d38ceaf9SAlex Deucher */ 216d38ceaf9SAlex Deucher void amdgpu_fence_process(struct amdgpu_ring *ring) 217d38ceaf9SAlex Deucher { 21868ed3de4SChristian König if (amdgpu_fence_activity(ring)) 2197f06c236Smonk.liu wake_up_all(&ring->fence_drv.fence_queue); 220e0d8f3c3SChunming Zhou } 221d38ceaf9SAlex Deucher 222d38ceaf9SAlex Deucher /** 223c2776afeSChristian König * amdgpu_fence_fallback - fallback for hardware interrupts 224c2776afeSChristian König * 225c2776afeSChristian König * @work: delayed work item 226c2776afeSChristian König * 227c2776afeSChristian König * Checks for fence activity. 228c2776afeSChristian König */ 229c2776afeSChristian König static void amdgpu_fence_fallback(unsigned long arg) 230c2776afeSChristian König { 231c2776afeSChristian König struct amdgpu_ring *ring = (void *)arg; 232c2776afeSChristian König 233c2776afeSChristian König amdgpu_fence_process(ring); 234c2776afeSChristian König } 235c2776afeSChristian König 236c2776afeSChristian König /** 237d38ceaf9SAlex Deucher * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled 238d38ceaf9SAlex Deucher * 239d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 240d38ceaf9SAlex Deucher * @seq: sequence number 241d38ceaf9SAlex Deucher * 242d38ceaf9SAlex Deucher * Check if the last signaled fence sequnce number is >= the requested 243d38ceaf9SAlex Deucher * sequence number (all asics). 244d38ceaf9SAlex Deucher * Returns true if the fence has signaled (current fence value 245d38ceaf9SAlex Deucher * is >= requested value) or false if it has not (current fence 246d38ceaf9SAlex Deucher * value is < the requested value. Helper function for 247d38ceaf9SAlex Deucher * amdgpu_fence_signaled(). 248d38ceaf9SAlex Deucher */ 249d38ceaf9SAlex Deucher static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq) 250d38ceaf9SAlex Deucher { 251d38ceaf9SAlex Deucher if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 252d38ceaf9SAlex Deucher return true; 253d38ceaf9SAlex Deucher 254d38ceaf9SAlex Deucher /* poll new last sequence at least once */ 255d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 256d38ceaf9SAlex Deucher if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 257d38ceaf9SAlex Deucher return true; 258d38ceaf9SAlex Deucher 259d38ceaf9SAlex Deucher return false; 260d38ceaf9SAlex Deucher } 261d38ceaf9SAlex Deucher 2627f06c236Smonk.liu /* 2637f06c236Smonk.liu * amdgpu_ring_wait_seq_timeout - wait for seq of the specific ring to signal 2647f06c236Smonk.liu * @ring: ring to wait on for the seq number 2657f06c236Smonk.liu * @seq: seq number wait for 266d38ceaf9SAlex Deucher * 2677f06c236Smonk.liu * return value: 26800d2a2b2SChristian König * 0: seq signaled, and gpu not hang 26900d2a2b2SChristian König * -EDEADL: GPU hang detected 2707f06c236Smonk.liu * -EINVAL: some paramter is not valid 271d38ceaf9SAlex Deucher */ 27200d2a2b2SChristian König static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) 273d38ceaf9SAlex Deucher { 2747f06c236Smonk.liu bool signaled = false; 275d38ceaf9SAlex Deucher 2767f06c236Smonk.liu BUG_ON(!ring); 2777f06c236Smonk.liu if (seq > ring->fence_drv.sync_seq[ring->idx]) 2787f06c236Smonk.liu return -EINVAL; 279d38ceaf9SAlex Deucher 2807f06c236Smonk.liu if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 281d38ceaf9SAlex Deucher return 0; 28200d2a2b2SChristian König 283c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 28400d2a2b2SChristian König wait_event(ring->fence_drv.fence_queue, ( 285b7e4dad3SChristian König (signaled = amdgpu_fence_seq_signaled(ring, seq)))); 28600d2a2b2SChristian König 28700d2a2b2SChristian König if (signaled) 28800d2a2b2SChristian König return 0; 28900d2a2b2SChristian König else 29000d2a2b2SChristian König return -EDEADLK; 291d38ceaf9SAlex Deucher } 2927f06c236Smonk.liu 293d38ceaf9SAlex Deucher /** 294d38ceaf9SAlex Deucher * amdgpu_fence_wait_next - wait for the next fence to signal 295d38ceaf9SAlex Deucher * 296d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 297d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 298d38ceaf9SAlex Deucher * 299d38ceaf9SAlex Deucher * Wait for the next fence on the requested ring to signal (all asics). 300d38ceaf9SAlex Deucher * Returns 0 if the next fence has passed, error for all other cases. 301d38ceaf9SAlex Deucher * Caller must hold ring lock. 302d38ceaf9SAlex Deucher */ 303d38ceaf9SAlex Deucher int amdgpu_fence_wait_next(struct amdgpu_ring *ring) 304d38ceaf9SAlex Deucher { 3057f06c236Smonk.liu uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL; 30600d2a2b2SChristian König 3077f06c236Smonk.liu if (seq >= ring->fence_drv.sync_seq[ring->idx]) 308d38ceaf9SAlex Deucher return -ENOENT; 3097f06c236Smonk.liu 31000d2a2b2SChristian König return amdgpu_fence_ring_wait_seq(ring, seq); 311d38ceaf9SAlex Deucher } 312d38ceaf9SAlex Deucher 313d38ceaf9SAlex Deucher /** 314d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 315d38ceaf9SAlex Deucher * 316d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 317d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 318d38ceaf9SAlex Deucher * 319d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 320d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 321d38ceaf9SAlex Deucher * Caller must hold ring lock. 322d38ceaf9SAlex Deucher */ 323d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 324d38ceaf9SAlex Deucher { 3257f06c236Smonk.liu uint64_t seq = ring->fence_drv.sync_seq[ring->idx]; 32600d2a2b2SChristian König 3277f06c236Smonk.liu if (!seq) 328d38ceaf9SAlex Deucher return 0; 329d38ceaf9SAlex Deucher 33000d2a2b2SChristian König return amdgpu_fence_ring_wait_seq(ring, seq); 331d38ceaf9SAlex Deucher } 332d38ceaf9SAlex Deucher 333d38ceaf9SAlex Deucher /** 334d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 335d38ceaf9SAlex Deucher * 336d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 337d38ceaf9SAlex Deucher * 338d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 339d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 340d38ceaf9SAlex Deucher * dynpm code to ring track activity. 341d38ceaf9SAlex Deucher */ 342d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 343d38ceaf9SAlex Deucher { 344d38ceaf9SAlex Deucher uint64_t emitted; 345d38ceaf9SAlex Deucher 346d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 347d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 348d38ceaf9SAlex Deucher */ 349d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 350d38ceaf9SAlex Deucher emitted = ring->fence_drv.sync_seq[ring->idx] 351d38ceaf9SAlex Deucher - atomic64_read(&ring->fence_drv.last_seq); 352d38ceaf9SAlex Deucher /* to avoid 32bits warp around */ 353d38ceaf9SAlex Deucher if (emitted > 0x10000000) 354d38ceaf9SAlex Deucher emitted = 0x10000000; 355d38ceaf9SAlex Deucher 356d38ceaf9SAlex Deucher return (unsigned)emitted; 357d38ceaf9SAlex Deucher } 358d38ceaf9SAlex Deucher 359d38ceaf9SAlex Deucher /** 360d38ceaf9SAlex Deucher * amdgpu_fence_need_sync - do we need a semaphore 361d38ceaf9SAlex Deucher * 362d38ceaf9SAlex Deucher * @fence: amdgpu fence object 363d38ceaf9SAlex Deucher * @dst_ring: which ring to check against 364d38ceaf9SAlex Deucher * 365d38ceaf9SAlex Deucher * Check if the fence needs to be synced against another ring 366d38ceaf9SAlex Deucher * (all asics). If so, we need to emit a semaphore. 367d38ceaf9SAlex Deucher * Returns true if we need to sync with another ring, false if 368d38ceaf9SAlex Deucher * not. 369d38ceaf9SAlex Deucher */ 370d38ceaf9SAlex Deucher bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 371d38ceaf9SAlex Deucher struct amdgpu_ring *dst_ring) 372d38ceaf9SAlex Deucher { 373d38ceaf9SAlex Deucher struct amdgpu_fence_driver *fdrv; 374d38ceaf9SAlex Deucher 375d38ceaf9SAlex Deucher if (!fence) 376d38ceaf9SAlex Deucher return false; 377d38ceaf9SAlex Deucher 378d38ceaf9SAlex Deucher if (fence->ring == dst_ring) 379d38ceaf9SAlex Deucher return false; 380d38ceaf9SAlex Deucher 381d38ceaf9SAlex Deucher /* we are protected by the ring mutex */ 382d38ceaf9SAlex Deucher fdrv = &dst_ring->fence_drv; 383d38ceaf9SAlex Deucher if (fence->seq <= fdrv->sync_seq[fence->ring->idx]) 384d38ceaf9SAlex Deucher return false; 385d38ceaf9SAlex Deucher 386d38ceaf9SAlex Deucher return true; 387d38ceaf9SAlex Deucher } 388d38ceaf9SAlex Deucher 389d38ceaf9SAlex Deucher /** 390d38ceaf9SAlex Deucher * amdgpu_fence_note_sync - record the sync point 391d38ceaf9SAlex Deucher * 392d38ceaf9SAlex Deucher * @fence: amdgpu fence object 393d38ceaf9SAlex Deucher * @dst_ring: which ring to check against 394d38ceaf9SAlex Deucher * 395d38ceaf9SAlex Deucher * Note the sequence number at which point the fence will 396d38ceaf9SAlex Deucher * be synced with the requested ring (all asics). 397d38ceaf9SAlex Deucher */ 398d38ceaf9SAlex Deucher void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 399d38ceaf9SAlex Deucher struct amdgpu_ring *dst_ring) 400d38ceaf9SAlex Deucher { 401d38ceaf9SAlex Deucher struct amdgpu_fence_driver *dst, *src; 402d38ceaf9SAlex Deucher unsigned i; 403d38ceaf9SAlex Deucher 404d38ceaf9SAlex Deucher if (!fence) 405d38ceaf9SAlex Deucher return; 406d38ceaf9SAlex Deucher 407d38ceaf9SAlex Deucher if (fence->ring == dst_ring) 408d38ceaf9SAlex Deucher return; 409d38ceaf9SAlex Deucher 410d38ceaf9SAlex Deucher /* we are protected by the ring mutex */ 411d38ceaf9SAlex Deucher src = &fence->ring->fence_drv; 412d38ceaf9SAlex Deucher dst = &dst_ring->fence_drv; 413d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 414d38ceaf9SAlex Deucher if (i == dst_ring->idx) 415d38ceaf9SAlex Deucher continue; 416d38ceaf9SAlex Deucher 417d38ceaf9SAlex Deucher dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]); 418d38ceaf9SAlex Deucher } 419d38ceaf9SAlex Deucher } 420d38ceaf9SAlex Deucher 421d38ceaf9SAlex Deucher /** 422d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 423d38ceaf9SAlex Deucher * ready for use on the requested ring. 424d38ceaf9SAlex Deucher * 425d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 426d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 427d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 428d38ceaf9SAlex Deucher * 429d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 430d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 431d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 432d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 433d38ceaf9SAlex Deucher */ 434d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 435d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 436d38ceaf9SAlex Deucher unsigned irq_type) 437d38ceaf9SAlex Deucher { 438d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 439d38ceaf9SAlex Deucher uint64_t index; 440d38ceaf9SAlex Deucher 441d38ceaf9SAlex Deucher if (ring != &adev->uvd.ring) { 442d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 443d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 444d38ceaf9SAlex Deucher } else { 445d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 446d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 447d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; 448d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; 449d38ceaf9SAlex Deucher } 450d38ceaf9SAlex Deucher amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq)); 451c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 452c6a4079bSChunming Zhou 453d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 454d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 455c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 456c6a4079bSChunming Zhou 457d38ceaf9SAlex Deucher dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " 458d38ceaf9SAlex Deucher "cpu addr 0x%p\n", ring->idx, 459d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 460d38ceaf9SAlex Deucher return 0; 461d38ceaf9SAlex Deucher } 462d38ceaf9SAlex Deucher 463d38ceaf9SAlex Deucher /** 464d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 465d38ceaf9SAlex Deucher * for the requested ring. 466d38ceaf9SAlex Deucher * 467d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 468d38ceaf9SAlex Deucher * 469d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 470d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 471d38ceaf9SAlex Deucher */ 4724f839a24SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) 473d38ceaf9SAlex Deucher { 4744f839a24SChristian König int i, r; 475cadf97b1SChunming Zhou long timeout; 476d38ceaf9SAlex Deucher 477d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 478d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 479d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) 480d38ceaf9SAlex Deucher ring->fence_drv.sync_seq[i] = 0; 481d38ceaf9SAlex Deucher 482d38ceaf9SAlex Deucher atomic64_set(&ring->fence_drv.last_seq, 0); 483d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 484d38ceaf9SAlex Deucher 485c2776afeSChristian König setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 486c2776afeSChristian König (unsigned long)ring); 487b80d8475SAlex Deucher 4885ec92a76SChristian König init_waitqueue_head(&ring->fence_drv.fence_queue); 4895ec92a76SChristian König 490cadf97b1SChunming Zhou timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 4912440ff2cSJunwei Zhang if (timeout == 0) { 4922440ff2cSJunwei Zhang /* 4932440ff2cSJunwei Zhang * FIXME: 4942440ff2cSJunwei Zhang * Delayed workqueue cannot use it directly, 4952440ff2cSJunwei Zhang * so the scheduler will not use delayed workqueue if 4962440ff2cSJunwei Zhang * MAX_SCHEDULE_TIMEOUT is set. 4972440ff2cSJunwei Zhang * Currently keep it simple and silly. 4982440ff2cSJunwei Zhang */ 4992440ff2cSJunwei Zhang timeout = MAX_SCHEDULE_TIMEOUT; 5002440ff2cSJunwei Zhang } 5014f839a24SChristian König r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 5022440ff2cSJunwei Zhang amdgpu_sched_hw_submission, 5032440ff2cSJunwei Zhang timeout, ring->name); 5044f839a24SChristian König if (r) { 5054f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 5064f839a24SChristian König ring->name); 5074f839a24SChristian König return r; 508b80d8475SAlex Deucher } 509d38ceaf9SAlex Deucher 5104f839a24SChristian König return 0; 5114f839a24SChristian König } 5124f839a24SChristian König 513d38ceaf9SAlex Deucher /** 514d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 515d38ceaf9SAlex Deucher * for all possible rings. 516d38ceaf9SAlex Deucher * 517d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 518d38ceaf9SAlex Deucher * 519d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 520d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 521d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 522d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 523d38ceaf9SAlex Deucher * Returns 0 for success. 524d38ceaf9SAlex Deucher */ 525d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 526d38ceaf9SAlex Deucher { 527b49c84a5SChunming Zhou if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) { 528b49c84a5SChunming Zhou amdgpu_fence_slab = kmem_cache_create( 529b49c84a5SChunming Zhou "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 530b49c84a5SChunming Zhou SLAB_HWCACHE_ALIGN, NULL); 531b49c84a5SChunming Zhou if (!amdgpu_fence_slab) 532b49c84a5SChunming Zhou return -ENOMEM; 533b49c84a5SChunming Zhou } 534d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 535d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 536d38ceaf9SAlex Deucher 537d38ceaf9SAlex Deucher return 0; 538d38ceaf9SAlex Deucher } 539d38ceaf9SAlex Deucher 540d38ceaf9SAlex Deucher /** 541d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 542d38ceaf9SAlex Deucher * for all possible rings. 543d38ceaf9SAlex Deucher * 544d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 545d38ceaf9SAlex Deucher * 546d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 547d38ceaf9SAlex Deucher */ 548d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 549d38ceaf9SAlex Deucher { 550d38ceaf9SAlex Deucher int i, r; 551d38ceaf9SAlex Deucher 552b49c84a5SChunming Zhou if (atomic_dec_and_test(&amdgpu_fence_slab_ref)) 553b49c84a5SChunming Zhou kmem_cache_destroy(amdgpu_fence_slab); 554d38ceaf9SAlex Deucher mutex_lock(&adev->ring_lock); 555d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 556d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 557c2776afeSChristian König 558d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 559d38ceaf9SAlex Deucher continue; 560d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 561d38ceaf9SAlex Deucher if (r) { 562d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 563d38ceaf9SAlex Deucher amdgpu_fence_driver_force_completion(adev); 564d38ceaf9SAlex Deucher } 5657f06c236Smonk.liu wake_up_all(&ring->fence_drv.fence_queue); 566c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 567c6a4079bSChunming Zhou ring->fence_drv.irq_type); 5684f839a24SChristian König amd_sched_fini(&ring->sched); 569c2776afeSChristian König del_timer_sync(&ring->fence_drv.fallback_timer); 570d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 571d38ceaf9SAlex Deucher } 572d38ceaf9SAlex Deucher mutex_unlock(&adev->ring_lock); 573d38ceaf9SAlex Deucher } 574d38ceaf9SAlex Deucher 575d38ceaf9SAlex Deucher /** 5765ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 5775ceb54c6SAlex Deucher * for all possible rings. 5785ceb54c6SAlex Deucher * 5795ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5805ceb54c6SAlex Deucher * 5815ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 5825ceb54c6SAlex Deucher */ 5835ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 5845ceb54c6SAlex Deucher { 5855ceb54c6SAlex Deucher int i, r; 5865ceb54c6SAlex Deucher 5875ceb54c6SAlex Deucher mutex_lock(&adev->ring_lock); 5885ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5895ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5905ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5915ceb54c6SAlex Deucher continue; 5925ceb54c6SAlex Deucher 5935ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 5945ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 5955ceb54c6SAlex Deucher if (r) { 5965ceb54c6SAlex Deucher /* delay GPU reset to resume */ 5975ceb54c6SAlex Deucher amdgpu_fence_driver_force_completion(adev); 5985ceb54c6SAlex Deucher } 5995ceb54c6SAlex Deucher 6005ceb54c6SAlex Deucher /* disable the interrupt */ 6015ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 6025ceb54c6SAlex Deucher ring->fence_drv.irq_type); 6035ceb54c6SAlex Deucher } 6045ceb54c6SAlex Deucher mutex_unlock(&adev->ring_lock); 6055ceb54c6SAlex Deucher } 6065ceb54c6SAlex Deucher 6075ceb54c6SAlex Deucher /** 6085ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 6095ceb54c6SAlex Deucher * for all possible rings. 6105ceb54c6SAlex Deucher * 6115ceb54c6SAlex Deucher * @adev: amdgpu device pointer 6125ceb54c6SAlex Deucher * 6135ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 6145ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 6155ceb54c6SAlex Deucher * start the fence driver on the rings it has using 6165ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 6175ceb54c6SAlex Deucher * Returns 0 for success. 6185ceb54c6SAlex Deucher */ 6195ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 6205ceb54c6SAlex Deucher { 6215ceb54c6SAlex Deucher int i; 6225ceb54c6SAlex Deucher 6235ceb54c6SAlex Deucher mutex_lock(&adev->ring_lock); 6245ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 6255ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 6265ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 6275ceb54c6SAlex Deucher continue; 6285ceb54c6SAlex Deucher 6295ceb54c6SAlex Deucher /* enable the interrupt */ 6305ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 6315ceb54c6SAlex Deucher ring->fence_drv.irq_type); 6325ceb54c6SAlex Deucher } 6335ceb54c6SAlex Deucher mutex_unlock(&adev->ring_lock); 6345ceb54c6SAlex Deucher } 6355ceb54c6SAlex Deucher 6365ceb54c6SAlex Deucher /** 637d38ceaf9SAlex Deucher * amdgpu_fence_driver_force_completion - force all fence waiter to complete 638d38ceaf9SAlex Deucher * 639d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 640d38ceaf9SAlex Deucher * 641d38ceaf9SAlex Deucher * In case of GPU reset failure make sure no process keep waiting on fence 642d38ceaf9SAlex Deucher * that will never complete. 643d38ceaf9SAlex Deucher */ 644d38ceaf9SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) 645d38ceaf9SAlex Deucher { 646d38ceaf9SAlex Deucher int i; 647d38ceaf9SAlex Deucher 648d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 649d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 650d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 651d38ceaf9SAlex Deucher continue; 652d38ceaf9SAlex Deucher 653d38ceaf9SAlex Deucher amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]); 654d38ceaf9SAlex Deucher } 655d38ceaf9SAlex Deucher } 656d38ceaf9SAlex Deucher 657a95e2642SChristian König /* 658a95e2642SChristian König * Common fence implementation 659a95e2642SChristian König */ 660a95e2642SChristian König 661a95e2642SChristian König static const char *amdgpu_fence_get_driver_name(struct fence *fence) 662a95e2642SChristian König { 663a95e2642SChristian König return "amdgpu"; 664a95e2642SChristian König } 665a95e2642SChristian König 666a95e2642SChristian König static const char *amdgpu_fence_get_timeline_name(struct fence *f) 667a95e2642SChristian König { 668a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 669a95e2642SChristian König return (const char *)fence->ring->name; 670a95e2642SChristian König } 671a95e2642SChristian König 672a95e2642SChristian König /** 673a95e2642SChristian König * amdgpu_fence_is_signaled - test if fence is signaled 674a95e2642SChristian König * 675a95e2642SChristian König * @f: fence to test 676a95e2642SChristian König * 677a95e2642SChristian König * Test the fence sequence number if it is already signaled. If it isn't 678a95e2642SChristian König * signaled start fence processing. Returns True if the fence is signaled. 679a95e2642SChristian König */ 680a95e2642SChristian König static bool amdgpu_fence_is_signaled(struct fence *f) 681a95e2642SChristian König { 682a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 683a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 684a95e2642SChristian König 685a95e2642SChristian König if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 686a95e2642SChristian König return true; 687a95e2642SChristian König 688a95e2642SChristian König amdgpu_fence_process(ring); 689a95e2642SChristian König 690a95e2642SChristian König if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 691a95e2642SChristian König return true; 692a95e2642SChristian König 693a95e2642SChristian König return false; 694a95e2642SChristian König } 695a95e2642SChristian König 696a95e2642SChristian König /** 697a95e2642SChristian König * amdgpu_fence_check_signaled - callback from fence_queue 698a95e2642SChristian König * 699a95e2642SChristian König * this function is called with fence_queue lock held, which is also used 700a95e2642SChristian König * for the fence locking itself, so unlocked variants are used for 701a95e2642SChristian König * fence_signal, and remove_wait_queue. 702a95e2642SChristian König */ 703a95e2642SChristian König static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key) 704a95e2642SChristian König { 705a95e2642SChristian König struct amdgpu_fence *fence; 706a95e2642SChristian König struct amdgpu_device *adev; 707a95e2642SChristian König u64 seq; 708a95e2642SChristian König int ret; 709a95e2642SChristian König 710a95e2642SChristian König fence = container_of(wait, struct amdgpu_fence, fence_wake); 711a95e2642SChristian König adev = fence->ring->adev; 712a95e2642SChristian König 713a95e2642SChristian König /* 714a95e2642SChristian König * We cannot use amdgpu_fence_process here because we're already 715a95e2642SChristian König * in the waitqueue, in a call from wake_up_all. 716a95e2642SChristian König */ 717a95e2642SChristian König seq = atomic64_read(&fence->ring->fence_drv.last_seq); 718a95e2642SChristian König if (seq >= fence->seq) { 719a95e2642SChristian König ret = fence_signal_locked(&fence->base); 720a95e2642SChristian König if (!ret) 721a95e2642SChristian König FENCE_TRACE(&fence->base, "signaled from irq context\n"); 722a95e2642SChristian König else 723a95e2642SChristian König FENCE_TRACE(&fence->base, "was already signaled\n"); 724a95e2642SChristian König 725a95e2642SChristian König __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake); 726a95e2642SChristian König fence_put(&fence->base); 727a95e2642SChristian König } else 728a95e2642SChristian König FENCE_TRACE(&fence->base, "pending\n"); 729a95e2642SChristian König return 0; 730a95e2642SChristian König } 731a95e2642SChristian König 732a95e2642SChristian König /** 733a95e2642SChristian König * amdgpu_fence_enable_signaling - enable signalling on fence 734a95e2642SChristian König * @fence: fence 735a95e2642SChristian König * 736a95e2642SChristian König * This function is called with fence_queue lock held, and adds a callback 737a95e2642SChristian König * to fence_queue that checks if this fence is signaled, and if so it 738a95e2642SChristian König * signals the fence and removes itself. 739a95e2642SChristian König */ 740a95e2642SChristian König static bool amdgpu_fence_enable_signaling(struct fence *f) 741a95e2642SChristian König { 742a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 743a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 744a95e2642SChristian König 745a95e2642SChristian König if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 746a95e2642SChristian König return false; 747a95e2642SChristian König 748a95e2642SChristian König fence->fence_wake.flags = 0; 749a95e2642SChristian König fence->fence_wake.private = NULL; 750a95e2642SChristian König fence->fence_wake.func = amdgpu_fence_check_signaled; 751a95e2642SChristian König __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake); 752a95e2642SChristian König fence_get(f); 753c2776afeSChristian König if (!timer_pending(&ring->fence_drv.fallback_timer)) 754c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 755a95e2642SChristian König FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 756a95e2642SChristian König return true; 757a95e2642SChristian König } 758a95e2642SChristian König 759b49c84a5SChunming Zhou static void amdgpu_fence_release(struct fence *f) 760b49c84a5SChunming Zhou { 761b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 762b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 763b49c84a5SChunming Zhou } 764b49c84a5SChunming Zhou 765a95e2642SChristian König const struct fence_ops amdgpu_fence_ops = { 766a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 767a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 768a95e2642SChristian König .enable_signaling = amdgpu_fence_enable_signaling, 769a95e2642SChristian König .signaled = amdgpu_fence_is_signaled, 770a95e2642SChristian König .wait = fence_default_wait, 771b49c84a5SChunming Zhou .release = amdgpu_fence_release, 772a95e2642SChristian König }; 773d38ceaf9SAlex Deucher 774d38ceaf9SAlex Deucher /* 775d38ceaf9SAlex Deucher * Fence debugfs 776d38ceaf9SAlex Deucher */ 777d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 778d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 779d38ceaf9SAlex Deucher { 780d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 781d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 782d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 783d38ceaf9SAlex Deucher int i, j; 784d38ceaf9SAlex Deucher 785d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 786d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 787d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 788d38ceaf9SAlex Deucher continue; 789d38ceaf9SAlex Deucher 790d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 791d38ceaf9SAlex Deucher 792344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 793d38ceaf9SAlex Deucher seq_printf(m, "Last signaled fence 0x%016llx\n", 794d38ceaf9SAlex Deucher (unsigned long long)atomic64_read(&ring->fence_drv.last_seq)); 795d38ceaf9SAlex Deucher seq_printf(m, "Last emitted 0x%016llx\n", 796d38ceaf9SAlex Deucher ring->fence_drv.sync_seq[i]); 797d38ceaf9SAlex Deucher 798d38ceaf9SAlex Deucher for (j = 0; j < AMDGPU_MAX_RINGS; ++j) { 799d38ceaf9SAlex Deucher struct amdgpu_ring *other = adev->rings[j]; 800344c19f9SChristian König if (i != j && other && other->fence_drv.initialized && 801344c19f9SChristian König ring->fence_drv.sync_seq[j]) 802d38ceaf9SAlex Deucher seq_printf(m, "Last sync to ring %d 0x%016llx\n", 803d38ceaf9SAlex Deucher j, ring->fence_drv.sync_seq[j]); 804d38ceaf9SAlex Deucher } 805d38ceaf9SAlex Deucher } 806d38ceaf9SAlex Deucher return 0; 807d38ceaf9SAlex Deucher } 808d38ceaf9SAlex Deucher 809d38ceaf9SAlex Deucher static struct drm_info_list amdgpu_debugfs_fence_list[] = { 810d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 811d38ceaf9SAlex Deucher }; 812d38ceaf9SAlex Deucher #endif 813d38ceaf9SAlex Deucher 814d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 815d38ceaf9SAlex Deucher { 816d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 817d38ceaf9SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1); 818d38ceaf9SAlex Deucher #else 819d38ceaf9SAlex Deucher return 0; 820d38ceaf9SAlex Deucher #endif 821d38ceaf9SAlex Deucher } 822d38ceaf9SAlex Deucher 823