1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 5022e5a2f4SChristian König struct amdgpu_fence { 5122e5a2f4SChristian König struct fence base; 5222e5a2f4SChristian König 5322e5a2f4SChristian König /* RB, DMA, etc. */ 5422e5a2f4SChristian König struct amdgpu_ring *ring; 5522e5a2f4SChristian König uint64_t seq; 5622e5a2f4SChristian König 5722e5a2f4SChristian König wait_queue_t fence_wake; 5822e5a2f4SChristian König }; 5922e5a2f4SChristian König 60b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 61b49c84a5SChunming Zhou static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0); 62b49c84a5SChunming Zhou 6322e5a2f4SChristian König /* 6422e5a2f4SChristian König * Cast helper 6522e5a2f4SChristian König */ 6622e5a2f4SChristian König static const struct fence_ops amdgpu_fence_ops; 6722e5a2f4SChristian König static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 6822e5a2f4SChristian König { 6922e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 7022e5a2f4SChristian König 7122e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 7222e5a2f4SChristian König return __f; 7322e5a2f4SChristian König 7422e5a2f4SChristian König return NULL; 7522e5a2f4SChristian König } 7622e5a2f4SChristian König 77d38ceaf9SAlex Deucher /** 78d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 79d38ceaf9SAlex Deucher * 80d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 81d38ceaf9SAlex Deucher * @seq: sequence number to write 82d38ceaf9SAlex Deucher * 83d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 84d38ceaf9SAlex Deucher */ 85d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 86d38ceaf9SAlex Deucher { 87d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 88d38ceaf9SAlex Deucher 89d38ceaf9SAlex Deucher if (drv->cpu_addr) 90d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 91d38ceaf9SAlex Deucher } 92d38ceaf9SAlex Deucher 93d38ceaf9SAlex Deucher /** 94d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 95d38ceaf9SAlex Deucher * 96d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 97d38ceaf9SAlex Deucher * 98d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 99d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 100d38ceaf9SAlex Deucher */ 101d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 102d38ceaf9SAlex Deucher { 103d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 104d38ceaf9SAlex Deucher u32 seq = 0; 105d38ceaf9SAlex Deucher 106d38ceaf9SAlex Deucher if (drv->cpu_addr) 107d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 108d38ceaf9SAlex Deucher else 109d38ceaf9SAlex Deucher seq = lower_32_bits(atomic64_read(&drv->last_seq)); 110d38ceaf9SAlex Deucher 111d38ceaf9SAlex Deucher return seq; 112d38ceaf9SAlex Deucher } 113d38ceaf9SAlex Deucher 114d38ceaf9SAlex Deucher /** 115d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 116d38ceaf9SAlex Deucher * 117d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 118364beb2cSChristian König * @f: resulting fence object 119d38ceaf9SAlex Deucher * 120d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 121d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 122d38ceaf9SAlex Deucher */ 123364beb2cSChristian König int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f) 124d38ceaf9SAlex Deucher { 125d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 126364beb2cSChristian König struct amdgpu_fence *fence; 127d38ceaf9SAlex Deucher 128364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 129364beb2cSChristian König if (fence == NULL) 130d38ceaf9SAlex Deucher return -ENOMEM; 131364beb2cSChristian König 132364beb2cSChristian König fence->seq = ++ring->fence_drv.sync_seq; 133364beb2cSChristian König fence->ring = ring; 134364beb2cSChristian König fence_init(&fence->base, &amdgpu_fence_ops, 1357f06c236Smonk.liu &ring->fence_drv.fence_queue.lock, 1367f06c236Smonk.liu adev->fence_context + ring->idx, 137364beb2cSChristian König fence->seq); 138890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 139364beb2cSChristian König fence->seq, AMDGPU_FENCE_FLAG_INT); 140364beb2cSChristian König *f = &fence->base; 141d38ceaf9SAlex Deucher return 0; 142d38ceaf9SAlex Deucher } 143d38ceaf9SAlex Deucher 144d38ceaf9SAlex Deucher /** 145c2776afeSChristian König * amdgpu_fence_schedule_fallback - schedule fallback check 146c2776afeSChristian König * 147c2776afeSChristian König * @ring: pointer to struct amdgpu_ring 148c2776afeSChristian König * 149c2776afeSChristian König * Start a timer as fallback to our interrupts. 150c2776afeSChristian König */ 151c2776afeSChristian König static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 152c2776afeSChristian König { 153c2776afeSChristian König mod_timer(&ring->fence_drv.fallback_timer, 154c2776afeSChristian König jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 155c2776afeSChristian König } 156c2776afeSChristian König 157c2776afeSChristian König /** 158ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 159d38ceaf9SAlex Deucher * 160d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 161d38ceaf9SAlex Deucher * 162d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 163ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 164ca08e04dSChristian König * sequence number has increased. 165d38ceaf9SAlex Deucher */ 166ca08e04dSChristian König void amdgpu_fence_process(struct amdgpu_ring *ring) 167d38ceaf9SAlex Deucher { 168d38ceaf9SAlex Deucher uint64_t seq, last_seq, last_emitted; 169d38ceaf9SAlex Deucher bool wake = false; 170d38ceaf9SAlex Deucher 171d38ceaf9SAlex Deucher last_seq = atomic64_read(&ring->fence_drv.last_seq); 172d38ceaf9SAlex Deucher do { 1735907a0d8SChristian König last_emitted = ring->fence_drv.sync_seq; 174d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 175d38ceaf9SAlex Deucher seq |= last_seq & 0xffffffff00000000LL; 176d38ceaf9SAlex Deucher if (seq < last_seq) { 177d38ceaf9SAlex Deucher seq &= 0xffffffff; 178d38ceaf9SAlex Deucher seq |= last_emitted & 0xffffffff00000000LL; 179d38ceaf9SAlex Deucher } 180d38ceaf9SAlex Deucher 181d9713ef6SChristian König if (seq <= last_seq || seq > last_emitted) 182d38ceaf9SAlex Deucher break; 183d9713ef6SChristian König 184d38ceaf9SAlex Deucher /* If we loop over we don't want to return without 185d38ceaf9SAlex Deucher * checking if a fence is signaled as it means that the 186d38ceaf9SAlex Deucher * seq we just read is different from the previous on. 187d38ceaf9SAlex Deucher */ 188d38ceaf9SAlex Deucher wake = true; 189d38ceaf9SAlex Deucher last_seq = seq; 190d9713ef6SChristian König 191d38ceaf9SAlex Deucher } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq); 192d38ceaf9SAlex Deucher 193d38ceaf9SAlex Deucher if (seq < last_emitted) 194c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 195d38ceaf9SAlex Deucher 196ca08e04dSChristian König if (wake) 1977f06c236Smonk.liu wake_up_all(&ring->fence_drv.fence_queue); 198e0d8f3c3SChunming Zhou } 199d38ceaf9SAlex Deucher 200d38ceaf9SAlex Deucher /** 201c2776afeSChristian König * amdgpu_fence_fallback - fallback for hardware interrupts 202c2776afeSChristian König * 203c2776afeSChristian König * @work: delayed work item 204c2776afeSChristian König * 205c2776afeSChristian König * Checks for fence activity. 206c2776afeSChristian König */ 207c2776afeSChristian König static void amdgpu_fence_fallback(unsigned long arg) 208c2776afeSChristian König { 209c2776afeSChristian König struct amdgpu_ring *ring = (void *)arg; 210c2776afeSChristian König 211c2776afeSChristian König amdgpu_fence_process(ring); 212c2776afeSChristian König } 213c2776afeSChristian König 214c2776afeSChristian König /** 215d38ceaf9SAlex Deucher * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled 216d38ceaf9SAlex Deucher * 217d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 218d38ceaf9SAlex Deucher * @seq: sequence number 219d38ceaf9SAlex Deucher * 220d38ceaf9SAlex Deucher * Check if the last signaled fence sequnce number is >= the requested 221d38ceaf9SAlex Deucher * sequence number (all asics). 222d38ceaf9SAlex Deucher * Returns true if the fence has signaled (current fence value 223d38ceaf9SAlex Deucher * is >= requested value) or false if it has not (current fence 224d38ceaf9SAlex Deucher * value is < the requested value. Helper function for 225d38ceaf9SAlex Deucher * amdgpu_fence_signaled(). 226d38ceaf9SAlex Deucher */ 227d38ceaf9SAlex Deucher static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq) 228d38ceaf9SAlex Deucher { 229d38ceaf9SAlex Deucher if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 230d38ceaf9SAlex Deucher return true; 231d38ceaf9SAlex Deucher 232d38ceaf9SAlex Deucher /* poll new last sequence at least once */ 233d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 234d38ceaf9SAlex Deucher if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 235d38ceaf9SAlex Deucher return true; 236d38ceaf9SAlex Deucher 237d38ceaf9SAlex Deucher return false; 238d38ceaf9SAlex Deucher } 239d38ceaf9SAlex Deucher 2407f06c236Smonk.liu /* 2419b389668SChristian König * amdgpu_ring_wait_seq - wait for seq of the specific ring to signal 2427f06c236Smonk.liu * @ring: ring to wait on for the seq number 2437f06c236Smonk.liu * @seq: seq number wait for 244d38ceaf9SAlex Deucher * 2457f06c236Smonk.liu * return value: 24600d2a2b2SChristian König * 0: seq signaled, and gpu not hang 2477f06c236Smonk.liu * -EINVAL: some paramter is not valid 248d38ceaf9SAlex Deucher */ 24900d2a2b2SChristian König static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) 250d38ceaf9SAlex Deucher { 2517f06c236Smonk.liu BUG_ON(!ring); 2525907a0d8SChristian König if (seq > ring->fence_drv.sync_seq) 2537f06c236Smonk.liu return -EINVAL; 254d38ceaf9SAlex Deucher 2557f06c236Smonk.liu if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 256d38ceaf9SAlex Deucher return 0; 25700d2a2b2SChristian König 258c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 2599b389668SChristian König wait_event(ring->fence_drv.fence_queue, 2609b389668SChristian König amdgpu_fence_seq_signaled(ring, seq)); 26100d2a2b2SChristian König 26200d2a2b2SChristian König return 0; 263d38ceaf9SAlex Deucher } 2647f06c236Smonk.liu 265d38ceaf9SAlex Deucher /** 266d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 267d38ceaf9SAlex Deucher * 268d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 269d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 270d38ceaf9SAlex Deucher * 271d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 272d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 273d38ceaf9SAlex Deucher * Caller must hold ring lock. 274d38ceaf9SAlex Deucher */ 275d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 276d38ceaf9SAlex Deucher { 2775907a0d8SChristian König uint64_t seq = ring->fence_drv.sync_seq; 27800d2a2b2SChristian König 2797f06c236Smonk.liu if (!seq) 280d38ceaf9SAlex Deucher return 0; 281d38ceaf9SAlex Deucher 28200d2a2b2SChristian König return amdgpu_fence_ring_wait_seq(ring, seq); 283d38ceaf9SAlex Deucher } 284d38ceaf9SAlex Deucher 285d38ceaf9SAlex Deucher /** 286d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 287d38ceaf9SAlex Deucher * 288d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 289d38ceaf9SAlex Deucher * 290d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 291d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 292d38ceaf9SAlex Deucher * dynpm code to ring track activity. 293d38ceaf9SAlex Deucher */ 294d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 295d38ceaf9SAlex Deucher { 296d38ceaf9SAlex Deucher uint64_t emitted; 297d38ceaf9SAlex Deucher 298d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 299d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 300d38ceaf9SAlex Deucher */ 301d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 3025907a0d8SChristian König emitted = ring->fence_drv.sync_seq 303d38ceaf9SAlex Deucher - atomic64_read(&ring->fence_drv.last_seq); 304d38ceaf9SAlex Deucher /* to avoid 32bits warp around */ 305d38ceaf9SAlex Deucher if (emitted > 0x10000000) 306d38ceaf9SAlex Deucher emitted = 0x10000000; 307d38ceaf9SAlex Deucher 308d38ceaf9SAlex Deucher return (unsigned)emitted; 309d38ceaf9SAlex Deucher } 310d38ceaf9SAlex Deucher 311d38ceaf9SAlex Deucher /** 312d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 313d38ceaf9SAlex Deucher * ready for use on the requested ring. 314d38ceaf9SAlex Deucher * 315d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 316d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 317d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 318d38ceaf9SAlex Deucher * 319d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 320d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 321d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 322d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 323d38ceaf9SAlex Deucher */ 324d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 325d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 326d38ceaf9SAlex Deucher unsigned irq_type) 327d38ceaf9SAlex Deucher { 328d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 329d38ceaf9SAlex Deucher uint64_t index; 330d38ceaf9SAlex Deucher 331d38ceaf9SAlex Deucher if (ring != &adev->uvd.ring) { 332d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 333d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 334d38ceaf9SAlex Deucher } else { 335d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 336d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 337d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; 338d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; 339d38ceaf9SAlex Deucher } 340d38ceaf9SAlex Deucher amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq)); 341c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 342c6a4079bSChunming Zhou 343d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 344d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 345c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 346c6a4079bSChunming Zhou 347d38ceaf9SAlex Deucher dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " 348d38ceaf9SAlex Deucher "cpu addr 0x%p\n", ring->idx, 349d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 350d38ceaf9SAlex Deucher return 0; 351d38ceaf9SAlex Deucher } 352d38ceaf9SAlex Deucher 353d38ceaf9SAlex Deucher /** 354d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 355d38ceaf9SAlex Deucher * for the requested ring. 356d38ceaf9SAlex Deucher * 357d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 358d38ceaf9SAlex Deucher * 359d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 360d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 361d38ceaf9SAlex Deucher */ 3624f839a24SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) 363d38ceaf9SAlex Deucher { 364cadf97b1SChunming Zhou long timeout; 3655907a0d8SChristian König int r; 366d38ceaf9SAlex Deucher 367d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 368d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 3695907a0d8SChristian König ring->fence_drv.sync_seq = 0; 370d38ceaf9SAlex Deucher atomic64_set(&ring->fence_drv.last_seq, 0); 371d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 372d38ceaf9SAlex Deucher 373c2776afeSChristian König setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 374c2776afeSChristian König (unsigned long)ring); 375b80d8475SAlex Deucher 3765ec92a76SChristian König init_waitqueue_head(&ring->fence_drv.fence_queue); 3775ec92a76SChristian König 378cadf97b1SChunming Zhou timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 3792440ff2cSJunwei Zhang if (timeout == 0) { 3802440ff2cSJunwei Zhang /* 3812440ff2cSJunwei Zhang * FIXME: 3822440ff2cSJunwei Zhang * Delayed workqueue cannot use it directly, 3832440ff2cSJunwei Zhang * so the scheduler will not use delayed workqueue if 3842440ff2cSJunwei Zhang * MAX_SCHEDULE_TIMEOUT is set. 3852440ff2cSJunwei Zhang * Currently keep it simple and silly. 3862440ff2cSJunwei Zhang */ 3872440ff2cSJunwei Zhang timeout = MAX_SCHEDULE_TIMEOUT; 3882440ff2cSJunwei Zhang } 3894f839a24SChristian König r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 3902440ff2cSJunwei Zhang amdgpu_sched_hw_submission, 3912440ff2cSJunwei Zhang timeout, ring->name); 3924f839a24SChristian König if (r) { 3934f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 3944f839a24SChristian König ring->name); 3954f839a24SChristian König return r; 396b80d8475SAlex Deucher } 397d38ceaf9SAlex Deucher 3984f839a24SChristian König return 0; 3994f839a24SChristian König } 4004f839a24SChristian König 401d38ceaf9SAlex Deucher /** 402d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 403d38ceaf9SAlex Deucher * for all possible rings. 404d38ceaf9SAlex Deucher * 405d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 406d38ceaf9SAlex Deucher * 407d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 408d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 409d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 410d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 411d38ceaf9SAlex Deucher * Returns 0 for success. 412d38ceaf9SAlex Deucher */ 413d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 414d38ceaf9SAlex Deucher { 415b49c84a5SChunming Zhou if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) { 416b49c84a5SChunming Zhou amdgpu_fence_slab = kmem_cache_create( 417b49c84a5SChunming Zhou "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 418b49c84a5SChunming Zhou SLAB_HWCACHE_ALIGN, NULL); 419b49c84a5SChunming Zhou if (!amdgpu_fence_slab) 420b49c84a5SChunming Zhou return -ENOMEM; 421b49c84a5SChunming Zhou } 422d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 423d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 424d38ceaf9SAlex Deucher 425d38ceaf9SAlex Deucher return 0; 426d38ceaf9SAlex Deucher } 427d38ceaf9SAlex Deucher 428d38ceaf9SAlex Deucher /** 429d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 430d38ceaf9SAlex Deucher * for all possible rings. 431d38ceaf9SAlex Deucher * 432d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 433d38ceaf9SAlex Deucher * 434d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 435d38ceaf9SAlex Deucher */ 436d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 437d38ceaf9SAlex Deucher { 438d38ceaf9SAlex Deucher int i, r; 439d38ceaf9SAlex Deucher 440b49c84a5SChunming Zhou if (atomic_dec_and_test(&amdgpu_fence_slab_ref)) 441b49c84a5SChunming Zhou kmem_cache_destroy(amdgpu_fence_slab); 442d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 443d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 444c2776afeSChristian König 445d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 446d38ceaf9SAlex Deucher continue; 447d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 448d38ceaf9SAlex Deucher if (r) { 449d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 450d38ceaf9SAlex Deucher amdgpu_fence_driver_force_completion(adev); 451d38ceaf9SAlex Deucher } 4527f06c236Smonk.liu wake_up_all(&ring->fence_drv.fence_queue); 453c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 454c6a4079bSChunming Zhou ring->fence_drv.irq_type); 4554f839a24SChristian König amd_sched_fini(&ring->sched); 456c2776afeSChristian König del_timer_sync(&ring->fence_drv.fallback_timer); 457d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 458d38ceaf9SAlex Deucher } 459d38ceaf9SAlex Deucher } 460d38ceaf9SAlex Deucher 461d38ceaf9SAlex Deucher /** 4625ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 4635ceb54c6SAlex Deucher * for all possible rings. 4645ceb54c6SAlex Deucher * 4655ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4665ceb54c6SAlex Deucher * 4675ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 4685ceb54c6SAlex Deucher */ 4695ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 4705ceb54c6SAlex Deucher { 4715ceb54c6SAlex Deucher int i, r; 4725ceb54c6SAlex Deucher 4735ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 4745ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 4755ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 4765ceb54c6SAlex Deucher continue; 4775ceb54c6SAlex Deucher 4785ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 4795ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 4805ceb54c6SAlex Deucher if (r) { 4815ceb54c6SAlex Deucher /* delay GPU reset to resume */ 4825ceb54c6SAlex Deucher amdgpu_fence_driver_force_completion(adev); 4835ceb54c6SAlex Deucher } 4845ceb54c6SAlex Deucher 4855ceb54c6SAlex Deucher /* disable the interrupt */ 4865ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 4875ceb54c6SAlex Deucher ring->fence_drv.irq_type); 4885ceb54c6SAlex Deucher } 4895ceb54c6SAlex Deucher } 4905ceb54c6SAlex Deucher 4915ceb54c6SAlex Deucher /** 4925ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 4935ceb54c6SAlex Deucher * for all possible rings. 4945ceb54c6SAlex Deucher * 4955ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4965ceb54c6SAlex Deucher * 4975ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 4985ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 4995ceb54c6SAlex Deucher * start the fence driver on the rings it has using 5005ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 5015ceb54c6SAlex Deucher * Returns 0 for success. 5025ceb54c6SAlex Deucher */ 5035ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 5045ceb54c6SAlex Deucher { 5055ceb54c6SAlex Deucher int i; 5065ceb54c6SAlex Deucher 5075ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5085ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5095ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5105ceb54c6SAlex Deucher continue; 5115ceb54c6SAlex Deucher 5125ceb54c6SAlex Deucher /* enable the interrupt */ 5135ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 5145ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5155ceb54c6SAlex Deucher } 5165ceb54c6SAlex Deucher } 5175ceb54c6SAlex Deucher 5185ceb54c6SAlex Deucher /** 519d38ceaf9SAlex Deucher * amdgpu_fence_driver_force_completion - force all fence waiter to complete 520d38ceaf9SAlex Deucher * 521d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 522d38ceaf9SAlex Deucher * 523d38ceaf9SAlex Deucher * In case of GPU reset failure make sure no process keep waiting on fence 524d38ceaf9SAlex Deucher * that will never complete. 525d38ceaf9SAlex Deucher */ 526d38ceaf9SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) 527d38ceaf9SAlex Deucher { 528d38ceaf9SAlex Deucher int i; 529d38ceaf9SAlex Deucher 530d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 531d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 532d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 533d38ceaf9SAlex Deucher continue; 534d38ceaf9SAlex Deucher 5355907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 536d38ceaf9SAlex Deucher } 537d38ceaf9SAlex Deucher } 538d38ceaf9SAlex Deucher 539a95e2642SChristian König /* 540a95e2642SChristian König * Common fence implementation 541a95e2642SChristian König */ 542a95e2642SChristian König 543a95e2642SChristian König static const char *amdgpu_fence_get_driver_name(struct fence *fence) 544a95e2642SChristian König { 545a95e2642SChristian König return "amdgpu"; 546a95e2642SChristian König } 547a95e2642SChristian König 548a95e2642SChristian König static const char *amdgpu_fence_get_timeline_name(struct fence *f) 549a95e2642SChristian König { 550a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 551a95e2642SChristian König return (const char *)fence->ring->name; 552a95e2642SChristian König } 553a95e2642SChristian König 554a95e2642SChristian König /** 555a95e2642SChristian König * amdgpu_fence_is_signaled - test if fence is signaled 556a95e2642SChristian König * 557a95e2642SChristian König * @f: fence to test 558a95e2642SChristian König * 559a95e2642SChristian König * Test the fence sequence number if it is already signaled. If it isn't 560a95e2642SChristian König * signaled start fence processing. Returns True if the fence is signaled. 561a95e2642SChristian König */ 562a95e2642SChristian König static bool amdgpu_fence_is_signaled(struct fence *f) 563a95e2642SChristian König { 564a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 565a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 566a95e2642SChristian König 567a95e2642SChristian König if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 568a95e2642SChristian König return true; 569a95e2642SChristian König 570a95e2642SChristian König amdgpu_fence_process(ring); 571a95e2642SChristian König 572a95e2642SChristian König if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 573a95e2642SChristian König return true; 574a95e2642SChristian König 575a95e2642SChristian König return false; 576a95e2642SChristian König } 577a95e2642SChristian König 578a95e2642SChristian König /** 579a95e2642SChristian König * amdgpu_fence_check_signaled - callback from fence_queue 580a95e2642SChristian König * 581a95e2642SChristian König * this function is called with fence_queue lock held, which is also used 582a95e2642SChristian König * for the fence locking itself, so unlocked variants are used for 583a95e2642SChristian König * fence_signal, and remove_wait_queue. 584a95e2642SChristian König */ 585a95e2642SChristian König static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key) 586a95e2642SChristian König { 587a95e2642SChristian König struct amdgpu_fence *fence; 588a95e2642SChristian König struct amdgpu_device *adev; 589a95e2642SChristian König u64 seq; 590a95e2642SChristian König int ret; 591a95e2642SChristian König 592a95e2642SChristian König fence = container_of(wait, struct amdgpu_fence, fence_wake); 593a95e2642SChristian König adev = fence->ring->adev; 594a95e2642SChristian König 595a95e2642SChristian König /* 596a95e2642SChristian König * We cannot use amdgpu_fence_process here because we're already 597a95e2642SChristian König * in the waitqueue, in a call from wake_up_all. 598a95e2642SChristian König */ 599a95e2642SChristian König seq = atomic64_read(&fence->ring->fence_drv.last_seq); 600a95e2642SChristian König if (seq >= fence->seq) { 601a95e2642SChristian König ret = fence_signal_locked(&fence->base); 602a95e2642SChristian König if (!ret) 603a95e2642SChristian König FENCE_TRACE(&fence->base, "signaled from irq context\n"); 604a95e2642SChristian König else 605a95e2642SChristian König FENCE_TRACE(&fence->base, "was already signaled\n"); 606a95e2642SChristian König 607a95e2642SChristian König __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake); 608a95e2642SChristian König fence_put(&fence->base); 609a95e2642SChristian König } else 610a95e2642SChristian König FENCE_TRACE(&fence->base, "pending\n"); 611a95e2642SChristian König return 0; 612a95e2642SChristian König } 613a95e2642SChristian König 614a95e2642SChristian König /** 615a95e2642SChristian König * amdgpu_fence_enable_signaling - enable signalling on fence 616a95e2642SChristian König * @fence: fence 617a95e2642SChristian König * 618a95e2642SChristian König * This function is called with fence_queue lock held, and adds a callback 619a95e2642SChristian König * to fence_queue that checks if this fence is signaled, and if so it 620a95e2642SChristian König * signals the fence and removes itself. 621a95e2642SChristian König */ 622a95e2642SChristian König static bool amdgpu_fence_enable_signaling(struct fence *f) 623a95e2642SChristian König { 624a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 625a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 626a95e2642SChristian König 627a95e2642SChristian König if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) 628a95e2642SChristian König return false; 629a95e2642SChristian König 630a95e2642SChristian König fence->fence_wake.flags = 0; 631a95e2642SChristian König fence->fence_wake.private = NULL; 632a95e2642SChristian König fence->fence_wake.func = amdgpu_fence_check_signaled; 633a95e2642SChristian König __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake); 634a95e2642SChristian König fence_get(f); 635c2776afeSChristian König if (!timer_pending(&ring->fence_drv.fallback_timer)) 636c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 637a95e2642SChristian König FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 638a95e2642SChristian König return true; 639a95e2642SChristian König } 640a95e2642SChristian König 641b49c84a5SChunming Zhou static void amdgpu_fence_release(struct fence *f) 642b49c84a5SChunming Zhou { 643b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 644b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 645b49c84a5SChunming Zhou } 646b49c84a5SChunming Zhou 64722e5a2f4SChristian König static const struct fence_ops amdgpu_fence_ops = { 648a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 649a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 650a95e2642SChristian König .enable_signaling = amdgpu_fence_enable_signaling, 651a95e2642SChristian König .signaled = amdgpu_fence_is_signaled, 652a95e2642SChristian König .wait = fence_default_wait, 653b49c84a5SChunming Zhou .release = amdgpu_fence_release, 654a95e2642SChristian König }; 655d38ceaf9SAlex Deucher 656d38ceaf9SAlex Deucher /* 657d38ceaf9SAlex Deucher * Fence debugfs 658d38ceaf9SAlex Deucher */ 659d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 660d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 661d38ceaf9SAlex Deucher { 662d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 663d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 664d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 6655907a0d8SChristian König int i; 666d38ceaf9SAlex Deucher 667d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 668d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 669d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 670d38ceaf9SAlex Deucher continue; 671d38ceaf9SAlex Deucher 672d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 673d38ceaf9SAlex Deucher 674344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 675d38ceaf9SAlex Deucher seq_printf(m, "Last signaled fence 0x%016llx\n", 676d38ceaf9SAlex Deucher (unsigned long long)atomic64_read(&ring->fence_drv.last_seq)); 677d38ceaf9SAlex Deucher seq_printf(m, "Last emitted 0x%016llx\n", 6785907a0d8SChristian König ring->fence_drv.sync_seq); 679d38ceaf9SAlex Deucher } 680d38ceaf9SAlex Deucher return 0; 681d38ceaf9SAlex Deucher } 682d38ceaf9SAlex Deucher 68318db89b4SAlex Deucher /** 68418db89b4SAlex Deucher * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset 68518db89b4SAlex Deucher * 68618db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 68718db89b4SAlex Deucher */ 68818db89b4SAlex Deucher static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) 68918db89b4SAlex Deucher { 69018db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 69118db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 69218db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 69318db89b4SAlex Deucher 69418db89b4SAlex Deucher seq_printf(m, "gpu reset\n"); 69518db89b4SAlex Deucher amdgpu_gpu_reset(adev); 69618db89b4SAlex Deucher 69718db89b4SAlex Deucher return 0; 69818db89b4SAlex Deucher } 69918db89b4SAlex Deucher 700d38ceaf9SAlex Deucher static struct drm_info_list amdgpu_debugfs_fence_list[] = { 701d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 70218db89b4SAlex Deucher {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} 703d38ceaf9SAlex Deucher }; 704d38ceaf9SAlex Deucher #endif 705d38ceaf9SAlex Deucher 706d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 707d38ceaf9SAlex Deucher { 708d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 70918db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 710d38ceaf9SAlex Deucher #else 711d38ceaf9SAlex Deucher return 0; 712d38ceaf9SAlex Deucher #endif 713d38ceaf9SAlex Deucher } 714d38ceaf9SAlex Deucher 715