1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 5022e5a2f4SChristian König struct amdgpu_fence { 51f54d1867SChris Wilson struct dma_fence base; 5222e5a2f4SChristian König 5322e5a2f4SChristian König /* RB, DMA, etc. */ 5422e5a2f4SChristian König struct amdgpu_ring *ring; 5522e5a2f4SChristian König }; 5622e5a2f4SChristian König 57b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 58b49c84a5SChunming Zhou 59d573de2dSRex Zhu int amdgpu_fence_slab_init(void) 60d573de2dSRex Zhu { 61d573de2dSRex Zhu amdgpu_fence_slab = kmem_cache_create( 62d573de2dSRex Zhu "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 63d573de2dSRex Zhu SLAB_HWCACHE_ALIGN, NULL); 64d573de2dSRex Zhu if (!amdgpu_fence_slab) 65d573de2dSRex Zhu return -ENOMEM; 66d573de2dSRex Zhu return 0; 67d573de2dSRex Zhu } 68d573de2dSRex Zhu 69d573de2dSRex Zhu void amdgpu_fence_slab_fini(void) 70d573de2dSRex Zhu { 710f10425eSGrazvydas Ignotas rcu_barrier(); 72d573de2dSRex Zhu kmem_cache_destroy(amdgpu_fence_slab); 73d573de2dSRex Zhu } 7422e5a2f4SChristian König /* 7522e5a2f4SChristian König * Cast helper 7622e5a2f4SChristian König */ 77f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops; 78f54d1867SChris Wilson static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 7922e5a2f4SChristian König { 8022e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 8122e5a2f4SChristian König 8222e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 8322e5a2f4SChristian König return __f; 8422e5a2f4SChristian König 8522e5a2f4SChristian König return NULL; 8622e5a2f4SChristian König } 8722e5a2f4SChristian König 88d38ceaf9SAlex Deucher /** 89d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 90d38ceaf9SAlex Deucher * 91d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 92d38ceaf9SAlex Deucher * @seq: sequence number to write 93d38ceaf9SAlex Deucher * 94d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 95d38ceaf9SAlex Deucher */ 96d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 97d38ceaf9SAlex Deucher { 98d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher if (drv->cpu_addr) 101d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 102d38ceaf9SAlex Deucher } 103d38ceaf9SAlex Deucher 104d38ceaf9SAlex Deucher /** 105d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 106d38ceaf9SAlex Deucher * 107d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 108d38ceaf9SAlex Deucher * 109d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 110d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 111d38ceaf9SAlex Deucher */ 112d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 113d38ceaf9SAlex Deucher { 114d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 115d38ceaf9SAlex Deucher u32 seq = 0; 116d38ceaf9SAlex Deucher 117d38ceaf9SAlex Deucher if (drv->cpu_addr) 118d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 119d38ceaf9SAlex Deucher else 120742c085fSChristian König seq = atomic_read(&drv->last_seq); 121d38ceaf9SAlex Deucher 122d38ceaf9SAlex Deucher return seq; 123d38ceaf9SAlex Deucher } 124d38ceaf9SAlex Deucher 125d38ceaf9SAlex Deucher /** 126d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 127d38ceaf9SAlex Deucher * 128d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 129364beb2cSChristian König * @f: resulting fence object 130d38ceaf9SAlex Deucher * 131d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 132d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 133d38ceaf9SAlex Deucher */ 134d240cd9eSMarek Olšák int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 135d240cd9eSMarek Olšák unsigned flags) 136d38ceaf9SAlex Deucher { 137d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 138364beb2cSChristian König struct amdgpu_fence *fence; 139f54d1867SChris Wilson struct dma_fence *old, **ptr; 140742c085fSChristian König uint32_t seq; 141d38ceaf9SAlex Deucher 142364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 143364beb2cSChristian König if (fence == NULL) 144d38ceaf9SAlex Deucher return -ENOMEM; 145364beb2cSChristian König 146742c085fSChristian König seq = ++ring->fence_drv.sync_seq; 147364beb2cSChristian König fence->ring = ring; 148f54d1867SChris Wilson dma_fence_init(&fence->base, &amdgpu_fence_ops, 1494a7d74f1SChristian König &ring->fence_drv.lock, 1507f06c236Smonk.liu adev->fence_context + ring->idx, 151742c085fSChristian König seq); 152890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 153d240cd9eSMarek Olšák seq, flags | AMDGPU_FENCE_FLAG_INT); 154c89377d1SChristian König 155742c085fSChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 156c89377d1SChristian König /* This function can't be called concurrently anyway, otherwise 157c89377d1SChristian König * emitting the fence would mess up the hardware ring buffer. 158c89377d1SChristian König */ 159fc387a0bSChunming Zhou old = rcu_dereference_protected(*ptr, 1); 160f54d1867SChris Wilson if (old && !dma_fence_is_signaled(old)) { 161fc387a0bSChunming Zhou DRM_INFO("rcu slot is busy\n"); 162f54d1867SChris Wilson dma_fence_wait(old, false); 163fc387a0bSChunming Zhou } 164c89377d1SChristian König 165f54d1867SChris Wilson rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 166c89377d1SChristian König 167364beb2cSChristian König *f = &fence->base; 168c89377d1SChristian König 169d38ceaf9SAlex Deucher return 0; 170d38ceaf9SAlex Deucher } 171d38ceaf9SAlex Deucher 172d38ceaf9SAlex Deucher /** 17343ca8efaSpding * amdgpu_fence_emit_polling - emit a fence on the requeste ring 17443ca8efaSpding * 17543ca8efaSpding * @ring: ring the fence is associated with 17643ca8efaSpding * @s: resulting sequence number 17743ca8efaSpding * 17843ca8efaSpding * Emits a fence command on the requested ring (all asics). 17943ca8efaSpding * Used For polling fence. 18043ca8efaSpding * Returns 0 on success, -ENOMEM on failure. 18143ca8efaSpding */ 18243ca8efaSpding int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s) 18343ca8efaSpding { 18443ca8efaSpding uint32_t seq; 18543ca8efaSpding 18643ca8efaSpding if (!s) 18743ca8efaSpding return -EINVAL; 18843ca8efaSpding 18943ca8efaSpding seq = ++ring->fence_drv.sync_seq; 19043ca8efaSpding amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 191d118a621SMonk Liu seq, 0); 19243ca8efaSpding 19343ca8efaSpding *s = seq; 19443ca8efaSpding 19543ca8efaSpding return 0; 19643ca8efaSpding } 19743ca8efaSpding 19843ca8efaSpding /** 1998c5e13ecSAndrey Grodzovsky * amdgpu_fence_schedule_fallback - schedule fallback check 2008c5e13ecSAndrey Grodzovsky * 2018c5e13ecSAndrey Grodzovsky * @ring: pointer to struct amdgpu_ring 2028c5e13ecSAndrey Grodzovsky * 2038c5e13ecSAndrey Grodzovsky * Start a timer as fallback to our interrupts. 2048c5e13ecSAndrey Grodzovsky */ 2058c5e13ecSAndrey Grodzovsky static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 2068c5e13ecSAndrey Grodzovsky { 2078c5e13ecSAndrey Grodzovsky mod_timer(&ring->fence_drv.fallback_timer, 2088c5e13ecSAndrey Grodzovsky jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 2098c5e13ecSAndrey Grodzovsky } 2108c5e13ecSAndrey Grodzovsky 2118c5e13ecSAndrey Grodzovsky /** 212ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 213d38ceaf9SAlex Deucher * 214d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 215d38ceaf9SAlex Deucher * 216d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 217ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 218ca08e04dSChristian König * sequence number has increased. 219d38ceaf9SAlex Deucher */ 220ca08e04dSChristian König void amdgpu_fence_process(struct amdgpu_ring *ring) 221d38ceaf9SAlex Deucher { 2224a7d74f1SChristian König struct amdgpu_fence_driver *drv = &ring->fence_drv; 223742c085fSChristian König uint32_t seq, last_seq; 2244a7d74f1SChristian König int r; 225d38ceaf9SAlex Deucher 226d38ceaf9SAlex Deucher do { 227742c085fSChristian König last_seq = atomic_read(&ring->fence_drv.last_seq); 228d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 229d38ceaf9SAlex Deucher 230742c085fSChristian König } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 231d38ceaf9SAlex Deucher 2328c5e13ecSAndrey Grodzovsky if (seq != ring->fence_drv.sync_seq) 2338c5e13ecSAndrey Grodzovsky amdgpu_fence_schedule_fallback(ring); 2348c5e13ecSAndrey Grodzovsky 2352ef004d9SChristian König if (unlikely(seq == last_seq)) 2362ef004d9SChristian König return; 2372ef004d9SChristian König 2384f399a08SChristian König last_seq &= drv->num_fences_mask; 2394f399a08SChristian König seq &= drv->num_fences_mask; 2404f399a08SChristian König 2412ef004d9SChristian König do { 242f54d1867SChris Wilson struct dma_fence *fence, **ptr; 2434a7d74f1SChristian König 2444f399a08SChristian König ++last_seq; 2454f399a08SChristian König last_seq &= drv->num_fences_mask; 2464f399a08SChristian König ptr = &drv->fences[last_seq]; 2474a7d74f1SChristian König 2484a7d74f1SChristian König /* There is always exactly one thread signaling this fence slot */ 2494a7d74f1SChristian König fence = rcu_dereference_protected(*ptr, 1); 25084fae133SMuhammad Falak R Wani RCU_INIT_POINTER(*ptr, NULL); 2514a7d74f1SChristian König 2524f399a08SChristian König if (!fence) 2534f399a08SChristian König continue; 2544a7d74f1SChristian König 255f54d1867SChris Wilson r = dma_fence_signal(fence); 2564a7d74f1SChristian König if (!r) 257f54d1867SChris Wilson DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 2584a7d74f1SChristian König else 2594a7d74f1SChristian König BUG(); 2604a7d74f1SChristian König 261f54d1867SChris Wilson dma_fence_put(fence); 2622ef004d9SChristian König } while (last_seq != seq); 263e0d8f3c3SChunming Zhou } 264d38ceaf9SAlex Deucher 265d38ceaf9SAlex Deucher /** 2668c5e13ecSAndrey Grodzovsky * amdgpu_fence_fallback - fallback for hardware interrupts 2678c5e13ecSAndrey Grodzovsky * 2688c5e13ecSAndrey Grodzovsky * @work: delayed work item 2698c5e13ecSAndrey Grodzovsky * 2708c5e13ecSAndrey Grodzovsky * Checks for fence activity. 2718c5e13ecSAndrey Grodzovsky */ 2728c5e13ecSAndrey Grodzovsky static void amdgpu_fence_fallback(struct timer_list *t) 2738c5e13ecSAndrey Grodzovsky { 2748c5e13ecSAndrey Grodzovsky struct amdgpu_ring *ring = from_timer(ring, t, 2758c5e13ecSAndrey Grodzovsky fence_drv.fallback_timer); 2768c5e13ecSAndrey Grodzovsky 2778c5e13ecSAndrey Grodzovsky amdgpu_fence_process(ring); 2788c5e13ecSAndrey Grodzovsky } 2798c5e13ecSAndrey Grodzovsky 2808c5e13ecSAndrey Grodzovsky /** 281d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 282d38ceaf9SAlex Deucher * 283d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 284d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 285d38ceaf9SAlex Deucher * 286d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 287d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 288d38ceaf9SAlex Deucher */ 289d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 290d38ceaf9SAlex Deucher { 2916aa7de05SMark Rutland uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 292f54d1867SChris Wilson struct dma_fence *fence, **ptr; 293f09c2be4SChristian König int r; 29400d2a2b2SChristian König 2957f06c236Smonk.liu if (!seq) 296d38ceaf9SAlex Deucher return 0; 297d38ceaf9SAlex Deucher 298f09c2be4SChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 299f09c2be4SChristian König rcu_read_lock(); 300f09c2be4SChristian König fence = rcu_dereference(*ptr); 301f54d1867SChris Wilson if (!fence || !dma_fence_get_rcu(fence)) { 302f09c2be4SChristian König rcu_read_unlock(); 303f09c2be4SChristian König return 0; 304f09c2be4SChristian König } 305f09c2be4SChristian König rcu_read_unlock(); 306f09c2be4SChristian König 307f54d1867SChris Wilson r = dma_fence_wait(fence, false); 308f54d1867SChris Wilson dma_fence_put(fence); 309f09c2be4SChristian König return r; 310d38ceaf9SAlex Deucher } 311d38ceaf9SAlex Deucher 312d38ceaf9SAlex Deucher /** 31343ca8efaSpding * amdgpu_fence_wait_polling - busy wait for givn sequence number 31443ca8efaSpding * 31543ca8efaSpding * @ring: ring index the fence is associated with 31643ca8efaSpding * @wait_seq: sequence number to wait 31743ca8efaSpding * @timeout: the timeout for waiting in usecs 31843ca8efaSpding * 31943ca8efaSpding * Wait for all fences on the requested ring to signal (all asics). 32043ca8efaSpding * Returns left time if no timeout, 0 or minus if timeout. 32143ca8efaSpding */ 32243ca8efaSpding signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 32343ca8efaSpding uint32_t wait_seq, 32443ca8efaSpding signed long timeout) 32543ca8efaSpding { 32643ca8efaSpding uint32_t seq; 32743ca8efaSpding 32843ca8efaSpding do { 32943ca8efaSpding seq = amdgpu_fence_read(ring); 33043ca8efaSpding udelay(5); 33143ca8efaSpding timeout -= 5; 33243ca8efaSpding } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 33343ca8efaSpding 33443ca8efaSpding return timeout > 0 ? timeout : 0; 33543ca8efaSpding } 33643ca8efaSpding /** 337d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 338d38ceaf9SAlex Deucher * 339d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 340d38ceaf9SAlex Deucher * 341d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 342d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 343d38ceaf9SAlex Deucher * dynpm code to ring track activity. 344d38ceaf9SAlex Deucher */ 345d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 346d38ceaf9SAlex Deucher { 347d38ceaf9SAlex Deucher uint64_t emitted; 348d38ceaf9SAlex Deucher 349d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 350d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 351d38ceaf9SAlex Deucher */ 352d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 353742c085fSChristian König emitted = 0x100000000ull; 354742c085fSChristian König emitted -= atomic_read(&ring->fence_drv.last_seq); 3556aa7de05SMark Rutland emitted += READ_ONCE(ring->fence_drv.sync_seq); 356742c085fSChristian König return lower_32_bits(emitted); 357d38ceaf9SAlex Deucher } 358d38ceaf9SAlex Deucher 359d38ceaf9SAlex Deucher /** 360d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 361d38ceaf9SAlex Deucher * ready for use on the requested ring. 362d38ceaf9SAlex Deucher * 363d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 364d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 365d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 366d38ceaf9SAlex Deucher * 367d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 368d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 369d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 370d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 371d38ceaf9SAlex Deucher */ 372d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 373d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 374d38ceaf9SAlex Deucher unsigned irq_type) 375d38ceaf9SAlex Deucher { 376d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 377d38ceaf9SAlex Deucher uint64_t index; 378d38ceaf9SAlex Deucher 379d9e98ee2SLeo Liu if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 380d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 381d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 382d38ceaf9SAlex Deucher } else { 383d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 384d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 38510dd74eaSJames Zhu ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 38610dd74eaSJames Zhu ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 387d38ceaf9SAlex Deucher } 388742c085fSChristian König amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 389c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 390c6a4079bSChunming Zhou 391d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 392d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 393c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 394c6a4079bSChunming Zhou 3959953b72fSpding dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " 396d38ceaf9SAlex Deucher "cpu addr 0x%p\n", ring->idx, 397d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 398d38ceaf9SAlex Deucher return 0; 399d38ceaf9SAlex Deucher } 400d38ceaf9SAlex Deucher 401d38ceaf9SAlex Deucher /** 402d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 403d38ceaf9SAlex Deucher * for the requested ring. 404d38ceaf9SAlex Deucher * 405d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 406e6151a08SChristian König * @num_hw_submission: number of entries on the hardware queue 407d38ceaf9SAlex Deucher * 408d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 409d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 410d38ceaf9SAlex Deucher */ 411e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 412e6151a08SChristian König unsigned num_hw_submission) 413d38ceaf9SAlex Deucher { 414687c1c2eSEvan Quan long timeout; 4155907a0d8SChristian König int r; 416d38ceaf9SAlex Deucher 417e6151a08SChristian König /* Check that num_hw_submission is a power of two */ 418e6151a08SChristian König if ((num_hw_submission & (num_hw_submission - 1)) != 0) 419e6151a08SChristian König return -EINVAL; 420e6151a08SChristian König 421d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 422d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 4235907a0d8SChristian König ring->fence_drv.sync_seq = 0; 424742c085fSChristian König atomic_set(&ring->fence_drv.last_seq, 0); 425d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 426d38ceaf9SAlex Deucher 4278c5e13ecSAndrey Grodzovsky timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 4288c5e13ecSAndrey Grodzovsky 42966067ad7SChunming Zhou ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 4304a7d74f1SChristian König spin_lock_init(&ring->fence_drv.lock); 43166067ad7SChunming Zhou ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 432c89377d1SChristian König GFP_KERNEL); 433c89377d1SChristian König if (!ring->fence_drv.fences) 434c89377d1SChristian König return -ENOMEM; 4355ec92a76SChristian König 436e2250442STrigger Huang /* No need to setup the GPU scheduler for KIQ ring */ 437e2250442STrigger Huang if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) { 438687c1c2eSEvan Quan /* for non-sriov case, no timeout enforce on compute ring */ 439687c1c2eSEvan Quan if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) 440687c1c2eSEvan Quan && !amdgpu_sriov_vf(ring->adev)) 441687c1c2eSEvan Quan timeout = MAX_SCHEDULE_TIMEOUT; 442687c1c2eSEvan Quan else 443687c1c2eSEvan Quan timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 444687c1c2eSEvan Quan 4451b1f42d8SLucas Stach r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 44695aa9b1dSMonk Liu num_hw_submission, amdgpu_job_hang_limit, 447687c1c2eSEvan Quan timeout, ring->name); 4484f839a24SChristian König if (r) { 4494f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 4504f839a24SChristian König ring->name); 4514f839a24SChristian König return r; 452b80d8475SAlex Deucher } 453e2250442STrigger Huang } 454d38ceaf9SAlex Deucher 4554f839a24SChristian König return 0; 4564f839a24SChristian König } 4574f839a24SChristian König 458d38ceaf9SAlex Deucher /** 459d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 460d38ceaf9SAlex Deucher * for all possible rings. 461d38ceaf9SAlex Deucher * 462d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 463d38ceaf9SAlex Deucher * 464d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 465d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 466d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 467d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 468d38ceaf9SAlex Deucher * Returns 0 for success. 469d38ceaf9SAlex Deucher */ 470d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 471d38ceaf9SAlex Deucher { 472d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 473d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 474d38ceaf9SAlex Deucher 475d38ceaf9SAlex Deucher return 0; 476d38ceaf9SAlex Deucher } 477d38ceaf9SAlex Deucher 478d38ceaf9SAlex Deucher /** 479d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 480d38ceaf9SAlex Deucher * for all possible rings. 481d38ceaf9SAlex Deucher * 482d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 483d38ceaf9SAlex Deucher * 484d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 485d38ceaf9SAlex Deucher */ 486d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 487d38ceaf9SAlex Deucher { 488c89377d1SChristian König unsigned i, j; 489c89377d1SChristian König int r; 490d38ceaf9SAlex Deucher 491d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 492d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 493c2776afeSChristian König 494d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 495d38ceaf9SAlex Deucher continue; 496d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 497d38ceaf9SAlex Deucher if (r) { 498d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 4992f9d4084SMonk Liu amdgpu_fence_driver_force_completion(ring); 500d38ceaf9SAlex Deucher } 501c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 502c6a4079bSChunming Zhou ring->fence_drv.irq_type); 5031b1f42d8SLucas Stach drm_sched_fini(&ring->sched); 5048c5e13ecSAndrey Grodzovsky del_timer_sync(&ring->fence_drv.fallback_timer); 505c89377d1SChristian König for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 506f54d1867SChris Wilson dma_fence_put(ring->fence_drv.fences[j]); 507c89377d1SChristian König kfree(ring->fence_drv.fences); 50854ddf3a6SGrazvydas Ignotas ring->fence_drv.fences = NULL; 509d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 510d38ceaf9SAlex Deucher } 511d38ceaf9SAlex Deucher } 512d38ceaf9SAlex Deucher 513d38ceaf9SAlex Deucher /** 5145ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 5155ceb54c6SAlex Deucher * for all possible rings. 5165ceb54c6SAlex Deucher * 5175ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5185ceb54c6SAlex Deucher * 5195ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 5205ceb54c6SAlex Deucher */ 5215ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 5225ceb54c6SAlex Deucher { 5235ceb54c6SAlex Deucher int i, r; 5245ceb54c6SAlex Deucher 5255ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5265ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5275ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5285ceb54c6SAlex Deucher continue; 5295ceb54c6SAlex Deucher 5305ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 5315ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 5325ceb54c6SAlex Deucher if (r) { 5335ceb54c6SAlex Deucher /* delay GPU reset to resume */ 5342f9d4084SMonk Liu amdgpu_fence_driver_force_completion(ring); 5355ceb54c6SAlex Deucher } 5365ceb54c6SAlex Deucher 5375ceb54c6SAlex Deucher /* disable the interrupt */ 5385ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 5395ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5405ceb54c6SAlex Deucher } 5415ceb54c6SAlex Deucher } 5425ceb54c6SAlex Deucher 5435ceb54c6SAlex Deucher /** 5445ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 5455ceb54c6SAlex Deucher * for all possible rings. 5465ceb54c6SAlex Deucher * 5475ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5485ceb54c6SAlex Deucher * 5495ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 5505ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 5515ceb54c6SAlex Deucher * start the fence driver on the rings it has using 5525ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 5535ceb54c6SAlex Deucher * Returns 0 for success. 5545ceb54c6SAlex Deucher */ 5555ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 5565ceb54c6SAlex Deucher { 5575ceb54c6SAlex Deucher int i; 5585ceb54c6SAlex Deucher 5595ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5605ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5615ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5625ceb54c6SAlex Deucher continue; 5635ceb54c6SAlex Deucher 5645ceb54c6SAlex Deucher /* enable the interrupt */ 5655ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 5665ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5675ceb54c6SAlex Deucher } 5685ceb54c6SAlex Deucher } 5695ceb54c6SAlex Deucher 5705ceb54c6SAlex Deucher /** 5712f9d4084SMonk Liu * amdgpu_fence_driver_force_completion - force signal latest fence of ring 572d38ceaf9SAlex Deucher * 5732f9d4084SMonk Liu * @ring: fence of the ring to signal 574d38ceaf9SAlex Deucher * 575d38ceaf9SAlex Deucher */ 5762f9d4084SMonk Liu void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 577d38ceaf9SAlex Deucher { 5785907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 5792f9d4084SMonk Liu amdgpu_fence_process(ring); 58065781c78SMonk Liu } 58165781c78SMonk Liu 582a95e2642SChristian König /* 583a95e2642SChristian König * Common fence implementation 584a95e2642SChristian König */ 585a95e2642SChristian König 586f54d1867SChris Wilson static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 587a95e2642SChristian König { 588a95e2642SChristian König return "amdgpu"; 589a95e2642SChristian König } 590a95e2642SChristian König 591f54d1867SChris Wilson static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 592a95e2642SChristian König { 593a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 594a95e2642SChristian König return (const char *)fence->ring->name; 595a95e2642SChristian König } 596a95e2642SChristian König 597a95e2642SChristian König /** 5988c5e13ecSAndrey Grodzovsky * amdgpu_fence_enable_signaling - enable signalling on fence 5998c5e13ecSAndrey Grodzovsky * @fence: fence 6008c5e13ecSAndrey Grodzovsky * 6018c5e13ecSAndrey Grodzovsky * This function is called with fence_queue lock held, and adds a callback 6028c5e13ecSAndrey Grodzovsky * to fence_queue that checks if this fence is signaled, and if so it 6038c5e13ecSAndrey Grodzovsky * signals the fence and removes itself. 6048c5e13ecSAndrey Grodzovsky */ 6058c5e13ecSAndrey Grodzovsky static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 6068c5e13ecSAndrey Grodzovsky { 6078c5e13ecSAndrey Grodzovsky struct amdgpu_fence *fence = to_amdgpu_fence(f); 6088c5e13ecSAndrey Grodzovsky struct amdgpu_ring *ring = fence->ring; 6098c5e13ecSAndrey Grodzovsky 6108c5e13ecSAndrey Grodzovsky if (!timer_pending(&ring->fence_drv.fallback_timer)) 6118c5e13ecSAndrey Grodzovsky amdgpu_fence_schedule_fallback(ring); 6128c5e13ecSAndrey Grodzovsky 6138c5e13ecSAndrey Grodzovsky DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 6148c5e13ecSAndrey Grodzovsky 6158c5e13ecSAndrey Grodzovsky return true; 6168c5e13ecSAndrey Grodzovsky } 6178c5e13ecSAndrey Grodzovsky 6188c5e13ecSAndrey Grodzovsky /** 619b4413535SChristian König * amdgpu_fence_free - free up the fence memory 620b4413535SChristian König * 621b4413535SChristian König * @rcu: RCU callback head 622b4413535SChristian König * 623b4413535SChristian König * Free up the fence memory after the RCU grace period. 624b4413535SChristian König */ 625b4413535SChristian König static void amdgpu_fence_free(struct rcu_head *rcu) 626b49c84a5SChunming Zhou { 627f54d1867SChris Wilson struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 628b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 629b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 630b49c84a5SChunming Zhou } 631b49c84a5SChunming Zhou 632b4413535SChristian König /** 633b4413535SChristian König * amdgpu_fence_release - callback that fence can be freed 634b4413535SChristian König * 635b4413535SChristian König * @fence: fence 636b4413535SChristian König * 637b4413535SChristian König * This function is called when the reference count becomes zero. 638b4413535SChristian König * It just RCU schedules freeing up the fence. 639b4413535SChristian König */ 640f54d1867SChris Wilson static void amdgpu_fence_release(struct dma_fence *f) 641b4413535SChristian König { 642b4413535SChristian König call_rcu(&f->rcu, amdgpu_fence_free); 643b4413535SChristian König } 644b4413535SChristian König 645f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops = { 646a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 647a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 6488c5e13ecSAndrey Grodzovsky .enable_signaling = amdgpu_fence_enable_signaling, 649b49c84a5SChunming Zhou .release = amdgpu_fence_release, 650a95e2642SChristian König }; 651d38ceaf9SAlex Deucher 652d38ceaf9SAlex Deucher /* 653d38ceaf9SAlex Deucher * Fence debugfs 654d38ceaf9SAlex Deucher */ 655d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 656d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 657d38ceaf9SAlex Deucher { 658d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 659d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 660d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 6615907a0d8SChristian König int i; 662d38ceaf9SAlex Deucher 663d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 664d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 665d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 666d38ceaf9SAlex Deucher continue; 667d38ceaf9SAlex Deucher 668d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 669d38ceaf9SAlex Deucher 670344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 671742c085fSChristian König seq_printf(m, "Last signaled fence 0x%08x\n", 672742c085fSChristian König atomic_read(&ring->fence_drv.last_seq)); 673742c085fSChristian König seq_printf(m, "Last emitted 0x%08x\n", 6745907a0d8SChristian König ring->fence_drv.sync_seq); 675e71de076Spding 676e71de076Spding if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 677e71de076Spding continue; 678e71de076Spding 679e71de076Spding /* set in CP_VMID_PREEMPT and preemption occurred */ 680e71de076Spding seq_printf(m, "Last preempted 0x%08x\n", 681e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 682e71de076Spding /* set in CP_VMID_RESET and reset occurred */ 683e71de076Spding seq_printf(m, "Last reset 0x%08x\n", 684e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 685e71de076Spding /* Both preemption and reset occurred */ 686e71de076Spding seq_printf(m, "Last both 0x%08x\n", 687e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 688d38ceaf9SAlex Deucher } 689d38ceaf9SAlex Deucher return 0; 690d38ceaf9SAlex Deucher } 691d38ceaf9SAlex Deucher 69218db89b4SAlex Deucher /** 6935740682eSMonk Liu * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 69418db89b4SAlex Deucher * 69518db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 69618db89b4SAlex Deucher */ 6975740682eSMonk Liu static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) 69818db89b4SAlex Deucher { 69918db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 70018db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 70118db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 70218db89b4SAlex Deucher 7035740682eSMonk Liu seq_printf(m, "gpu recover\n"); 70412938fadSChristian König amdgpu_device_gpu_recover(adev, NULL); 70518db89b4SAlex Deucher 70618db89b4SAlex Deucher return 0; 70718db89b4SAlex Deucher } 70818db89b4SAlex Deucher 70906ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 710d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 7115740682eSMonk Liu {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} 712d38ceaf9SAlex Deucher }; 7134fbf87e2SMonk Liu 7144fbf87e2SMonk Liu static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { 7154fbf87e2SMonk Liu {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 7164fbf87e2SMonk Liu }; 717d38ceaf9SAlex Deucher #endif 718d38ceaf9SAlex Deucher 719d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 720d38ceaf9SAlex Deucher { 721d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 7224fbf87e2SMonk Liu if (amdgpu_sriov_vf(adev)) 7234fbf87e2SMonk Liu return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1); 72418db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 725d38ceaf9SAlex Deucher #else 726d38ceaf9SAlex Deucher return 0; 727d38ceaf9SAlex Deucher #endif 728d38ceaf9SAlex Deucher } 729d38ceaf9SAlex Deucher 730