1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 3745a80abeSAlex Deucher #include <linux/pm_runtime.h> 38fdf2f6c5SSam Ravnborg 39fdf2f6c5SSam Ravnborg #include <drm/drm_debugfs.h> 40fdf2f6c5SSam Ravnborg 41d38ceaf9SAlex Deucher #include "amdgpu.h" 42d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 43d38ceaf9SAlex Deucher 44d38ceaf9SAlex Deucher /* 45d38ceaf9SAlex Deucher * Fences 46d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 47d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 48d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 49d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 50d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 51d38ceaf9SAlex Deucher */ 52d38ceaf9SAlex Deucher 5322e5a2f4SChristian König struct amdgpu_fence { 54f54d1867SChris Wilson struct dma_fence base; 5522e5a2f4SChristian König 5622e5a2f4SChristian König /* RB, DMA, etc. */ 5722e5a2f4SChristian König struct amdgpu_ring *ring; 5822e5a2f4SChristian König }; 5922e5a2f4SChristian König 60b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 61b49c84a5SChunming Zhou 62d573de2dSRex Zhu int amdgpu_fence_slab_init(void) 63d573de2dSRex Zhu { 64d573de2dSRex Zhu amdgpu_fence_slab = kmem_cache_create( 65d573de2dSRex Zhu "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 66d573de2dSRex Zhu SLAB_HWCACHE_ALIGN, NULL); 67d573de2dSRex Zhu if (!amdgpu_fence_slab) 68d573de2dSRex Zhu return -ENOMEM; 69d573de2dSRex Zhu return 0; 70d573de2dSRex Zhu } 71d573de2dSRex Zhu 72d573de2dSRex Zhu void amdgpu_fence_slab_fini(void) 73d573de2dSRex Zhu { 740f10425eSGrazvydas Ignotas rcu_barrier(); 75d573de2dSRex Zhu kmem_cache_destroy(amdgpu_fence_slab); 76d573de2dSRex Zhu } 7722e5a2f4SChristian König /* 7822e5a2f4SChristian König * Cast helper 7922e5a2f4SChristian König */ 80f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops; 81f54d1867SChris Wilson static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f) 8222e5a2f4SChristian König { 8322e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 8422e5a2f4SChristian König 8522e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 8622e5a2f4SChristian König return __f; 8722e5a2f4SChristian König 8822e5a2f4SChristian König return NULL; 8922e5a2f4SChristian König } 9022e5a2f4SChristian König 91d38ceaf9SAlex Deucher /** 92d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 93d38ceaf9SAlex Deucher * 94d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 95d38ceaf9SAlex Deucher * @seq: sequence number to write 96d38ceaf9SAlex Deucher * 97d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 98d38ceaf9SAlex Deucher */ 99d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 100d38ceaf9SAlex Deucher { 101d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 102d38ceaf9SAlex Deucher 103d38ceaf9SAlex Deucher if (drv->cpu_addr) 104d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 105d38ceaf9SAlex Deucher } 106d38ceaf9SAlex Deucher 107d38ceaf9SAlex Deucher /** 108d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 109d38ceaf9SAlex Deucher * 110d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 111d38ceaf9SAlex Deucher * 112d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 113d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 114d38ceaf9SAlex Deucher */ 115d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 116d38ceaf9SAlex Deucher { 117d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 118d38ceaf9SAlex Deucher u32 seq = 0; 119d38ceaf9SAlex Deucher 120d38ceaf9SAlex Deucher if (drv->cpu_addr) 121d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 122d38ceaf9SAlex Deucher else 123742c085fSChristian König seq = atomic_read(&drv->last_seq); 124d38ceaf9SAlex Deucher 125d38ceaf9SAlex Deucher return seq; 126d38ceaf9SAlex Deucher } 127d38ceaf9SAlex Deucher 128d38ceaf9SAlex Deucher /** 129d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 130d38ceaf9SAlex Deucher * 131d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 132364beb2cSChristian König * @f: resulting fence object 133d38ceaf9SAlex Deucher * 134d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 135d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 136d38ceaf9SAlex Deucher */ 137d240cd9eSMarek Olšák int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, 138d240cd9eSMarek Olšák unsigned flags) 139d38ceaf9SAlex Deucher { 140d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 141364beb2cSChristian König struct amdgpu_fence *fence; 1423d2aca8cSChristian König struct dma_fence __rcu **ptr; 143742c085fSChristian König uint32_t seq; 1443d2aca8cSChristian König int r; 145d38ceaf9SAlex Deucher 146364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 147364beb2cSChristian König if (fence == NULL) 148d38ceaf9SAlex Deucher return -ENOMEM; 149364beb2cSChristian König 150742c085fSChristian König seq = ++ring->fence_drv.sync_seq; 151364beb2cSChristian König fence->ring = ring; 152f54d1867SChris Wilson dma_fence_init(&fence->base, &amdgpu_fence_ops, 1534a7d74f1SChristian König &ring->fence_drv.lock, 1547f06c236Smonk.liu adev->fence_context + ring->idx, 155742c085fSChristian König seq); 156890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 157d240cd9eSMarek Olšák seq, flags | AMDGPU_FENCE_FLAG_INT); 15845a80abeSAlex Deucher pm_runtime_get_noresume(adev->ddev->dev); 159742c085fSChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 1603d2aca8cSChristian König if (unlikely(rcu_dereference_protected(*ptr, 1))) { 1613d2aca8cSChristian König struct dma_fence *old; 1623d2aca8cSChristian König 1633d2aca8cSChristian König rcu_read_lock(); 1643d2aca8cSChristian König old = dma_fence_get_rcu_safe(ptr); 1653d2aca8cSChristian König rcu_read_unlock(); 1663d2aca8cSChristian König 1673d2aca8cSChristian König if (old) { 1683d2aca8cSChristian König r = dma_fence_wait(old, false); 1693d2aca8cSChristian König dma_fence_put(old); 1703d2aca8cSChristian König if (r) 1713d2aca8cSChristian König return r; 1723d2aca8cSChristian König } 1733d2aca8cSChristian König } 1743d2aca8cSChristian König 175c89377d1SChristian König /* This function can't be called concurrently anyway, otherwise 176c89377d1SChristian König * emitting the fence would mess up the hardware ring buffer. 177c89377d1SChristian König */ 178f54d1867SChris Wilson rcu_assign_pointer(*ptr, dma_fence_get(&fence->base)); 179c89377d1SChristian König 180364beb2cSChristian König *f = &fence->base; 181c89377d1SChristian König 182d38ceaf9SAlex Deucher return 0; 183d38ceaf9SAlex Deucher } 184d38ceaf9SAlex Deucher 185d38ceaf9SAlex Deucher /** 18643ca8efaSpding * amdgpu_fence_emit_polling - emit a fence on the requeste ring 18743ca8efaSpding * 18843ca8efaSpding * @ring: ring the fence is associated with 18943ca8efaSpding * @s: resulting sequence number 19043ca8efaSpding * 19143ca8efaSpding * Emits a fence command on the requested ring (all asics). 19243ca8efaSpding * Used For polling fence. 19343ca8efaSpding * Returns 0 on success, -ENOMEM on failure. 19443ca8efaSpding */ 19504e4e2e9SYintian Tao int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, 19604e4e2e9SYintian Tao uint32_t timeout) 19743ca8efaSpding { 19843ca8efaSpding uint32_t seq; 19904e4e2e9SYintian Tao signed long r; 20043ca8efaSpding 20143ca8efaSpding if (!s) 20243ca8efaSpding return -EINVAL; 20343ca8efaSpding 20443ca8efaSpding seq = ++ring->fence_drv.sync_seq; 20504e4e2e9SYintian Tao r = amdgpu_fence_wait_polling(ring, 20604e4e2e9SYintian Tao seq - ring->fence_drv.num_fences_mask, 20704e4e2e9SYintian Tao timeout); 20804e4e2e9SYintian Tao if (r < 1) 20904e4e2e9SYintian Tao return -ETIMEDOUT; 21004e4e2e9SYintian Tao 21143ca8efaSpding amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 212d118a621SMonk Liu seq, 0); 21343ca8efaSpding 21443ca8efaSpding *s = seq; 21543ca8efaSpding 21643ca8efaSpding return 0; 21743ca8efaSpding } 21843ca8efaSpding 21943ca8efaSpding /** 2208c5e13ecSAndrey Grodzovsky * amdgpu_fence_schedule_fallback - schedule fallback check 2218c5e13ecSAndrey Grodzovsky * 2228c5e13ecSAndrey Grodzovsky * @ring: pointer to struct amdgpu_ring 2238c5e13ecSAndrey Grodzovsky * 2248c5e13ecSAndrey Grodzovsky * Start a timer as fallback to our interrupts. 2258c5e13ecSAndrey Grodzovsky */ 2268c5e13ecSAndrey Grodzovsky static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 2278c5e13ecSAndrey Grodzovsky { 2288c5e13ecSAndrey Grodzovsky mod_timer(&ring->fence_drv.fallback_timer, 2298c5e13ecSAndrey Grodzovsky jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 2308c5e13ecSAndrey Grodzovsky } 2318c5e13ecSAndrey Grodzovsky 2328c5e13ecSAndrey Grodzovsky /** 233ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 234d38ceaf9SAlex Deucher * 235d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 236d38ceaf9SAlex Deucher * 237d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 238ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 239ca08e04dSChristian König * sequence number has increased. 24095d7fc4aSAndrey Grodzovsky * 24195d7fc4aSAndrey Grodzovsky * Returns true if fence was processed 242d38ceaf9SAlex Deucher */ 24395d7fc4aSAndrey Grodzovsky bool amdgpu_fence_process(struct amdgpu_ring *ring) 244d38ceaf9SAlex Deucher { 2454a7d74f1SChristian König struct amdgpu_fence_driver *drv = &ring->fence_drv; 24645a80abeSAlex Deucher struct amdgpu_device *adev = ring->adev; 247742c085fSChristian König uint32_t seq, last_seq; 2484a7d74f1SChristian König int r; 249d38ceaf9SAlex Deucher 250d38ceaf9SAlex Deucher do { 251742c085fSChristian König last_seq = atomic_read(&ring->fence_drv.last_seq); 252d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 253d38ceaf9SAlex Deucher 254742c085fSChristian König } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 255d38ceaf9SAlex Deucher 2563547e3cfSAndrey Grodzovsky if (del_timer(&ring->fence_drv.fallback_timer) && 2573547e3cfSAndrey Grodzovsky seq != ring->fence_drv.sync_seq) 2588c5e13ecSAndrey Grodzovsky amdgpu_fence_schedule_fallback(ring); 2598c5e13ecSAndrey Grodzovsky 2602ef004d9SChristian König if (unlikely(seq == last_seq)) 26195d7fc4aSAndrey Grodzovsky return false; 2622ef004d9SChristian König 2634f399a08SChristian König last_seq &= drv->num_fences_mask; 2644f399a08SChristian König seq &= drv->num_fences_mask; 2654f399a08SChristian König 2662ef004d9SChristian König do { 267f54d1867SChris Wilson struct dma_fence *fence, **ptr; 2684a7d74f1SChristian König 2694f399a08SChristian König ++last_seq; 2704f399a08SChristian König last_seq &= drv->num_fences_mask; 2714f399a08SChristian König ptr = &drv->fences[last_seq]; 2724a7d74f1SChristian König 2734a7d74f1SChristian König /* There is always exactly one thread signaling this fence slot */ 2744a7d74f1SChristian König fence = rcu_dereference_protected(*ptr, 1); 27584fae133SMuhammad Falak R Wani RCU_INIT_POINTER(*ptr, NULL); 2764a7d74f1SChristian König 2774f399a08SChristian König if (!fence) 2784f399a08SChristian König continue; 2794a7d74f1SChristian König 280f54d1867SChris Wilson r = dma_fence_signal(fence); 2814a7d74f1SChristian König if (!r) 282f54d1867SChris Wilson DMA_FENCE_TRACE(fence, "signaled from irq context\n"); 2834a7d74f1SChristian König else 2844a7d74f1SChristian König BUG(); 2854a7d74f1SChristian König 286f54d1867SChris Wilson dma_fence_put(fence); 28745a80abeSAlex Deucher pm_runtime_mark_last_busy(adev->ddev->dev); 28845a80abeSAlex Deucher pm_runtime_put_autosuspend(adev->ddev->dev); 2892ef004d9SChristian König } while (last_seq != seq); 29095d7fc4aSAndrey Grodzovsky 29195d7fc4aSAndrey Grodzovsky return true; 292e0d8f3c3SChunming Zhou } 293d38ceaf9SAlex Deucher 294d38ceaf9SAlex Deucher /** 2958c5e13ecSAndrey Grodzovsky * amdgpu_fence_fallback - fallback for hardware interrupts 2968c5e13ecSAndrey Grodzovsky * 2978c5e13ecSAndrey Grodzovsky * @work: delayed work item 2988c5e13ecSAndrey Grodzovsky * 2998c5e13ecSAndrey Grodzovsky * Checks for fence activity. 3008c5e13ecSAndrey Grodzovsky */ 3018c5e13ecSAndrey Grodzovsky static void amdgpu_fence_fallback(struct timer_list *t) 3028c5e13ecSAndrey Grodzovsky { 3038c5e13ecSAndrey Grodzovsky struct amdgpu_ring *ring = from_timer(ring, t, 3048c5e13ecSAndrey Grodzovsky fence_drv.fallback_timer); 3058c5e13ecSAndrey Grodzovsky 30695d7fc4aSAndrey Grodzovsky if (amdgpu_fence_process(ring)) 3073547e3cfSAndrey Grodzovsky DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); 3088c5e13ecSAndrey Grodzovsky } 3098c5e13ecSAndrey Grodzovsky 3108c5e13ecSAndrey Grodzovsky /** 311d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 312d38ceaf9SAlex Deucher * 313d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 314d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 315d38ceaf9SAlex Deucher * 316d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 317d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 318d38ceaf9SAlex Deucher */ 319d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 320d38ceaf9SAlex Deucher { 3216aa7de05SMark Rutland uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq); 322f54d1867SChris Wilson struct dma_fence *fence, **ptr; 323f09c2be4SChristian König int r; 32400d2a2b2SChristian König 3257f06c236Smonk.liu if (!seq) 326d38ceaf9SAlex Deucher return 0; 327d38ceaf9SAlex Deucher 328f09c2be4SChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 329f09c2be4SChristian König rcu_read_lock(); 330f09c2be4SChristian König fence = rcu_dereference(*ptr); 331f54d1867SChris Wilson if (!fence || !dma_fence_get_rcu(fence)) { 332f09c2be4SChristian König rcu_read_unlock(); 333f09c2be4SChristian König return 0; 334f09c2be4SChristian König } 335f09c2be4SChristian König rcu_read_unlock(); 336f09c2be4SChristian König 337f54d1867SChris Wilson r = dma_fence_wait(fence, false); 338f54d1867SChris Wilson dma_fence_put(fence); 339f09c2be4SChristian König return r; 340d38ceaf9SAlex Deucher } 341d38ceaf9SAlex Deucher 342d38ceaf9SAlex Deucher /** 34343ca8efaSpding * amdgpu_fence_wait_polling - busy wait for givn sequence number 34443ca8efaSpding * 34543ca8efaSpding * @ring: ring index the fence is associated with 34643ca8efaSpding * @wait_seq: sequence number to wait 34743ca8efaSpding * @timeout: the timeout for waiting in usecs 34843ca8efaSpding * 34943ca8efaSpding * Wait for all fences on the requested ring to signal (all asics). 35043ca8efaSpding * Returns left time if no timeout, 0 or minus if timeout. 35143ca8efaSpding */ 35243ca8efaSpding signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 35343ca8efaSpding uint32_t wait_seq, 35443ca8efaSpding signed long timeout) 35543ca8efaSpding { 35643ca8efaSpding uint32_t seq; 35743ca8efaSpding 35843ca8efaSpding do { 35943ca8efaSpding seq = amdgpu_fence_read(ring); 36043ca8efaSpding udelay(5); 36143ca8efaSpding timeout -= 5; 36243ca8efaSpding } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0); 36343ca8efaSpding 36443ca8efaSpding return timeout > 0 ? timeout : 0; 36543ca8efaSpding } 36643ca8efaSpding /** 367d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 368d38ceaf9SAlex Deucher * 369d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 370d38ceaf9SAlex Deucher * 371d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 372d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 373d38ceaf9SAlex Deucher * dynpm code to ring track activity. 374d38ceaf9SAlex Deucher */ 375d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 376d38ceaf9SAlex Deucher { 377d38ceaf9SAlex Deucher uint64_t emitted; 378d38ceaf9SAlex Deucher 379d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 380d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 381d38ceaf9SAlex Deucher */ 382d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 383742c085fSChristian König emitted = 0x100000000ull; 384742c085fSChristian König emitted -= atomic_read(&ring->fence_drv.last_seq); 3856aa7de05SMark Rutland emitted += READ_ONCE(ring->fence_drv.sync_seq); 386742c085fSChristian König return lower_32_bits(emitted); 387d38ceaf9SAlex Deucher } 388d38ceaf9SAlex Deucher 389d38ceaf9SAlex Deucher /** 390d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 391d38ceaf9SAlex Deucher * ready for use on the requested ring. 392d38ceaf9SAlex Deucher * 393d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 394d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 395d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 396d38ceaf9SAlex Deucher * 397d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 398d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 399d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 400d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 401d38ceaf9SAlex Deucher */ 402d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 403d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 404d38ceaf9SAlex Deucher unsigned irq_type) 405d38ceaf9SAlex Deucher { 406d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 407d38ceaf9SAlex Deucher uint64_t index; 408d38ceaf9SAlex Deucher 409d9e98ee2SLeo Liu if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) { 410d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 411d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 412d38ceaf9SAlex Deucher } else { 413d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 414d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 41510dd74eaSJames Zhu ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; 41610dd74eaSJames Zhu ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; 417d38ceaf9SAlex Deucher } 418742c085fSChristian König amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 41955611b50SJack Xiao 42055611b50SJack Xiao if (irq_src) 421c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 422c6a4079bSChunming Zhou 423d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 424d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 425c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 426c6a4079bSChunming Zhou 4276e82c6e0SChristian König DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr " 4286e82c6e0SChristian König "0x%016llx, cpu addr 0x%p\n", ring->name, 429d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 430d38ceaf9SAlex Deucher return 0; 431d38ceaf9SAlex Deucher } 432d38ceaf9SAlex Deucher 433d38ceaf9SAlex Deucher /** 434d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 435d38ceaf9SAlex Deucher * for the requested ring. 436d38ceaf9SAlex Deucher * 437d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 438e6151a08SChristian König * @num_hw_submission: number of entries on the hardware queue 439d38ceaf9SAlex Deucher * 440d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 441d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 442d38ceaf9SAlex Deucher */ 443e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 444e6151a08SChristian König unsigned num_hw_submission) 445d38ceaf9SAlex Deucher { 446912dfc84SEvan Quan struct amdgpu_device *adev = ring->adev; 447687c1c2eSEvan Quan long timeout; 4485907a0d8SChristian König int r; 449d38ceaf9SAlex Deucher 450912dfc84SEvan Quan if (!adev) 451912dfc84SEvan Quan return -EINVAL; 452912dfc84SEvan Quan 453e6151a08SChristian König /* Check that num_hw_submission is a power of two */ 454e6151a08SChristian König if ((num_hw_submission & (num_hw_submission - 1)) != 0) 455e6151a08SChristian König return -EINVAL; 456e6151a08SChristian König 457d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 458d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 4595907a0d8SChristian König ring->fence_drv.sync_seq = 0; 460742c085fSChristian König atomic_set(&ring->fence_drv.last_seq, 0); 461d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 462d38ceaf9SAlex Deucher 4638c5e13ecSAndrey Grodzovsky timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); 4648c5e13ecSAndrey Grodzovsky 46566067ad7SChunming Zhou ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 4664a7d74f1SChristian König spin_lock_init(&ring->fence_drv.lock); 46766067ad7SChunming Zhou ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 468c89377d1SChristian König GFP_KERNEL); 469c89377d1SChristian König if (!ring->fence_drv.fences) 470c89377d1SChristian König return -ENOMEM; 4715ec92a76SChristian König 472730c2eb9SAlex Deucher /* No need to setup the GPU scheduler for rings that don't need it */ 473730c2eb9SAlex Deucher if (!ring->no_scheduler) { 474912dfc84SEvan Quan switch (ring->funcs->type) { 475912dfc84SEvan Quan case AMDGPU_RING_TYPE_GFX: 476912dfc84SEvan Quan timeout = adev->gfx_timeout; 477912dfc84SEvan Quan break; 478912dfc84SEvan Quan case AMDGPU_RING_TYPE_COMPUTE: 479912dfc84SEvan Quan timeout = adev->compute_timeout; 480912dfc84SEvan Quan break; 481912dfc84SEvan Quan case AMDGPU_RING_TYPE_SDMA: 482912dfc84SEvan Quan timeout = adev->sdma_timeout; 483912dfc84SEvan Quan break; 484912dfc84SEvan Quan default: 485912dfc84SEvan Quan timeout = adev->video_timeout; 486912dfc84SEvan Quan break; 487912dfc84SEvan Quan } 488687c1c2eSEvan Quan 4891b1f42d8SLucas Stach r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 49095aa9b1dSMonk Liu num_hw_submission, amdgpu_job_hang_limit, 491687c1c2eSEvan Quan timeout, ring->name); 4924f839a24SChristian König if (r) { 4934f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 4944f839a24SChristian König ring->name); 4954f839a24SChristian König return r; 496b80d8475SAlex Deucher } 497e2250442STrigger Huang } 498d38ceaf9SAlex Deucher 4994f839a24SChristian König return 0; 5004f839a24SChristian König } 5014f839a24SChristian König 502d38ceaf9SAlex Deucher /** 503d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 504d38ceaf9SAlex Deucher * for all possible rings. 505d38ceaf9SAlex Deucher * 506d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 507d38ceaf9SAlex Deucher * 508d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 509d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 510d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 511d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 512d38ceaf9SAlex Deucher * Returns 0 for success. 513d38ceaf9SAlex Deucher */ 514d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 515d38ceaf9SAlex Deucher { 516d38ceaf9SAlex Deucher return 0; 517d38ceaf9SAlex Deucher } 518d38ceaf9SAlex Deucher 519d38ceaf9SAlex Deucher /** 520d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 521d38ceaf9SAlex Deucher * for all possible rings. 522d38ceaf9SAlex Deucher * 523d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 524d38ceaf9SAlex Deucher * 525d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 526d38ceaf9SAlex Deucher */ 527d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 528d38ceaf9SAlex Deucher { 529c89377d1SChristian König unsigned i, j; 530c89377d1SChristian König int r; 531d38ceaf9SAlex Deucher 532d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 533d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 534c2776afeSChristian König 535d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 536d38ceaf9SAlex Deucher continue; 537d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 538d38ceaf9SAlex Deucher if (r) { 539d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 5402f9d4084SMonk Liu amdgpu_fence_driver_force_completion(ring); 541d38ceaf9SAlex Deucher } 54255611b50SJack Xiao if (ring->fence_drv.irq_src) 543c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 544c6a4079bSChunming Zhou ring->fence_drv.irq_type); 545730c2eb9SAlex Deucher if (!ring->no_scheduler) 5461b1f42d8SLucas Stach drm_sched_fini(&ring->sched); 5478c5e13ecSAndrey Grodzovsky del_timer_sync(&ring->fence_drv.fallback_timer); 548c89377d1SChristian König for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 549f54d1867SChris Wilson dma_fence_put(ring->fence_drv.fences[j]); 550c89377d1SChristian König kfree(ring->fence_drv.fences); 55154ddf3a6SGrazvydas Ignotas ring->fence_drv.fences = NULL; 552d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 553d38ceaf9SAlex Deucher } 554d38ceaf9SAlex Deucher } 555d38ceaf9SAlex Deucher 556d38ceaf9SAlex Deucher /** 5575ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 5585ceb54c6SAlex Deucher * for all possible rings. 5595ceb54c6SAlex Deucher * 5605ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5615ceb54c6SAlex Deucher * 5625ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 5635ceb54c6SAlex Deucher */ 5645ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 5655ceb54c6SAlex Deucher { 5665ceb54c6SAlex Deucher int i, r; 5675ceb54c6SAlex Deucher 5685ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 5695ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 5705ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 5715ceb54c6SAlex Deucher continue; 5725ceb54c6SAlex Deucher 5735ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 5745ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 5755ceb54c6SAlex Deucher if (r) { 5765ceb54c6SAlex Deucher /* delay GPU reset to resume */ 5772f9d4084SMonk Liu amdgpu_fence_driver_force_completion(ring); 5785ceb54c6SAlex Deucher } 5795ceb54c6SAlex Deucher 5805ceb54c6SAlex Deucher /* disable the interrupt */ 58155611b50SJack Xiao if (ring->fence_drv.irq_src) 5825ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 5835ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5845ceb54c6SAlex Deucher } 5855ceb54c6SAlex Deucher } 5865ceb54c6SAlex Deucher 5875ceb54c6SAlex Deucher /** 5885ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 5895ceb54c6SAlex Deucher * for all possible rings. 5905ceb54c6SAlex Deucher * 5915ceb54c6SAlex Deucher * @adev: amdgpu device pointer 5925ceb54c6SAlex Deucher * 5935ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 5945ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 5955ceb54c6SAlex Deucher * start the fence driver on the rings it has using 5965ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 5975ceb54c6SAlex Deucher * Returns 0 for success. 5985ceb54c6SAlex Deucher */ 5995ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 6005ceb54c6SAlex Deucher { 6015ceb54c6SAlex Deucher int i; 6025ceb54c6SAlex Deucher 6035ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 6045ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 6055ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 6065ceb54c6SAlex Deucher continue; 6075ceb54c6SAlex Deucher 6085ceb54c6SAlex Deucher /* enable the interrupt */ 60955611b50SJack Xiao if (ring->fence_drv.irq_src) 6105ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 6115ceb54c6SAlex Deucher ring->fence_drv.irq_type); 6125ceb54c6SAlex Deucher } 6135ceb54c6SAlex Deucher } 6145ceb54c6SAlex Deucher 6155ceb54c6SAlex Deucher /** 6162f9d4084SMonk Liu * amdgpu_fence_driver_force_completion - force signal latest fence of ring 617d38ceaf9SAlex Deucher * 6182f9d4084SMonk Liu * @ring: fence of the ring to signal 619d38ceaf9SAlex Deucher * 620d38ceaf9SAlex Deucher */ 6212f9d4084SMonk Liu void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) 622d38ceaf9SAlex Deucher { 6235907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 6242f9d4084SMonk Liu amdgpu_fence_process(ring); 62565781c78SMonk Liu } 62665781c78SMonk Liu 627a95e2642SChristian König /* 628a95e2642SChristian König * Common fence implementation 629a95e2642SChristian König */ 630a95e2642SChristian König 631f54d1867SChris Wilson static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence) 632a95e2642SChristian König { 633a95e2642SChristian König return "amdgpu"; 634a95e2642SChristian König } 635a95e2642SChristian König 636f54d1867SChris Wilson static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f) 637a95e2642SChristian König { 638a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 639a95e2642SChristian König return (const char *)fence->ring->name; 640a95e2642SChristian König } 641a95e2642SChristian König 642a95e2642SChristian König /** 6438c5e13ecSAndrey Grodzovsky * amdgpu_fence_enable_signaling - enable signalling on fence 6448c5e13ecSAndrey Grodzovsky * @fence: fence 6458c5e13ecSAndrey Grodzovsky * 6468c5e13ecSAndrey Grodzovsky * This function is called with fence_queue lock held, and adds a callback 6478c5e13ecSAndrey Grodzovsky * to fence_queue that checks if this fence is signaled, and if so it 6488c5e13ecSAndrey Grodzovsky * signals the fence and removes itself. 6498c5e13ecSAndrey Grodzovsky */ 6508c5e13ecSAndrey Grodzovsky static bool amdgpu_fence_enable_signaling(struct dma_fence *f) 6518c5e13ecSAndrey Grodzovsky { 6528c5e13ecSAndrey Grodzovsky struct amdgpu_fence *fence = to_amdgpu_fence(f); 6538c5e13ecSAndrey Grodzovsky struct amdgpu_ring *ring = fence->ring; 6548c5e13ecSAndrey Grodzovsky 6558c5e13ecSAndrey Grodzovsky if (!timer_pending(&ring->fence_drv.fallback_timer)) 6568c5e13ecSAndrey Grodzovsky amdgpu_fence_schedule_fallback(ring); 6578c5e13ecSAndrey Grodzovsky 6588c5e13ecSAndrey Grodzovsky DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 6598c5e13ecSAndrey Grodzovsky 6608c5e13ecSAndrey Grodzovsky return true; 6618c5e13ecSAndrey Grodzovsky } 6628c5e13ecSAndrey Grodzovsky 6638c5e13ecSAndrey Grodzovsky /** 664b4413535SChristian König * amdgpu_fence_free - free up the fence memory 665b4413535SChristian König * 666b4413535SChristian König * @rcu: RCU callback head 667b4413535SChristian König * 668b4413535SChristian König * Free up the fence memory after the RCU grace period. 669b4413535SChristian König */ 670b4413535SChristian König static void amdgpu_fence_free(struct rcu_head *rcu) 671b49c84a5SChunming Zhou { 672f54d1867SChris Wilson struct dma_fence *f = container_of(rcu, struct dma_fence, rcu); 673b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 674b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 675b49c84a5SChunming Zhou } 676b49c84a5SChunming Zhou 677b4413535SChristian König /** 678b4413535SChristian König * amdgpu_fence_release - callback that fence can be freed 679b4413535SChristian König * 680b4413535SChristian König * @fence: fence 681b4413535SChristian König * 682b4413535SChristian König * This function is called when the reference count becomes zero. 683b4413535SChristian König * It just RCU schedules freeing up the fence. 684b4413535SChristian König */ 685f54d1867SChris Wilson static void amdgpu_fence_release(struct dma_fence *f) 686b4413535SChristian König { 687b4413535SChristian König call_rcu(&f->rcu, amdgpu_fence_free); 688b4413535SChristian König } 689b4413535SChristian König 690f54d1867SChris Wilson static const struct dma_fence_ops amdgpu_fence_ops = { 691a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 692a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 6938c5e13ecSAndrey Grodzovsky .enable_signaling = amdgpu_fence_enable_signaling, 694b49c84a5SChunming Zhou .release = amdgpu_fence_release, 695a95e2642SChristian König }; 696d38ceaf9SAlex Deucher 697d38ceaf9SAlex Deucher /* 698d38ceaf9SAlex Deucher * Fence debugfs 699d38ceaf9SAlex Deucher */ 700d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 701d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 702d38ceaf9SAlex Deucher { 703d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 704d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 705d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 7065907a0d8SChristian König int i; 707d38ceaf9SAlex Deucher 708d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 709d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 710d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 711d38ceaf9SAlex Deucher continue; 712d38ceaf9SAlex Deucher 713d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 714d38ceaf9SAlex Deucher 715344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 716742c085fSChristian König seq_printf(m, "Last signaled fence 0x%08x\n", 717742c085fSChristian König atomic_read(&ring->fence_drv.last_seq)); 718742c085fSChristian König seq_printf(m, "Last emitted 0x%08x\n", 7195907a0d8SChristian König ring->fence_drv.sync_seq); 720e71de076Spding 721ef3e1323SJack Xiao if (ring->funcs->type == AMDGPU_RING_TYPE_GFX || 722ef3e1323SJack Xiao ring->funcs->type == AMDGPU_RING_TYPE_SDMA) { 723ef3e1323SJack Xiao seq_printf(m, "Last signaled trailing fence 0x%08x\n", 724ef3e1323SJack Xiao le32_to_cpu(*ring->trail_fence_cpu_addr)); 725ef3e1323SJack Xiao seq_printf(m, "Last emitted 0x%08x\n", 726ef3e1323SJack Xiao ring->trail_seq); 727ef3e1323SJack Xiao } 728ef3e1323SJack Xiao 729e71de076Spding if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 730e71de076Spding continue; 731e71de076Spding 732e71de076Spding /* set in CP_VMID_PREEMPT and preemption occurred */ 733e71de076Spding seq_printf(m, "Last preempted 0x%08x\n", 734e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); 735e71de076Spding /* set in CP_VMID_RESET and reset occurred */ 736e71de076Spding seq_printf(m, "Last reset 0x%08x\n", 737e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); 738e71de076Spding /* Both preemption and reset occurred */ 739e71de076Spding seq_printf(m, "Last both 0x%08x\n", 740e71de076Spding le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); 741d38ceaf9SAlex Deucher } 742d38ceaf9SAlex Deucher return 0; 743d38ceaf9SAlex Deucher } 744d38ceaf9SAlex Deucher 74518db89b4SAlex Deucher /** 7465740682eSMonk Liu * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover 74718db89b4SAlex Deucher * 74818db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 74918db89b4SAlex Deucher */ 7505740682eSMonk Liu static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) 75118db89b4SAlex Deucher { 75218db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 75318db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 75418db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 755a9ffe2a9SAlex Deucher int r; 756a9ffe2a9SAlex Deucher 757a9ffe2a9SAlex Deucher r = pm_runtime_get_sync(dev->dev); 758a9ffe2a9SAlex Deucher if (r < 0) 759a9ffe2a9SAlex Deucher return 0; 76018db89b4SAlex Deucher 7615740682eSMonk Liu seq_printf(m, "gpu recover\n"); 76212938fadSChristian König amdgpu_device_gpu_recover(adev, NULL); 76318db89b4SAlex Deucher 764a9ffe2a9SAlex Deucher pm_runtime_mark_last_busy(dev->dev); 765a9ffe2a9SAlex Deucher pm_runtime_put_autosuspend(dev->dev); 766a9ffe2a9SAlex Deucher 76718db89b4SAlex Deucher return 0; 76818db89b4SAlex Deucher } 76918db89b4SAlex Deucher 77006ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 771d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 7725740682eSMonk Liu {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} 773d38ceaf9SAlex Deucher }; 7744fbf87e2SMonk Liu 7754fbf87e2SMonk Liu static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { 7764fbf87e2SMonk Liu {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 7774fbf87e2SMonk Liu }; 778d38ceaf9SAlex Deucher #endif 779d38ceaf9SAlex Deucher 780d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 781d38ceaf9SAlex Deucher { 782d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 7834fbf87e2SMonk Liu if (amdgpu_sriov_vf(adev)) 7844fbf87e2SMonk Liu return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1); 78518db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 786d38ceaf9SAlex Deucher #else 787d38ceaf9SAlex Deucher return 0; 788d38ceaf9SAlex Deucher #endif 789d38ceaf9SAlex Deucher } 790d38ceaf9SAlex Deucher 791