1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2009 Jerome Glisse. 3d38ceaf9SAlex Deucher * All Rights Reserved. 4d38ceaf9SAlex Deucher * 5d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 6d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the 7d38ceaf9SAlex Deucher * "Software"), to deal in the Software without restriction, including 8d38ceaf9SAlex Deucher * without limitation the rights to use, copy, modify, merge, publish, 9d38ceaf9SAlex Deucher * distribute, sub license, and/or sell copies of the Software, and to 10d38ceaf9SAlex Deucher * permit persons to whom the Software is furnished to do so, subject to 11d38ceaf9SAlex Deucher * the following conditions: 12d38ceaf9SAlex Deucher * 13d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17d38ceaf9SAlex Deucher * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18d38ceaf9SAlex Deucher * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19d38ceaf9SAlex Deucher * USE OR OTHER DEALINGS IN THE SOFTWARE. 20d38ceaf9SAlex Deucher * 21d38ceaf9SAlex Deucher * The above copyright notice and this permission notice (including the 22d38ceaf9SAlex Deucher * next paragraph) shall be included in all copies or substantial portions 23d38ceaf9SAlex Deucher * of the Software. 24d38ceaf9SAlex Deucher * 25d38ceaf9SAlex Deucher */ 26d38ceaf9SAlex Deucher /* 27d38ceaf9SAlex Deucher * Authors: 28d38ceaf9SAlex Deucher * Jerome Glisse <glisse@freedesktop.org> 29d38ceaf9SAlex Deucher * Dave Airlie 30d38ceaf9SAlex Deucher */ 31d38ceaf9SAlex Deucher #include <linux/seq_file.h> 32d38ceaf9SAlex Deucher #include <linux/atomic.h> 33d38ceaf9SAlex Deucher #include <linux/wait.h> 34d38ceaf9SAlex Deucher #include <linux/kref.h> 35d38ceaf9SAlex Deucher #include <linux/slab.h> 36d38ceaf9SAlex Deucher #include <linux/firmware.h> 37d38ceaf9SAlex Deucher #include <drm/drmP.h> 38d38ceaf9SAlex Deucher #include "amdgpu.h" 39d38ceaf9SAlex Deucher #include "amdgpu_trace.h" 40d38ceaf9SAlex Deucher 41d38ceaf9SAlex Deucher /* 42d38ceaf9SAlex Deucher * Fences 43d38ceaf9SAlex Deucher * Fences mark an event in the GPUs pipeline and are used 44d38ceaf9SAlex Deucher * for GPU/CPU synchronization. When the fence is written, 45d38ceaf9SAlex Deucher * it is expected that all buffers associated with that fence 46d38ceaf9SAlex Deucher * are no longer in use by the associated ring on the GPU and 47d38ceaf9SAlex Deucher * that the the relevant GPU caches have been flushed. 48d38ceaf9SAlex Deucher */ 49d38ceaf9SAlex Deucher 5022e5a2f4SChristian König struct amdgpu_fence { 5122e5a2f4SChristian König struct fence base; 5222e5a2f4SChristian König 5322e5a2f4SChristian König /* RB, DMA, etc. */ 5422e5a2f4SChristian König struct amdgpu_ring *ring; 5522e5a2f4SChristian König }; 5622e5a2f4SChristian König 57b49c84a5SChunming Zhou static struct kmem_cache *amdgpu_fence_slab; 58b49c84a5SChunming Zhou static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0); 59b49c84a5SChunming Zhou 6022e5a2f4SChristian König /* 6122e5a2f4SChristian König * Cast helper 6222e5a2f4SChristian König */ 6322e5a2f4SChristian König static const struct fence_ops amdgpu_fence_ops; 6422e5a2f4SChristian König static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 6522e5a2f4SChristian König { 6622e5a2f4SChristian König struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 6722e5a2f4SChristian König 6822e5a2f4SChristian König if (__f->base.ops == &amdgpu_fence_ops) 6922e5a2f4SChristian König return __f; 7022e5a2f4SChristian König 7122e5a2f4SChristian König return NULL; 7222e5a2f4SChristian König } 7322e5a2f4SChristian König 74d38ceaf9SAlex Deucher /** 75d38ceaf9SAlex Deucher * amdgpu_fence_write - write a fence value 76d38ceaf9SAlex Deucher * 77d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 78d38ceaf9SAlex Deucher * @seq: sequence number to write 79d38ceaf9SAlex Deucher * 80d38ceaf9SAlex Deucher * Writes a fence value to memory (all asics). 81d38ceaf9SAlex Deucher */ 82d38ceaf9SAlex Deucher static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq) 83d38ceaf9SAlex Deucher { 84d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 85d38ceaf9SAlex Deucher 86d38ceaf9SAlex Deucher if (drv->cpu_addr) 87d38ceaf9SAlex Deucher *drv->cpu_addr = cpu_to_le32(seq); 88d38ceaf9SAlex Deucher } 89d38ceaf9SAlex Deucher 90d38ceaf9SAlex Deucher /** 91d38ceaf9SAlex Deucher * amdgpu_fence_read - read a fence value 92d38ceaf9SAlex Deucher * 93d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 94d38ceaf9SAlex Deucher * 95d38ceaf9SAlex Deucher * Reads a fence value from memory (all asics). 96d38ceaf9SAlex Deucher * Returns the value of the fence read from memory. 97d38ceaf9SAlex Deucher */ 98d38ceaf9SAlex Deucher static u32 amdgpu_fence_read(struct amdgpu_ring *ring) 99d38ceaf9SAlex Deucher { 100d38ceaf9SAlex Deucher struct amdgpu_fence_driver *drv = &ring->fence_drv; 101d38ceaf9SAlex Deucher u32 seq = 0; 102d38ceaf9SAlex Deucher 103d38ceaf9SAlex Deucher if (drv->cpu_addr) 104d38ceaf9SAlex Deucher seq = le32_to_cpu(*drv->cpu_addr); 105d38ceaf9SAlex Deucher else 106742c085fSChristian König seq = atomic_read(&drv->last_seq); 107d38ceaf9SAlex Deucher 108d38ceaf9SAlex Deucher return seq; 109d38ceaf9SAlex Deucher } 110d38ceaf9SAlex Deucher 111d38ceaf9SAlex Deucher /** 112d38ceaf9SAlex Deucher * amdgpu_fence_emit - emit a fence on the requested ring 113d38ceaf9SAlex Deucher * 114d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 115364beb2cSChristian König * @f: resulting fence object 116d38ceaf9SAlex Deucher * 117d38ceaf9SAlex Deucher * Emits a fence command on the requested ring (all asics). 118d38ceaf9SAlex Deucher * Returns 0 on success, -ENOMEM on failure. 119d38ceaf9SAlex Deucher */ 120364beb2cSChristian König int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f) 121d38ceaf9SAlex Deucher { 122d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 123364beb2cSChristian König struct amdgpu_fence *fence; 124fc387a0bSChunming Zhou struct fence *old, **ptr; 125742c085fSChristian König uint32_t seq; 126d38ceaf9SAlex Deucher 127364beb2cSChristian König fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 128364beb2cSChristian König if (fence == NULL) 129d38ceaf9SAlex Deucher return -ENOMEM; 130364beb2cSChristian König 131742c085fSChristian König seq = ++ring->fence_drv.sync_seq; 132364beb2cSChristian König fence->ring = ring; 133364beb2cSChristian König fence_init(&fence->base, &amdgpu_fence_ops, 1344a7d74f1SChristian König &ring->fence_drv.lock, 1357f06c236Smonk.liu adev->fence_context + ring->idx, 136742c085fSChristian König seq); 137890ee23fSChunming Zhou amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 138742c085fSChristian König seq, AMDGPU_FENCE_FLAG_INT); 139c89377d1SChristian König 140742c085fSChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 141c89377d1SChristian König /* This function can't be called concurrently anyway, otherwise 142c89377d1SChristian König * emitting the fence would mess up the hardware ring buffer. 143c89377d1SChristian König */ 144fc387a0bSChunming Zhou old = rcu_dereference_protected(*ptr, 1); 145fc387a0bSChunming Zhou if (old && !fence_is_signaled(old)) { 146fc387a0bSChunming Zhou DRM_INFO("rcu slot is busy\n"); 147fc387a0bSChunming Zhou fence_wait(old, false); 148fc387a0bSChunming Zhou } 149c89377d1SChristian König 150c89377d1SChristian König rcu_assign_pointer(*ptr, fence_get(&fence->base)); 151c89377d1SChristian König 152364beb2cSChristian König *f = &fence->base; 153c89377d1SChristian König 154d38ceaf9SAlex Deucher return 0; 155d38ceaf9SAlex Deucher } 156d38ceaf9SAlex Deucher 157d38ceaf9SAlex Deucher /** 158c2776afeSChristian König * amdgpu_fence_schedule_fallback - schedule fallback check 159c2776afeSChristian König * 160c2776afeSChristian König * @ring: pointer to struct amdgpu_ring 161c2776afeSChristian König * 162c2776afeSChristian König * Start a timer as fallback to our interrupts. 163c2776afeSChristian König */ 164c2776afeSChristian König static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 165c2776afeSChristian König { 166c2776afeSChristian König mod_timer(&ring->fence_drv.fallback_timer, 167c2776afeSChristian König jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 168c2776afeSChristian König } 169c2776afeSChristian König 170c2776afeSChristian König /** 171ca08e04dSChristian König * amdgpu_fence_process - check for fence activity 172d38ceaf9SAlex Deucher * 173d38ceaf9SAlex Deucher * @ring: pointer to struct amdgpu_ring 174d38ceaf9SAlex Deucher * 175d38ceaf9SAlex Deucher * Checks the current fence value and calculates the last 176ca08e04dSChristian König * signalled fence value. Wakes the fence queue if the 177ca08e04dSChristian König * sequence number has increased. 178d38ceaf9SAlex Deucher */ 179ca08e04dSChristian König void amdgpu_fence_process(struct amdgpu_ring *ring) 180d38ceaf9SAlex Deucher { 1814a7d74f1SChristian König struct amdgpu_fence_driver *drv = &ring->fence_drv; 182742c085fSChristian König uint32_t seq, last_seq; 1834a7d74f1SChristian König int r; 184d38ceaf9SAlex Deucher 185d38ceaf9SAlex Deucher do { 186742c085fSChristian König last_seq = atomic_read(&ring->fence_drv.last_seq); 187d38ceaf9SAlex Deucher seq = amdgpu_fence_read(ring); 188d38ceaf9SAlex Deucher 189742c085fSChristian König } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 190d38ceaf9SAlex Deucher 191742c085fSChristian König if (seq != ring->fence_drv.sync_seq) 192c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 193d38ceaf9SAlex Deucher 1944a7d74f1SChristian König while (last_seq != seq) { 1954a7d74f1SChristian König struct fence *fence, **ptr; 1964a7d74f1SChristian König 1974a7d74f1SChristian König ptr = &drv->fences[++last_seq & drv->num_fences_mask]; 1984a7d74f1SChristian König 1994a7d74f1SChristian König /* There is always exactly one thread signaling this fence slot */ 2004a7d74f1SChristian König fence = rcu_dereference_protected(*ptr, 1); 2014a7d74f1SChristian König rcu_assign_pointer(*ptr, NULL); 2024a7d74f1SChristian König 2034a7d74f1SChristian König BUG_ON(!fence); 2044a7d74f1SChristian König 2054a7d74f1SChristian König r = fence_signal(fence); 2064a7d74f1SChristian König if (!r) 2074a7d74f1SChristian König FENCE_TRACE(fence, "signaled from irq context\n"); 2084a7d74f1SChristian König else 2094a7d74f1SChristian König BUG(); 2104a7d74f1SChristian König 2114a7d74f1SChristian König fence_put(fence); 2124a7d74f1SChristian König } 213e0d8f3c3SChunming Zhou } 214d38ceaf9SAlex Deucher 215d38ceaf9SAlex Deucher /** 216c2776afeSChristian König * amdgpu_fence_fallback - fallback for hardware interrupts 217c2776afeSChristian König * 218c2776afeSChristian König * @work: delayed work item 219c2776afeSChristian König * 220c2776afeSChristian König * Checks for fence activity. 221c2776afeSChristian König */ 222c2776afeSChristian König static void amdgpu_fence_fallback(unsigned long arg) 223c2776afeSChristian König { 224c2776afeSChristian König struct amdgpu_ring *ring = (void *)arg; 225c2776afeSChristian König 226c2776afeSChristian König amdgpu_fence_process(ring); 227c2776afeSChristian König } 228c2776afeSChristian König 229c2776afeSChristian König /** 230d38ceaf9SAlex Deucher * amdgpu_fence_wait_empty - wait for all fences to signal 231d38ceaf9SAlex Deucher * 232d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 233d38ceaf9SAlex Deucher * @ring: ring index the fence is associated with 234d38ceaf9SAlex Deucher * 235d38ceaf9SAlex Deucher * Wait for all fences on the requested ring to signal (all asics). 236d38ceaf9SAlex Deucher * Returns 0 if the fences have passed, error for all other cases. 237d38ceaf9SAlex Deucher */ 238d38ceaf9SAlex Deucher int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) 239d38ceaf9SAlex Deucher { 240f09c2be4SChristian König uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq); 241f09c2be4SChristian König struct fence *fence, **ptr; 242f09c2be4SChristian König int r; 24300d2a2b2SChristian König 2447f06c236Smonk.liu if (!seq) 245d38ceaf9SAlex Deucher return 0; 246d38ceaf9SAlex Deucher 247f09c2be4SChristian König ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; 248f09c2be4SChristian König rcu_read_lock(); 249f09c2be4SChristian König fence = rcu_dereference(*ptr); 250f09c2be4SChristian König if (!fence || !fence_get_rcu(fence)) { 251f09c2be4SChristian König rcu_read_unlock(); 252f09c2be4SChristian König return 0; 253f09c2be4SChristian König } 254f09c2be4SChristian König rcu_read_unlock(); 255f09c2be4SChristian König 256f09c2be4SChristian König r = fence_wait(fence, false); 257f09c2be4SChristian König fence_put(fence); 258f09c2be4SChristian König return r; 259d38ceaf9SAlex Deucher } 260d38ceaf9SAlex Deucher 261d38ceaf9SAlex Deucher /** 262d38ceaf9SAlex Deucher * amdgpu_fence_count_emitted - get the count of emitted fences 263d38ceaf9SAlex Deucher * 264d38ceaf9SAlex Deucher * @ring: ring the fence is associated with 265d38ceaf9SAlex Deucher * 266d38ceaf9SAlex Deucher * Get the number of fences emitted on the requested ring (all asics). 267d38ceaf9SAlex Deucher * Returns the number of emitted fences on the ring. Used by the 268d38ceaf9SAlex Deucher * dynpm code to ring track activity. 269d38ceaf9SAlex Deucher */ 270d38ceaf9SAlex Deucher unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) 271d38ceaf9SAlex Deucher { 272d38ceaf9SAlex Deucher uint64_t emitted; 273d38ceaf9SAlex Deucher 274d38ceaf9SAlex Deucher /* We are not protected by ring lock when reading the last sequence 275d38ceaf9SAlex Deucher * but it's ok to report slightly wrong fence count here. 276d38ceaf9SAlex Deucher */ 277d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 278742c085fSChristian König emitted = 0x100000000ull; 279742c085fSChristian König emitted -= atomic_read(&ring->fence_drv.last_seq); 280742c085fSChristian König emitted += ACCESS_ONCE(ring->fence_drv.sync_seq); 281742c085fSChristian König return lower_32_bits(emitted); 282d38ceaf9SAlex Deucher } 283d38ceaf9SAlex Deucher 284d38ceaf9SAlex Deucher /** 285d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring - make the fence driver 286d38ceaf9SAlex Deucher * ready for use on the requested ring. 287d38ceaf9SAlex Deucher * 288d38ceaf9SAlex Deucher * @ring: ring to start the fence driver on 289d38ceaf9SAlex Deucher * @irq_src: interrupt source to use for this ring 290d38ceaf9SAlex Deucher * @irq_type: interrupt type to use for this ring 291d38ceaf9SAlex Deucher * 292d38ceaf9SAlex Deucher * Make the fence driver ready for processing (all asics). 293d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 294d38ceaf9SAlex Deucher * start the fence driver on the rings it has. 295d38ceaf9SAlex Deucher * Returns 0 for success, errors for failure. 296d38ceaf9SAlex Deucher */ 297d38ceaf9SAlex Deucher int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 298d38ceaf9SAlex Deucher struct amdgpu_irq_src *irq_src, 299d38ceaf9SAlex Deucher unsigned irq_type) 300d38ceaf9SAlex Deucher { 301d38ceaf9SAlex Deucher struct amdgpu_device *adev = ring->adev; 302d38ceaf9SAlex Deucher uint64_t index; 303d38ceaf9SAlex Deucher 304d38ceaf9SAlex Deucher if (ring != &adev->uvd.ring) { 305d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs]; 306d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); 307d38ceaf9SAlex Deucher } else { 308d38ceaf9SAlex Deucher /* put fence directly behind firmware */ 309d38ceaf9SAlex Deucher index = ALIGN(adev->uvd.fw->size, 8); 310d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index; 311d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; 312d38ceaf9SAlex Deucher } 313742c085fSChristian König amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 314c6a4079bSChunming Zhou amdgpu_irq_get(adev, irq_src, irq_type); 315c6a4079bSChunming Zhou 316d38ceaf9SAlex Deucher ring->fence_drv.irq_src = irq_src; 317d38ceaf9SAlex Deucher ring->fence_drv.irq_type = irq_type; 318c6a4079bSChunming Zhou ring->fence_drv.initialized = true; 319c6a4079bSChunming Zhou 320d38ceaf9SAlex Deucher dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " 321d38ceaf9SAlex Deucher "cpu addr 0x%p\n", ring->idx, 322d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); 323d38ceaf9SAlex Deucher return 0; 324d38ceaf9SAlex Deucher } 325d38ceaf9SAlex Deucher 326d38ceaf9SAlex Deucher /** 327d38ceaf9SAlex Deucher * amdgpu_fence_driver_init_ring - init the fence driver 328d38ceaf9SAlex Deucher * for the requested ring. 329d38ceaf9SAlex Deucher * 330d38ceaf9SAlex Deucher * @ring: ring to init the fence driver on 331e6151a08SChristian König * @num_hw_submission: number of entries on the hardware queue 332d38ceaf9SAlex Deucher * 333d38ceaf9SAlex Deucher * Init the fence driver for the requested ring (all asics). 334d38ceaf9SAlex Deucher * Helper function for amdgpu_fence_driver_init(). 335d38ceaf9SAlex Deucher */ 336e6151a08SChristian König int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 337e6151a08SChristian König unsigned num_hw_submission) 338d38ceaf9SAlex Deucher { 339cadf97b1SChunming Zhou long timeout; 3405907a0d8SChristian König int r; 341d38ceaf9SAlex Deucher 342e6151a08SChristian König /* Check that num_hw_submission is a power of two */ 343e6151a08SChristian König if ((num_hw_submission & (num_hw_submission - 1)) != 0) 344e6151a08SChristian König return -EINVAL; 345e6151a08SChristian König 346d38ceaf9SAlex Deucher ring->fence_drv.cpu_addr = NULL; 347d38ceaf9SAlex Deucher ring->fence_drv.gpu_addr = 0; 3485907a0d8SChristian König ring->fence_drv.sync_seq = 0; 349742c085fSChristian König atomic_set(&ring->fence_drv.last_seq, 0); 350d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 351d38ceaf9SAlex Deucher 352c2776afeSChristian König setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 353c2776afeSChristian König (unsigned long)ring); 354b80d8475SAlex Deucher 35566067ad7SChunming Zhou ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1; 3564a7d74f1SChristian König spin_lock_init(&ring->fence_drv.lock); 35766067ad7SChunming Zhou ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *), 358c89377d1SChristian König GFP_KERNEL); 359c89377d1SChristian König if (!ring->fence_drv.fences) 360c89377d1SChristian König return -ENOMEM; 3615ec92a76SChristian König 362cadf97b1SChunming Zhou timeout = msecs_to_jiffies(amdgpu_lockup_timeout); 3632440ff2cSJunwei Zhang if (timeout == 0) { 3642440ff2cSJunwei Zhang /* 3652440ff2cSJunwei Zhang * FIXME: 3662440ff2cSJunwei Zhang * Delayed workqueue cannot use it directly, 3672440ff2cSJunwei Zhang * so the scheduler will not use delayed workqueue if 3682440ff2cSJunwei Zhang * MAX_SCHEDULE_TIMEOUT is set. 3692440ff2cSJunwei Zhang * Currently keep it simple and silly. 3702440ff2cSJunwei Zhang */ 3712440ff2cSJunwei Zhang timeout = MAX_SCHEDULE_TIMEOUT; 3722440ff2cSJunwei Zhang } 3734f839a24SChristian König r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, 374e6151a08SChristian König num_hw_submission, 3752440ff2cSJunwei Zhang timeout, ring->name); 3764f839a24SChristian König if (r) { 3774f839a24SChristian König DRM_ERROR("Failed to create scheduler on ring %s.\n", 3784f839a24SChristian König ring->name); 3794f839a24SChristian König return r; 380b80d8475SAlex Deucher } 381d38ceaf9SAlex Deucher 3824f839a24SChristian König return 0; 3834f839a24SChristian König } 3844f839a24SChristian König 385d38ceaf9SAlex Deucher /** 386d38ceaf9SAlex Deucher * amdgpu_fence_driver_init - init the fence driver 387d38ceaf9SAlex Deucher * for all possible rings. 388d38ceaf9SAlex Deucher * 389d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 390d38ceaf9SAlex Deucher * 391d38ceaf9SAlex Deucher * Init the fence driver for all possible rings (all asics). 392d38ceaf9SAlex Deucher * Not all asics have all rings, so each asic will only 393d38ceaf9SAlex Deucher * start the fence driver on the rings it has using 394d38ceaf9SAlex Deucher * amdgpu_fence_driver_start_ring(). 395d38ceaf9SAlex Deucher * Returns 0 for success. 396d38ceaf9SAlex Deucher */ 397d38ceaf9SAlex Deucher int amdgpu_fence_driver_init(struct amdgpu_device *adev) 398d38ceaf9SAlex Deucher { 399b49c84a5SChunming Zhou if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) { 400b49c84a5SChunming Zhou amdgpu_fence_slab = kmem_cache_create( 401b49c84a5SChunming Zhou "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 402b49c84a5SChunming Zhou SLAB_HWCACHE_ALIGN, NULL); 403b49c84a5SChunming Zhou if (!amdgpu_fence_slab) 404b49c84a5SChunming Zhou return -ENOMEM; 405b49c84a5SChunming Zhou } 406d38ceaf9SAlex Deucher if (amdgpu_debugfs_fence_init(adev)) 407d38ceaf9SAlex Deucher dev_err(adev->dev, "fence debugfs file creation failed\n"); 408d38ceaf9SAlex Deucher 409d38ceaf9SAlex Deucher return 0; 410d38ceaf9SAlex Deucher } 411d38ceaf9SAlex Deucher 412d38ceaf9SAlex Deucher /** 413d38ceaf9SAlex Deucher * amdgpu_fence_driver_fini - tear down the fence driver 414d38ceaf9SAlex Deucher * for all possible rings. 415d38ceaf9SAlex Deucher * 416d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 417d38ceaf9SAlex Deucher * 418d38ceaf9SAlex Deucher * Tear down the fence driver for all possible rings (all asics). 419d38ceaf9SAlex Deucher */ 420d38ceaf9SAlex Deucher void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 421d38ceaf9SAlex Deucher { 422c89377d1SChristian König unsigned i, j; 423c89377d1SChristian König int r; 424d38ceaf9SAlex Deucher 425d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 426d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 427c2776afeSChristian König 428d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 429d38ceaf9SAlex Deucher continue; 430d38ceaf9SAlex Deucher r = amdgpu_fence_wait_empty(ring); 431d38ceaf9SAlex Deucher if (r) { 432d38ceaf9SAlex Deucher /* no need to trigger GPU reset as we are unloading */ 433d38ceaf9SAlex Deucher amdgpu_fence_driver_force_completion(adev); 434d38ceaf9SAlex Deucher } 435c6a4079bSChunming Zhou amdgpu_irq_put(adev, ring->fence_drv.irq_src, 436c6a4079bSChunming Zhou ring->fence_drv.irq_type); 4374f839a24SChristian König amd_sched_fini(&ring->sched); 438c2776afeSChristian König del_timer_sync(&ring->fence_drv.fallback_timer); 439c89377d1SChristian König for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j) 440c89377d1SChristian König fence_put(ring->fence_drv.fences[i]); 441c89377d1SChristian König kfree(ring->fence_drv.fences); 442d38ceaf9SAlex Deucher ring->fence_drv.initialized = false; 443d38ceaf9SAlex Deucher } 444c89377d1SChristian König 445c89377d1SChristian König if (atomic_dec_and_test(&amdgpu_fence_slab_ref)) 446c89377d1SChristian König kmem_cache_destroy(amdgpu_fence_slab); 447d38ceaf9SAlex Deucher } 448d38ceaf9SAlex Deucher 449d38ceaf9SAlex Deucher /** 4505ceb54c6SAlex Deucher * amdgpu_fence_driver_suspend - suspend the fence driver 4515ceb54c6SAlex Deucher * for all possible rings. 4525ceb54c6SAlex Deucher * 4535ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4545ceb54c6SAlex Deucher * 4555ceb54c6SAlex Deucher * Suspend the fence driver for all possible rings (all asics). 4565ceb54c6SAlex Deucher */ 4575ceb54c6SAlex Deucher void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) 4585ceb54c6SAlex Deucher { 4595ceb54c6SAlex Deucher int i, r; 4605ceb54c6SAlex Deucher 4615ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 4625ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 4635ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 4645ceb54c6SAlex Deucher continue; 4655ceb54c6SAlex Deucher 4665ceb54c6SAlex Deucher /* wait for gpu to finish processing current batch */ 4675ceb54c6SAlex Deucher r = amdgpu_fence_wait_empty(ring); 4685ceb54c6SAlex Deucher if (r) { 4695ceb54c6SAlex Deucher /* delay GPU reset to resume */ 4705ceb54c6SAlex Deucher amdgpu_fence_driver_force_completion(adev); 4715ceb54c6SAlex Deucher } 4725ceb54c6SAlex Deucher 4735ceb54c6SAlex Deucher /* disable the interrupt */ 4745ceb54c6SAlex Deucher amdgpu_irq_put(adev, ring->fence_drv.irq_src, 4755ceb54c6SAlex Deucher ring->fence_drv.irq_type); 4765ceb54c6SAlex Deucher } 4775ceb54c6SAlex Deucher } 4785ceb54c6SAlex Deucher 4795ceb54c6SAlex Deucher /** 4805ceb54c6SAlex Deucher * amdgpu_fence_driver_resume - resume the fence driver 4815ceb54c6SAlex Deucher * for all possible rings. 4825ceb54c6SAlex Deucher * 4835ceb54c6SAlex Deucher * @adev: amdgpu device pointer 4845ceb54c6SAlex Deucher * 4855ceb54c6SAlex Deucher * Resume the fence driver for all possible rings (all asics). 4865ceb54c6SAlex Deucher * Not all asics have all rings, so each asic will only 4875ceb54c6SAlex Deucher * start the fence driver on the rings it has using 4885ceb54c6SAlex Deucher * amdgpu_fence_driver_start_ring(). 4895ceb54c6SAlex Deucher * Returns 0 for success. 4905ceb54c6SAlex Deucher */ 4915ceb54c6SAlex Deucher void amdgpu_fence_driver_resume(struct amdgpu_device *adev) 4925ceb54c6SAlex Deucher { 4935ceb54c6SAlex Deucher int i; 4945ceb54c6SAlex Deucher 4955ceb54c6SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 4965ceb54c6SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 4975ceb54c6SAlex Deucher if (!ring || !ring->fence_drv.initialized) 4985ceb54c6SAlex Deucher continue; 4995ceb54c6SAlex Deucher 5005ceb54c6SAlex Deucher /* enable the interrupt */ 5015ceb54c6SAlex Deucher amdgpu_irq_get(adev, ring->fence_drv.irq_src, 5025ceb54c6SAlex Deucher ring->fence_drv.irq_type); 5035ceb54c6SAlex Deucher } 5045ceb54c6SAlex Deucher } 5055ceb54c6SAlex Deucher 5065ceb54c6SAlex Deucher /** 507d38ceaf9SAlex Deucher * amdgpu_fence_driver_force_completion - force all fence waiter to complete 508d38ceaf9SAlex Deucher * 509d38ceaf9SAlex Deucher * @adev: amdgpu device pointer 510d38ceaf9SAlex Deucher * 511d38ceaf9SAlex Deucher * In case of GPU reset failure make sure no process keep waiting on fence 512d38ceaf9SAlex Deucher * that will never complete. 513d38ceaf9SAlex Deucher */ 514d38ceaf9SAlex Deucher void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) 515d38ceaf9SAlex Deucher { 516d38ceaf9SAlex Deucher int i; 517d38ceaf9SAlex Deucher 518d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 519d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 520d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 521d38ceaf9SAlex Deucher continue; 522d38ceaf9SAlex Deucher 5235907a0d8SChristian König amdgpu_fence_write(ring, ring->fence_drv.sync_seq); 524d38ceaf9SAlex Deucher } 525d38ceaf9SAlex Deucher } 526d38ceaf9SAlex Deucher 527a95e2642SChristian König /* 528a95e2642SChristian König * Common fence implementation 529a95e2642SChristian König */ 530a95e2642SChristian König 531a95e2642SChristian König static const char *amdgpu_fence_get_driver_name(struct fence *fence) 532a95e2642SChristian König { 533a95e2642SChristian König return "amdgpu"; 534a95e2642SChristian König } 535a95e2642SChristian König 536a95e2642SChristian König static const char *amdgpu_fence_get_timeline_name(struct fence *f) 537a95e2642SChristian König { 538a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 539a95e2642SChristian König return (const char *)fence->ring->name; 540a95e2642SChristian König } 541a95e2642SChristian König 542a95e2642SChristian König /** 543a95e2642SChristian König * amdgpu_fence_enable_signaling - enable signalling on fence 544a95e2642SChristian König * @fence: fence 545a95e2642SChristian König * 546a95e2642SChristian König * This function is called with fence_queue lock held, and adds a callback 547a95e2642SChristian König * to fence_queue that checks if this fence is signaled, and if so it 548a95e2642SChristian König * signals the fence and removes itself. 549a95e2642SChristian König */ 550a95e2642SChristian König static bool amdgpu_fence_enable_signaling(struct fence *f) 551a95e2642SChristian König { 552a95e2642SChristian König struct amdgpu_fence *fence = to_amdgpu_fence(f); 553a95e2642SChristian König struct amdgpu_ring *ring = fence->ring; 554a95e2642SChristian König 555c2776afeSChristian König if (!timer_pending(&ring->fence_drv.fallback_timer)) 556c2776afeSChristian König amdgpu_fence_schedule_fallback(ring); 5574a7d74f1SChristian König 558a95e2642SChristian König FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 5594a7d74f1SChristian König 560a95e2642SChristian König return true; 561a95e2642SChristian König } 562a95e2642SChristian König 563b4413535SChristian König /** 564b4413535SChristian König * amdgpu_fence_free - free up the fence memory 565b4413535SChristian König * 566b4413535SChristian König * @rcu: RCU callback head 567b4413535SChristian König * 568b4413535SChristian König * Free up the fence memory after the RCU grace period. 569b4413535SChristian König */ 570b4413535SChristian König static void amdgpu_fence_free(struct rcu_head *rcu) 571b49c84a5SChunming Zhou { 572b4413535SChristian König struct fence *f = container_of(rcu, struct fence, rcu); 573b49c84a5SChunming Zhou struct amdgpu_fence *fence = to_amdgpu_fence(f); 574b49c84a5SChunming Zhou kmem_cache_free(amdgpu_fence_slab, fence); 575b49c84a5SChunming Zhou } 576b49c84a5SChunming Zhou 577b4413535SChristian König /** 578b4413535SChristian König * amdgpu_fence_release - callback that fence can be freed 579b4413535SChristian König * 580b4413535SChristian König * @fence: fence 581b4413535SChristian König * 582b4413535SChristian König * This function is called when the reference count becomes zero. 583b4413535SChristian König * It just RCU schedules freeing up the fence. 584b4413535SChristian König */ 585b4413535SChristian König static void amdgpu_fence_release(struct fence *f) 586b4413535SChristian König { 587b4413535SChristian König call_rcu(&f->rcu, amdgpu_fence_free); 588b4413535SChristian König } 589b4413535SChristian König 59022e5a2f4SChristian König static const struct fence_ops amdgpu_fence_ops = { 591a95e2642SChristian König .get_driver_name = amdgpu_fence_get_driver_name, 592a95e2642SChristian König .get_timeline_name = amdgpu_fence_get_timeline_name, 593a95e2642SChristian König .enable_signaling = amdgpu_fence_enable_signaling, 594a95e2642SChristian König .wait = fence_default_wait, 595b49c84a5SChunming Zhou .release = amdgpu_fence_release, 596a95e2642SChristian König }; 597d38ceaf9SAlex Deucher 598d38ceaf9SAlex Deucher /* 599d38ceaf9SAlex Deucher * Fence debugfs 600d38ceaf9SAlex Deucher */ 601d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 602d38ceaf9SAlex Deucher static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) 603d38ceaf9SAlex Deucher { 604d38ceaf9SAlex Deucher struct drm_info_node *node = (struct drm_info_node *)m->private; 605d38ceaf9SAlex Deucher struct drm_device *dev = node->minor->dev; 606d38ceaf9SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 6075907a0d8SChristian König int i; 608d38ceaf9SAlex Deucher 609d38ceaf9SAlex Deucher for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 610d38ceaf9SAlex Deucher struct amdgpu_ring *ring = adev->rings[i]; 611d38ceaf9SAlex Deucher if (!ring || !ring->fence_drv.initialized) 612d38ceaf9SAlex Deucher continue; 613d38ceaf9SAlex Deucher 614d38ceaf9SAlex Deucher amdgpu_fence_process(ring); 615d38ceaf9SAlex Deucher 616344c19f9SChristian König seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); 617742c085fSChristian König seq_printf(m, "Last signaled fence 0x%08x\n", 618742c085fSChristian König atomic_read(&ring->fence_drv.last_seq)); 619742c085fSChristian König seq_printf(m, "Last emitted 0x%08x\n", 6205907a0d8SChristian König ring->fence_drv.sync_seq); 621d38ceaf9SAlex Deucher } 622d38ceaf9SAlex Deucher return 0; 623d38ceaf9SAlex Deucher } 624d38ceaf9SAlex Deucher 62518db89b4SAlex Deucher /** 62618db89b4SAlex Deucher * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset 62718db89b4SAlex Deucher * 62818db89b4SAlex Deucher * Manually trigger a gpu reset at the next fence wait. 62918db89b4SAlex Deucher */ 63018db89b4SAlex Deucher static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) 63118db89b4SAlex Deucher { 63218db89b4SAlex Deucher struct drm_info_node *node = (struct drm_info_node *) m->private; 63318db89b4SAlex Deucher struct drm_device *dev = node->minor->dev; 63418db89b4SAlex Deucher struct amdgpu_device *adev = dev->dev_private; 63518db89b4SAlex Deucher 63618db89b4SAlex Deucher seq_printf(m, "gpu reset\n"); 63718db89b4SAlex Deucher amdgpu_gpu_reset(adev); 63818db89b4SAlex Deucher 63918db89b4SAlex Deucher return 0; 64018db89b4SAlex Deucher } 64118db89b4SAlex Deucher 64206ab6832SNils Wallménius static const struct drm_info_list amdgpu_debugfs_fence_list[] = { 643d38ceaf9SAlex Deucher {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, 64418db89b4SAlex Deucher {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} 645d38ceaf9SAlex Deucher }; 646d38ceaf9SAlex Deucher #endif 647d38ceaf9SAlex Deucher 648d38ceaf9SAlex Deucher int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) 649d38ceaf9SAlex Deucher { 650d38ceaf9SAlex Deucher #if defined(CONFIG_DEBUG_FS) 65118db89b4SAlex Deucher return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2); 652d38ceaf9SAlex Deucher #else 653d38ceaf9SAlex Deucher return 0; 654d38ceaf9SAlex Deucher #endif 655d38ceaf9SAlex Deucher } 656d38ceaf9SAlex Deucher 657