1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/amdgpu_drm.h> 27 #include <drm/drm_gem.h> 28 #include "amdgpu_drv.h" 29 30 #include <drm/drm_pciids.h> 31 #include <linux/console.h> 32 #include <linux/module.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/vga_switcheroo.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "amdgpu.h" 38 #include "amdgpu_irq.h" 39 #include "amdgpu_dma_buf.h" 40 41 #include "amdgpu_amdkfd.h" 42 43 /* 44 * KMS wrapper. 45 * - 3.0.0 - initial driver 46 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 47 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 48 * at the end of IBs. 49 * - 3.3.0 - Add VM support for UVD on supported hardware. 50 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 51 * - 3.5.0 - Add support for new UVD_NO_OP register. 52 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 53 * - 3.7.0 - Add support for VCE clock list packet 54 * - 3.8.0 - Add support raster config init in the kernel 55 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 56 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 57 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 58 * - 3.12.0 - Add query for double offchip LDS buffers 59 * - 3.13.0 - Add PRT support 60 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 61 * - 3.15.0 - Export more gpu info for gfx9 62 * - 3.16.0 - Add reserved vmid support 63 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 64 * - 3.18.0 - Export gpu always on cu bitmap 65 * - 3.19.0 - Add support for UVD MJPEG decode 66 * - 3.20.0 - Add support for local BOs 67 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 68 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 69 * - 3.23.0 - Add query for VRAM lost counter 70 * - 3.24.0 - Add high priority compute support for gfx9 71 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 72 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 73 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 74 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 75 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 76 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 77 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 78 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 79 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 80 */ 81 #define KMS_DRIVER_MAJOR 3 82 #define KMS_DRIVER_MINOR 33 83 #define KMS_DRIVER_PATCHLEVEL 0 84 85 #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256 86 87 int amdgpu_vram_limit = 0; 88 int amdgpu_vis_vram_limit = 0; 89 int amdgpu_gart_size = -1; /* auto */ 90 int amdgpu_gtt_size = -1; /* auto */ 91 int amdgpu_moverate = -1; /* auto */ 92 int amdgpu_benchmarking = 0; 93 int amdgpu_testing = 0; 94 int amdgpu_audio = -1; 95 int amdgpu_disp_priority = 0; 96 int amdgpu_hw_i2c = 0; 97 int amdgpu_pcie_gen2 = -1; 98 int amdgpu_msi = -1; 99 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH]; 100 int amdgpu_dpm = -1; 101 int amdgpu_fw_load_type = -1; 102 int amdgpu_aspm = -1; 103 int amdgpu_runtime_pm = -1; 104 uint amdgpu_ip_block_mask = 0xffffffff; 105 int amdgpu_bapm = -1; 106 int amdgpu_deep_color = 0; 107 int amdgpu_vm_size = -1; 108 int amdgpu_vm_fragment_size = -1; 109 int amdgpu_vm_block_size = -1; 110 int amdgpu_vm_fault_stop = 0; 111 int amdgpu_vm_debug = 0; 112 int amdgpu_vm_update_mode = -1; 113 int amdgpu_exp_hw_support = 0; 114 int amdgpu_dc = -1; 115 int amdgpu_sched_jobs = 32; 116 int amdgpu_sched_hw_submission = 2; 117 uint amdgpu_pcie_gen_cap = 0; 118 uint amdgpu_pcie_lane_cap = 0; 119 uint amdgpu_cg_mask = 0xffffffff; 120 uint amdgpu_pg_mask = 0xffffffff; 121 uint amdgpu_sdma_phase_quantum = 32; 122 char *amdgpu_disable_cu = NULL; 123 char *amdgpu_virtual_display = NULL; 124 /* OverDrive(bit 14) disabled by default*/ 125 uint amdgpu_pp_feature_mask = 0xffffbfff; 126 int amdgpu_ngg = 0; 127 int amdgpu_prim_buf_per_se = 0; 128 int amdgpu_pos_buf_per_se = 0; 129 int amdgpu_cntl_sb_buf_per_se = 0; 130 int amdgpu_param_buf_per_se = 0; 131 int amdgpu_job_hang_limit = 0; 132 int amdgpu_lbpw = -1; 133 int amdgpu_compute_multipipe = -1; 134 int amdgpu_gpu_recovery = -1; /* auto */ 135 int amdgpu_emu_mode = 0; 136 uint amdgpu_smu_memory_pool_size = 0; 137 /* FBC (bit 0) disabled by default*/ 138 uint amdgpu_dc_feature_mask = 0; 139 int amdgpu_async_gfx_ring = 1; 140 int amdgpu_mcbp = 0; 141 int amdgpu_discovery = 0; 142 int amdgpu_mes = 0; 143 144 struct amdgpu_mgpu_info mgpu_info = { 145 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 146 }; 147 int amdgpu_ras_enable = -1; 148 uint amdgpu_ras_mask = 0xffffffff; 149 150 /** 151 * DOC: vramlimit (int) 152 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 153 */ 154 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 155 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 156 157 /** 158 * DOC: vis_vramlimit (int) 159 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 160 */ 161 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 162 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 163 164 /** 165 * DOC: gartsize (uint) 166 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 167 */ 168 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 169 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 170 171 /** 172 * DOC: gttsize (int) 173 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 174 * otherwise 3/4 RAM size). 175 */ 176 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 177 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 178 179 /** 180 * DOC: moverate (int) 181 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 182 */ 183 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 184 module_param_named(moverate, amdgpu_moverate, int, 0600); 185 186 /** 187 * DOC: benchmark (int) 188 * Run benchmarks. The default is 0 (Skip benchmarks). 189 */ 190 MODULE_PARM_DESC(benchmark, "Run benchmark"); 191 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 192 193 /** 194 * DOC: test (int) 195 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 196 */ 197 MODULE_PARM_DESC(test, "Run tests"); 198 module_param_named(test, amdgpu_testing, int, 0444); 199 200 /** 201 * DOC: audio (int) 202 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 203 */ 204 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 205 module_param_named(audio, amdgpu_audio, int, 0444); 206 207 /** 208 * DOC: disp_priority (int) 209 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 210 */ 211 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 212 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 213 214 /** 215 * DOC: hw_i2c (int) 216 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 217 */ 218 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 219 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 220 221 /** 222 * DOC: pcie_gen2 (int) 223 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 224 */ 225 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 226 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 227 228 /** 229 * DOC: msi (int) 230 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 231 */ 232 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 233 module_param_named(msi, amdgpu_msi, int, 0444); 234 235 /** 236 * DOC: lockup_timeout (string) 237 * Set GPU scheduler timeout value in ms. 238 * 239 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 240 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 241 * to default timeout. 242 * - With one value specified, the setting will apply to all non-compute jobs. 243 * - With multiple values specified, the first one will be for GFX. The second one is for Compute. 244 * And the third and fourth ones are for SDMA and Video. 245 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 246 * jobs is 10000. And there is no timeout enforced on compute jobs. 247 */ 248 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and no timeout for compute jobs), " 249 "format is [Non-Compute] or [GFX,Compute,SDMA,Video]"); 250 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 251 252 /** 253 * DOC: dpm (int) 254 * Override for dynamic power management setting 255 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 256 * The default is -1 (auto). 257 */ 258 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 259 module_param_named(dpm, amdgpu_dpm, int, 0444); 260 261 /** 262 * DOC: fw_load_type (int) 263 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 264 */ 265 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 266 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 267 268 /** 269 * DOC: aspm (int) 270 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 271 */ 272 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 273 module_param_named(aspm, amdgpu_aspm, int, 0444); 274 275 /** 276 * DOC: runpm (int) 277 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 278 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 279 */ 280 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 281 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 282 283 /** 284 * DOC: ip_block_mask (uint) 285 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 286 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 287 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 288 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 289 */ 290 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 291 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 292 293 /** 294 * DOC: bapm (int) 295 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 296 * The default -1 (auto, enabled) 297 */ 298 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 299 module_param_named(bapm, amdgpu_bapm, int, 0444); 300 301 /** 302 * DOC: deep_color (int) 303 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 304 */ 305 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 306 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 307 308 /** 309 * DOC: vm_size (int) 310 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 311 */ 312 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 313 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 314 315 /** 316 * DOC: vm_fragment_size (int) 317 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 318 */ 319 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 320 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 321 322 /** 323 * DOC: vm_block_size (int) 324 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 325 */ 326 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 327 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 328 329 /** 330 * DOC: vm_fault_stop (int) 331 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 332 */ 333 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 334 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 335 336 /** 337 * DOC: vm_debug (int) 338 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 339 */ 340 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 341 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 342 343 /** 344 * DOC: vm_update_mode (int) 345 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 346 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 347 */ 348 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 349 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 350 351 /** 352 * DOC: exp_hw_support (int) 353 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 354 */ 355 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 356 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 357 358 /** 359 * DOC: dc (int) 360 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 361 */ 362 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 363 module_param_named(dc, amdgpu_dc, int, 0444); 364 365 /** 366 * DOC: sched_jobs (int) 367 * Override the max number of jobs supported in the sw queue. The default is 32. 368 */ 369 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 370 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 371 372 /** 373 * DOC: sched_hw_submission (int) 374 * Override the max number of HW submissions. The default is 2. 375 */ 376 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 377 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 378 379 /** 380 * DOC: ppfeaturemask (uint) 381 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 382 * The default is the current set of stable power features. 383 */ 384 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 385 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 386 387 /** 388 * DOC: pcie_gen_cap (uint) 389 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 390 * The default is 0 (automatic for each asic). 391 */ 392 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 393 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 394 395 /** 396 * DOC: pcie_lane_cap (uint) 397 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 398 * The default is 0 (automatic for each asic). 399 */ 400 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 401 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 402 403 /** 404 * DOC: cg_mask (uint) 405 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 406 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 407 */ 408 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 409 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 410 411 /** 412 * DOC: pg_mask (uint) 413 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 414 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 415 */ 416 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 417 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 418 419 /** 420 * DOC: sdma_phase_quantum (uint) 421 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 422 */ 423 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 424 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 425 426 /** 427 * DOC: disable_cu (charp) 428 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 429 */ 430 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 431 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 432 433 /** 434 * DOC: virtual_display (charp) 435 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 436 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 437 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 438 * device at 26:00.0. The default is NULL. 439 */ 440 MODULE_PARM_DESC(virtual_display, 441 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 442 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 443 444 /** 445 * DOC: ngg (int) 446 * Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled). 447 */ 448 MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); 449 module_param_named(ngg, amdgpu_ngg, int, 0444); 450 451 /** 452 * DOC: prim_buf_per_se (int) 453 * Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 454 */ 455 MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); 456 module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); 457 458 /** 459 * DOC: pos_buf_per_se (int) 460 * Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx). 461 */ 462 MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); 463 module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); 464 465 /** 466 * DOC: cntl_sb_buf_per_se (int) 467 * Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx). 468 */ 469 MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); 470 module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); 471 472 /** 473 * DOC: param_buf_per_se (int) 474 * Override the size of Off-Chip Parameter Cache per Shader Engine in Byte. 475 * The default is 0 (depending on gfx). 476 */ 477 MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Parameter Cache per Shader Engine (default depending on gfx)"); 478 module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); 479 480 /** 481 * DOC: job_hang_limit (int) 482 * Set how much time allow a job hang and not drop it. The default is 0. 483 */ 484 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 485 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 486 487 /** 488 * DOC: lbpw (int) 489 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 490 */ 491 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 492 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 493 494 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 495 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 496 497 /** 498 * DOC: gpu_recovery (int) 499 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 500 */ 501 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 502 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 503 504 /** 505 * DOC: emu_mode (int) 506 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 507 */ 508 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 509 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 510 511 /** 512 * DOC: ras_enable (int) 513 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 514 */ 515 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 516 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 517 518 /** 519 * DOC: ras_mask (uint) 520 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 521 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 522 */ 523 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 524 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 525 526 /** 527 * DOC: si_support (int) 528 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 529 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 530 * otherwise using amdgpu driver. 531 */ 532 #ifdef CONFIG_DRM_AMDGPU_SI 533 534 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 535 int amdgpu_si_support = 0; 536 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 537 #else 538 int amdgpu_si_support = 1; 539 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 540 #endif 541 542 module_param_named(si_support, amdgpu_si_support, int, 0444); 543 #endif 544 545 /** 546 * DOC: cik_support (int) 547 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 548 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 549 * otherwise using amdgpu driver. 550 */ 551 #ifdef CONFIG_DRM_AMDGPU_CIK 552 553 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 554 int amdgpu_cik_support = 0; 555 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 556 #else 557 int amdgpu_cik_support = 1; 558 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 559 #endif 560 561 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 562 #endif 563 564 /** 565 * DOC: smu_memory_pool_size (uint) 566 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 567 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 568 */ 569 MODULE_PARM_DESC(smu_memory_pool_size, 570 "reserve gtt for smu debug usage, 0 = disable," 571 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 572 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 573 574 /** 575 * DOC: async_gfx_ring (int) 576 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 577 */ 578 MODULE_PARM_DESC(async_gfx_ring, 579 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 580 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 581 582 MODULE_PARM_DESC(mcbp, 583 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 584 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 585 586 MODULE_PARM_DESC(discovery, 587 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 588 module_param_named(discovery, amdgpu_discovery, int, 0444); 589 590 MODULE_PARM_DESC(mes, 591 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 592 module_param_named(mes, amdgpu_mes, int, 0444); 593 594 #ifdef CONFIG_HSA_AMD 595 /** 596 * DOC: sched_policy (int) 597 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 598 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 599 * assigns queues to HQDs. 600 */ 601 int sched_policy = KFD_SCHED_POLICY_HWS; 602 module_param(sched_policy, int, 0444); 603 MODULE_PARM_DESC(sched_policy, 604 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 605 606 /** 607 * DOC: hws_max_conc_proc (int) 608 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 609 * number of VMIDs assigned to the HWS, which is also the default. 610 */ 611 int hws_max_conc_proc = 8; 612 module_param(hws_max_conc_proc, int, 0444); 613 MODULE_PARM_DESC(hws_max_conc_proc, 614 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 615 616 /** 617 * DOC: cwsr_enable (int) 618 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 619 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 620 * disables it. 621 */ 622 int cwsr_enable = 1; 623 module_param(cwsr_enable, int, 0444); 624 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 625 626 /** 627 * DOC: max_num_of_queues_per_device (int) 628 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 629 * is 4096. 630 */ 631 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 632 module_param(max_num_of_queues_per_device, int, 0444); 633 MODULE_PARM_DESC(max_num_of_queues_per_device, 634 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 635 636 /** 637 * DOC: send_sigterm (int) 638 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 639 * but just print errors on dmesg. Setting 1 enables sending sigterm. 640 */ 641 int send_sigterm; 642 module_param(send_sigterm, int, 0444); 643 MODULE_PARM_DESC(send_sigterm, 644 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 645 646 /** 647 * DOC: debug_largebar (int) 648 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 649 * system. This limits the VRAM size reported to ROCm applications to the visible 650 * size, usually 256MB. 651 * Default value is 0, diabled. 652 */ 653 int debug_largebar; 654 module_param(debug_largebar, int, 0444); 655 MODULE_PARM_DESC(debug_largebar, 656 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 657 658 /** 659 * DOC: ignore_crat (int) 660 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 661 * table to get information about AMD APUs. This option can serve as a workaround on 662 * systems with a broken CRAT table. 663 */ 664 int ignore_crat; 665 module_param(ignore_crat, int, 0444); 666 MODULE_PARM_DESC(ignore_crat, 667 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 668 669 /** 670 * DOC: noretry (int) 671 * This parameter sets sh_mem_config.retry_disable. Default value, 0, enables retry. 672 * Setting 1 disables retry. 673 * Retry is needed for recoverable page faults. 674 */ 675 int noretry; 676 module_param(noretry, int, 0644); 677 MODULE_PARM_DESC(noretry, 678 "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled (default), 1 = retry disabled)"); 679 680 /** 681 * DOC: halt_if_hws_hang (int) 682 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 683 * Setting 1 enables halt on hang. 684 */ 685 int halt_if_hws_hang; 686 module_param(halt_if_hws_hang, int, 0644); 687 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 688 689 /** 690 * DOC: hws_gws_support(bool) 691 * Whether HWS support gws barriers. Default value: false (not supported) 692 * This will be replaced with a MEC firmware version check once firmware 693 * is ready 694 */ 695 bool hws_gws_support; 696 module_param(hws_gws_support, bool, 0444); 697 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 698 699 /** 700 * DOC: queue_preemption_timeout_ms (int) 701 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 702 */ 703 int queue_preemption_timeout_ms; 704 module_param(queue_preemption_timeout_ms, int, 0644); 705 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 706 #endif 707 708 /** 709 * DOC: dcfeaturemask (uint) 710 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 711 * The default is the current set of stable display features. 712 */ 713 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 714 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 715 716 /** 717 * DOC: abmlevel (uint) 718 * Override the default ABM (Adaptive Backlight Management) level used for DC 719 * enabled hardware. Requires DMCU to be supported and loaded. 720 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 721 * default. Values 1-4 control the maximum allowable brightness reduction via 722 * the ABM algorithm, with 1 being the least reduction and 4 being the most 723 * reduction. 724 * 725 * Defaults to 0, or disabled. Userspace can still override this level later 726 * after boot. 727 */ 728 uint amdgpu_dm_abm_level = 0; 729 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 730 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 731 732 static const struct pci_device_id pciidlist[] = { 733 #ifdef CONFIG_DRM_AMDGPU_SI 734 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 735 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 736 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 737 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 738 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 739 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 740 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 741 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 742 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 743 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 744 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 745 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 746 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 747 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 748 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 749 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 750 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 751 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 752 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 753 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 754 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 755 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 756 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 757 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 758 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 759 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 760 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 761 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 762 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 763 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 764 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 765 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 766 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 767 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 768 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 769 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 770 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 771 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 772 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 773 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 774 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 775 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 776 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 777 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 778 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 779 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 780 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 781 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 782 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 783 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 784 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 785 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 786 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 787 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 788 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 789 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 790 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 791 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 792 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 793 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 794 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 795 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 796 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 797 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 798 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 799 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 800 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 801 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 802 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 803 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 804 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 805 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 806 #endif 807 #ifdef CONFIG_DRM_AMDGPU_CIK 808 /* Kaveri */ 809 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 810 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 811 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 812 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 813 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 814 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 815 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 816 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 817 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 818 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 819 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 820 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 821 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 822 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 823 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 824 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 825 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 826 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 827 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 828 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 829 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 830 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 831 /* Bonaire */ 832 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 833 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 834 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 835 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 836 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 837 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 838 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 839 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 840 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 841 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 842 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 843 /* Hawaii */ 844 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 845 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 846 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 847 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 848 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 849 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 850 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 851 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 852 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 853 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 854 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 855 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 856 /* Kabini */ 857 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 858 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 859 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 860 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 861 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 862 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 863 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 864 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 865 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 866 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 867 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 868 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 869 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 870 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 871 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 872 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 873 /* mullins */ 874 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 875 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 876 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 877 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 878 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 879 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 881 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 884 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 890 #endif 891 /* topaz */ 892 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 893 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 894 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 895 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 896 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 897 /* tonga */ 898 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 899 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 900 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 901 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 902 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 903 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 904 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 905 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 906 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 907 /* fiji */ 908 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 909 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 910 /* carrizo */ 911 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 912 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 913 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 914 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 915 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 916 /* stoney */ 917 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 918 /* Polaris11 */ 919 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 920 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 921 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 922 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 923 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 924 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 925 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 926 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 927 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 928 /* Polaris10 */ 929 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 930 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 931 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 932 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 933 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 934 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 935 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 936 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 937 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 938 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 939 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 940 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 941 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 942 /* Polaris12 */ 943 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 944 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 945 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 946 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 947 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 948 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 949 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 950 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 951 /* VEGAM */ 952 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 953 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 954 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 955 /* Vega 10 */ 956 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 957 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 958 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 959 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 960 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 961 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 962 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 963 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 964 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 965 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 966 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 967 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 968 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 969 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 970 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 971 /* Vega 12 */ 972 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 973 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 974 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 975 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 976 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 977 /* Vega 20 */ 978 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 979 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 980 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 981 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 982 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 983 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 984 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 985 /* Raven */ 986 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 987 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 988 /* Navi10 */ 989 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 990 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 991 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 992 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 993 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 994 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 995 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 996 997 {0, 0, 0} 998 }; 999 1000 MODULE_DEVICE_TABLE(pci, pciidlist); 1001 1002 static struct drm_driver kms_driver; 1003 1004 static int amdgpu_pci_probe(struct pci_dev *pdev, 1005 const struct pci_device_id *ent) 1006 { 1007 struct drm_device *dev; 1008 unsigned long flags = ent->driver_data; 1009 int ret, retry = 0; 1010 bool supports_atomic = false; 1011 1012 if (!amdgpu_virtual_display && 1013 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1014 supports_atomic = true; 1015 1016 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1017 DRM_INFO("This hardware requires experimental hardware support.\n" 1018 "See modparam exp_hw_support\n"); 1019 return -ENODEV; 1020 } 1021 1022 /* Get rid of things like offb */ 1023 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, "amdgpudrmfb"); 1024 if (ret) 1025 return ret; 1026 1027 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1028 if (IS_ERR(dev)) 1029 return PTR_ERR(dev); 1030 1031 if (!supports_atomic) 1032 dev->driver_features &= ~DRIVER_ATOMIC; 1033 1034 ret = pci_enable_device(pdev); 1035 if (ret) 1036 goto err_free; 1037 1038 dev->pdev = pdev; 1039 1040 pci_set_drvdata(pdev, dev); 1041 1042 retry_init: 1043 ret = drm_dev_register(dev, ent->driver_data); 1044 if (ret == -EAGAIN && ++retry <= 3) { 1045 DRM_INFO("retry init %d\n", retry); 1046 /* Don't request EX mode too frequently which is attacking */ 1047 msleep(5000); 1048 goto retry_init; 1049 } else if (ret) 1050 goto err_pci; 1051 1052 return 0; 1053 1054 err_pci: 1055 pci_disable_device(pdev); 1056 err_free: 1057 drm_dev_put(dev); 1058 return ret; 1059 } 1060 1061 static void 1062 amdgpu_pci_remove(struct pci_dev *pdev) 1063 { 1064 struct drm_device *dev = pci_get_drvdata(pdev); 1065 1066 DRM_ERROR("Device removal is currently not supported outside of fbcon\n"); 1067 drm_dev_unplug(dev); 1068 drm_dev_put(dev); 1069 pci_disable_device(pdev); 1070 pci_set_drvdata(pdev, NULL); 1071 } 1072 1073 static void 1074 amdgpu_pci_shutdown(struct pci_dev *pdev) 1075 { 1076 struct drm_device *dev = pci_get_drvdata(pdev); 1077 struct amdgpu_device *adev = dev->dev_private; 1078 1079 /* if we are running in a VM, make sure the device 1080 * torn down properly on reboot/shutdown. 1081 * unfortunately we can't detect certain 1082 * hypervisors so just do this all the time. 1083 */ 1084 amdgpu_device_ip_suspend(adev); 1085 } 1086 1087 static int amdgpu_pmops_suspend(struct device *dev) 1088 { 1089 struct pci_dev *pdev = to_pci_dev(dev); 1090 1091 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1092 return amdgpu_device_suspend(drm_dev, true, true); 1093 } 1094 1095 static int amdgpu_pmops_resume(struct device *dev) 1096 { 1097 struct pci_dev *pdev = to_pci_dev(dev); 1098 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1099 1100 /* GPU comes up enabled by the bios on resume */ 1101 if (amdgpu_device_is_px(drm_dev)) { 1102 pm_runtime_disable(dev); 1103 pm_runtime_set_active(dev); 1104 pm_runtime_enable(dev); 1105 } 1106 1107 return amdgpu_device_resume(drm_dev, true, true); 1108 } 1109 1110 static int amdgpu_pmops_freeze(struct device *dev) 1111 { 1112 struct pci_dev *pdev = to_pci_dev(dev); 1113 1114 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1115 return amdgpu_device_suspend(drm_dev, false, true); 1116 } 1117 1118 static int amdgpu_pmops_thaw(struct device *dev) 1119 { 1120 struct pci_dev *pdev = to_pci_dev(dev); 1121 1122 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1123 return amdgpu_device_resume(drm_dev, false, true); 1124 } 1125 1126 static int amdgpu_pmops_poweroff(struct device *dev) 1127 { 1128 struct pci_dev *pdev = to_pci_dev(dev); 1129 1130 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1131 return amdgpu_device_suspend(drm_dev, true, true); 1132 } 1133 1134 static int amdgpu_pmops_restore(struct device *dev) 1135 { 1136 struct pci_dev *pdev = to_pci_dev(dev); 1137 1138 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1139 return amdgpu_device_resume(drm_dev, false, true); 1140 } 1141 1142 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1143 { 1144 struct pci_dev *pdev = to_pci_dev(dev); 1145 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1146 int ret; 1147 1148 if (!amdgpu_device_is_px(drm_dev)) { 1149 pm_runtime_forbid(dev); 1150 return -EBUSY; 1151 } 1152 1153 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1154 drm_kms_helper_poll_disable(drm_dev); 1155 1156 ret = amdgpu_device_suspend(drm_dev, false, false); 1157 pci_save_state(pdev); 1158 pci_disable_device(pdev); 1159 pci_ignore_hotplug(pdev); 1160 if (amdgpu_is_atpx_hybrid()) 1161 pci_set_power_state(pdev, PCI_D3cold); 1162 else if (!amdgpu_has_atpx_dgpu_power_cntl()) 1163 pci_set_power_state(pdev, PCI_D3hot); 1164 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1165 1166 return 0; 1167 } 1168 1169 static int amdgpu_pmops_runtime_resume(struct device *dev) 1170 { 1171 struct pci_dev *pdev = to_pci_dev(dev); 1172 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1173 int ret; 1174 1175 if (!amdgpu_device_is_px(drm_dev)) 1176 return -EINVAL; 1177 1178 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1179 1180 if (amdgpu_is_atpx_hybrid() || 1181 !amdgpu_has_atpx_dgpu_power_cntl()) 1182 pci_set_power_state(pdev, PCI_D0); 1183 pci_restore_state(pdev); 1184 ret = pci_enable_device(pdev); 1185 if (ret) 1186 return ret; 1187 pci_set_master(pdev); 1188 1189 ret = amdgpu_device_resume(drm_dev, false, false); 1190 drm_kms_helper_poll_enable(drm_dev); 1191 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1192 return 0; 1193 } 1194 1195 static int amdgpu_pmops_runtime_idle(struct device *dev) 1196 { 1197 struct pci_dev *pdev = to_pci_dev(dev); 1198 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1199 struct drm_crtc *crtc; 1200 1201 if (!amdgpu_device_is_px(drm_dev)) { 1202 pm_runtime_forbid(dev); 1203 return -EBUSY; 1204 } 1205 1206 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1207 if (crtc->enabled) { 1208 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1209 return -EBUSY; 1210 } 1211 } 1212 1213 pm_runtime_mark_last_busy(dev); 1214 pm_runtime_autosuspend(dev); 1215 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1216 return 1; 1217 } 1218 1219 long amdgpu_drm_ioctl(struct file *filp, 1220 unsigned int cmd, unsigned long arg) 1221 { 1222 struct drm_file *file_priv = filp->private_data; 1223 struct drm_device *dev; 1224 long ret; 1225 dev = file_priv->minor->dev; 1226 ret = pm_runtime_get_sync(dev->dev); 1227 if (ret < 0) 1228 return ret; 1229 1230 ret = drm_ioctl(filp, cmd, arg); 1231 1232 pm_runtime_mark_last_busy(dev->dev); 1233 pm_runtime_put_autosuspend(dev->dev); 1234 return ret; 1235 } 1236 1237 static const struct dev_pm_ops amdgpu_pm_ops = { 1238 .suspend = amdgpu_pmops_suspend, 1239 .resume = amdgpu_pmops_resume, 1240 .freeze = amdgpu_pmops_freeze, 1241 .thaw = amdgpu_pmops_thaw, 1242 .poweroff = amdgpu_pmops_poweroff, 1243 .restore = amdgpu_pmops_restore, 1244 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1245 .runtime_resume = amdgpu_pmops_runtime_resume, 1246 .runtime_idle = amdgpu_pmops_runtime_idle, 1247 }; 1248 1249 static int amdgpu_flush(struct file *f, fl_owner_t id) 1250 { 1251 struct drm_file *file_priv = f->private_data; 1252 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1253 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1254 1255 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1256 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1257 1258 return timeout >= 0 ? 0 : timeout; 1259 } 1260 1261 static const struct file_operations amdgpu_driver_kms_fops = { 1262 .owner = THIS_MODULE, 1263 .open = drm_open, 1264 .flush = amdgpu_flush, 1265 .release = drm_release, 1266 .unlocked_ioctl = amdgpu_drm_ioctl, 1267 .mmap = amdgpu_mmap, 1268 .poll = drm_poll, 1269 .read = drm_read, 1270 #ifdef CONFIG_COMPAT 1271 .compat_ioctl = amdgpu_kms_compat_ioctl, 1272 #endif 1273 }; 1274 1275 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1276 { 1277 struct drm_file *file; 1278 1279 if (!filp) 1280 return -EINVAL; 1281 1282 if (filp->f_op != &amdgpu_driver_kms_fops) { 1283 return -EINVAL; 1284 } 1285 1286 file = filp->private_data; 1287 *fpriv = file->driver_priv; 1288 return 0; 1289 } 1290 1291 int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) 1292 { 1293 char *input = amdgpu_lockup_timeout; 1294 char *timeout_setting = NULL; 1295 int index = 0; 1296 long timeout; 1297 int ret = 0; 1298 1299 /* 1300 * By default timeout for non compute jobs is 10000. 1301 * And there is no timeout enforced on compute jobs. 1302 */ 1303 adev->gfx_timeout = adev->sdma_timeout = adev->video_timeout = 10000; 1304 adev->compute_timeout = MAX_SCHEDULE_TIMEOUT; 1305 1306 if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1307 while ((timeout_setting = strsep(&input, ",")) && 1308 strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) { 1309 ret = kstrtol(timeout_setting, 0, &timeout); 1310 if (ret) 1311 return ret; 1312 1313 /* Invalidate 0 and negative values */ 1314 if (timeout <= 0) { 1315 index++; 1316 continue; 1317 } 1318 1319 switch (index++) { 1320 case 0: 1321 adev->gfx_timeout = timeout; 1322 break; 1323 case 1: 1324 adev->compute_timeout = timeout; 1325 break; 1326 case 2: 1327 adev->sdma_timeout = timeout; 1328 break; 1329 case 3: 1330 adev->video_timeout = timeout; 1331 break; 1332 default: 1333 break; 1334 } 1335 } 1336 /* 1337 * There is only one value specified and 1338 * it should apply to all non-compute jobs. 1339 */ 1340 if (index == 1) 1341 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; 1342 } 1343 1344 return ret; 1345 } 1346 1347 static bool 1348 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1349 bool in_vblank_irq, int *vpos, int *hpos, 1350 ktime_t *stime, ktime_t *etime, 1351 const struct drm_display_mode *mode) 1352 { 1353 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1354 stime, etime, mode); 1355 } 1356 1357 static struct drm_driver kms_driver = { 1358 .driver_features = 1359 DRIVER_USE_AGP | DRIVER_ATOMIC | 1360 DRIVER_GEM | 1361 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1362 .load = amdgpu_driver_load_kms, 1363 .open = amdgpu_driver_open_kms, 1364 .postclose = amdgpu_driver_postclose_kms, 1365 .lastclose = amdgpu_driver_lastclose_kms, 1366 .unload = amdgpu_driver_unload_kms, 1367 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1368 .enable_vblank = amdgpu_enable_vblank_kms, 1369 .disable_vblank = amdgpu_disable_vblank_kms, 1370 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1371 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1372 .irq_handler = amdgpu_irq_handler, 1373 .ioctls = amdgpu_ioctls_kms, 1374 .gem_free_object_unlocked = amdgpu_gem_object_free, 1375 .gem_open_object = amdgpu_gem_object_open, 1376 .gem_close_object = amdgpu_gem_object_close, 1377 .dumb_create = amdgpu_mode_dumb_create, 1378 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1379 .fops = &amdgpu_driver_kms_fops, 1380 1381 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1382 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1383 .gem_prime_export = amdgpu_gem_prime_export, 1384 .gem_prime_import = amdgpu_gem_prime_import, 1385 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 1386 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 1387 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 1388 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1389 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1390 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1391 1392 .name = DRIVER_NAME, 1393 .desc = DRIVER_DESC, 1394 .date = DRIVER_DATE, 1395 .major = KMS_DRIVER_MAJOR, 1396 .minor = KMS_DRIVER_MINOR, 1397 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1398 }; 1399 1400 static struct pci_driver amdgpu_kms_pci_driver = { 1401 .name = DRIVER_NAME, 1402 .id_table = pciidlist, 1403 .probe = amdgpu_pci_probe, 1404 .remove = amdgpu_pci_remove, 1405 .shutdown = amdgpu_pci_shutdown, 1406 .driver.pm = &amdgpu_pm_ops, 1407 }; 1408 1409 1410 1411 static int __init amdgpu_init(void) 1412 { 1413 int r; 1414 1415 if (vgacon_text_force()) { 1416 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1417 return -EINVAL; 1418 } 1419 1420 r = amdgpu_sync_init(); 1421 if (r) 1422 goto error_sync; 1423 1424 r = amdgpu_fence_slab_init(); 1425 if (r) 1426 goto error_fence; 1427 1428 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1429 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1430 amdgpu_register_atpx_handler(); 1431 1432 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1433 amdgpu_amdkfd_init(); 1434 1435 /* let modprobe override vga console setting */ 1436 return pci_register_driver(&amdgpu_kms_pci_driver); 1437 1438 error_fence: 1439 amdgpu_sync_fini(); 1440 1441 error_sync: 1442 return r; 1443 } 1444 1445 static void __exit amdgpu_exit(void) 1446 { 1447 amdgpu_amdkfd_fini(); 1448 pci_unregister_driver(&amdgpu_kms_pci_driver); 1449 amdgpu_unregister_atpx_handler(); 1450 amdgpu_sync_fini(); 1451 amdgpu_fence_slab_fini(); 1452 } 1453 1454 module_init(amdgpu_init); 1455 module_exit(amdgpu_exit); 1456 1457 MODULE_AUTHOR(DRIVER_AUTHOR); 1458 MODULE_DESCRIPTION(DRIVER_DESC); 1459 MODULE_LICENSE("GPL and additional rights"); 1460